320 lines
20 KiB
XML
320 lines
20 KiB
XML
<?xml version="1.0" encoding="utf-8"?>
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<?xml-stylesheet type="text/xsl" encoding="UTF-8" href="iform.xsl" version="1.0"?>
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<!DOCTYPE instructionsection PUBLIC "-//ARM//DTD instructionsection //EN" "iform-p.dtd">
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<!-- Copyright (c) 2010-2022 Arm Limited or its affiliates. All rights reserved. -->
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<!-- This document is Non-Confidential. This document may only be used and distributed in accordance with the terms of the agreement entered into by Arm and the party that Arm delivered this document to. -->
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<instructionsection id="LDMDB" title="LDMDB, LDMEA -- AArch32" type="instruction">
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<docvars>
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<docvar key="instr-class" value="general" />
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<docvar key="mnemonic" value="LDM" />
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</docvars>
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<heading>LDMDB, LDMEA</heading>
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<desc>
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<brief>
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<para>Load Multiple Decrement Before (Empty Ascending)</para>
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</brief>
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<authored>
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<para>Load Multiple Decrement Before (Empty Ascending) loads multiple registers from consecutive memory locations using an address from a base register. The consecutive memory locations end just below this address, and the address of the lowest of those locations can optionally be written back to the base register.</para>
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<para>The lowest-numbered register is loaded from the lowest memory address, through to the highest-numbered register from the highest memory address. See also <xref linkend="CHDDBEDG">Encoding of lists of general-purpose registers and the PC</xref>.</para>
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<para>Armv8.2 permits the deprecation of some Load Multiple ordering behaviors in AArch32 state, for more information see <xref linkend="v8.2.LSMAOC">FEAT_LSMAOC</xref>. The registers loaded can include the PC, causing a branch to a loaded address. This is an interworking branch, see <xref linkend="BEICJFEH">Pseudocode description of operations on the AArch32 general-purpose registers and the PC</xref>. Related system instructions are <xref linkend="A32T32-base.instructions.LDM_u">LDM (User registers)</xref> and <xref linkend="A32T32-base.instructions.LDM_e">LDM (exception return)</xref>.</para>
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</authored>
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<encodingnotes>
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<para>For more information about the <arm-defined-word>constrained unpredictable</arm-defined-word> behavior of this instruction, see <xref linkend="CJAEGDJC">Architectural Constraints on UNPREDICTABLE behaviors</xref>.</para>
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</encodingnotes>
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</desc>
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<operationalnotes>
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<para>If CPSR.DIT is 1, the timing of this instruction is insensitive to the value of the data being loaded or stored.</para>
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</operationalnotes>
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<alias_list howmany="0"></alias_list>
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<classes>
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<classesintro count="2">
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<txt>It has encodings from the following instruction sets:</txt>
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<txt> A32 (</txt>
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<a href="#iclass_a1">A1</a>
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<txt>)</txt>
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<txt> and </txt>
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<txt> T32 (</txt>
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<a href="#iclass_t1">T1</a>
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<txt>)</txt>
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<txt>.</txt>
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</classesintro>
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<iclass name="A1" oneof="2" id="iclass_a1" no_encodings="1" isa="A32">
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<docvars>
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<docvar key="armarmheading" value="A1" />
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<docvar key="instr-class" value="general" />
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<docvar key="isa" value="A32" />
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<docvar key="mnemonic" value="LDM" />
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</docvars>
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<iclassintro count="1"></iclassintro>
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<regdiagram form="32" psname="aarch32/instrs/LDMDB/A1_A.txt" tworows="1">
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<box hibit="31" width="4" name="cond" usename="1" settings="4" constraint="!= 1111">
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<c colspan="4">!= 1111</c>
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</box>
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<box hibit="27" width="3" settings="3">
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<c>1</c>
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<c>0</c>
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<c>0</c>
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</box>
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<box hibit="24" name="P" settings="1">
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<c>1</c>
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</box>
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<box hibit="23" name="U" settings="1">
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<c>0</c>
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</box>
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<box hibit="22" name="op" settings="1">
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<c>0</c>
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</box>
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<box hibit="21" name="W" usename="1">
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<c></c>
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</box>
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<box hibit="20" name="L" settings="1">
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<c>1</c>
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</box>
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<box hibit="19" width="4" name="Rn" usename="1">
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<c colspan="4"></c>
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</box>
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<box hibit="15" width="16" name="register_list" usename="1">
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<c colspan="16"></c>
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</box>
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</regdiagram>
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<encoding name="LDMDB_A1" oneofinclass="1" oneof="2" label="A1">
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<docvars>
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<docvar key="armarmheading" value="A1" />
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<docvar key="instr-class" value="general" />
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<docvar key="isa" value="A32" />
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<docvar key="mnemonic" value="LDM" />
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</docvars>
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<asmtemplate comment="Preferred syntax"><text>LDMDB</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}"><c></a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}"><q></a><text>}</text><text> </text><a link="sa_rn" hover="General-purpose base register (field "Rn")"><Rn></a><a link="sa_0d33" hover="The address adjusted by the size of data loaded is written back to the base register (field "W")">{!}</a><text>, </text><a link="sa_registers_1" hover="List of one or more registers to be loaded"><registers></a></asmtemplate>
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<asmtemplate comment="Alternate syntax, Empty Ascending stack"><text>LDMEA</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}"><c></a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}"><q></a><text>}</text><text> </text><a link="sa_rn" hover="General-purpose base register (field "Rn")"><Rn></a><a link="sa_0d33" hover="The address adjusted by the size of data loaded is written back to the base register (field "W")">{!}</a><text>, </text><a link="sa_registers_1" hover="List of one or more registers to be loaded"><registers></a></asmtemplate>
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</encoding>
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<ps_section howmany="1">
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<ps name="aarch32/instrs/LDMDB/A1_A.txt" mylink="aarch32.instrs.LDMDB.A1_A.txt" enclabels="" sections="1" secttype="noheading">
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<pstext mayhavelinks="1" section="Decode" rep_section="decode">n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rn); registers = register_list; wback = (W == '1');
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if n == 15 || <a link="impl-shared.BitCount.1" file="shared_pseudocode.xml" hover="function: integer BitCount(bits(N) x)">BitCount</a>(registers) < 1 then UNPREDICTABLE;
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if wback && registers<n> == '1' then UNPREDICTABLE;</pstext>
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</ps>
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</ps_section>
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<constrained_unpredictables encoding="A1" ps_block="Decode">
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<cu_case>
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<cu_cause>
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<pstext mayhavelinks="1">wback && registers<n> == '1'</pstext>
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</cu_cause>
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<cu_type constraint="Constraint_UNDEF" />
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<cu_type constraint="Constraint_NOP" />
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<cu_type>
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<cu_type_text>The instruction performs all of the loads using the specified addressing mode and the content of the register that is written back is <arm-defined-word>unknown</arm-defined-word>. In addition, if an exception occurs during such an instruction, the base address might be corrupted so that the instruction cannot be repeated.</cu_type_text>
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</cu_type>
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</cu_case>
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<cu_case>
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<cu_cause>
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<pstext mayhavelinks="1">BitCount(registers) < 1</pstext>
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</cu_cause>
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<cu_type constraint="Constraint_UNDEF" />
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<cu_type constraint="Constraint_NOP" />
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<cu_type>
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<cu_type_text>The instruction executes as <instruction>LDM</instruction> with the same addressing mode but targeting an unspecified set of registers. These registers might include R15. If the instruction specifies writeback, the modification to the base address on writeback might differ from the number of registers loaded.</cu_type_text>
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</cu_type>
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</cu_case>
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</constrained_unpredictables>
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</iclass>
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<iclass name="T1" oneof="2" id="iclass_t1" no_encodings="1" isa="T32">
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<docvars>
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<docvar key="armarmheading" value="T1" />
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<docvar key="instr-class" value="general" />
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<docvar key="isa" value="T32" />
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<docvar key="mnemonic" value="LDM" />
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</docvars>
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<iclassintro count="1"></iclassintro>
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<regdiagram form="16x2" psname="aarch32/instrs/LDMDB/T1_A.txt">
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<box hibit="31" width="7" settings="7">
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<c>1</c>
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<c>1</c>
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<c>1</c>
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<c>0</c>
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<c>1</c>
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<c>0</c>
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<c>0</c>
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</box>
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<box hibit="24" width="2" name="opc" settings="2">
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<c>1</c>
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<c>0</c>
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</box>
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<box hibit="22" settings="1">
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<c>0</c>
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</box>
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<box hibit="21" name="W" usename="1">
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<c></c>
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</box>
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<box hibit="20" name="L" settings="1">
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<c>1</c>
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</box>
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<box hibit="19" width="4" name="Rn" usename="1">
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<c colspan="4"></c>
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</box>
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<box hibit="15" name="P" usename="1">
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<c></c>
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</box>
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<box hibit="14" name="M" usename="1">
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<c></c>
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</box>
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<box hibit="13" width="14" name="register_list" usename="1">
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<c colspan="14"></c>
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</box>
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</regdiagram>
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<encoding name="LDMDB_T1" oneofinclass="1" oneof="2" label="T1">
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<docvars>
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<docvar key="armarmheading" value="T1" />
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<docvar key="instr-class" value="general" />
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<docvar key="isa" value="T32" />
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<docvar key="mnemonic" value="LDM" />
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</docvars>
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<asmtemplate comment="Preferred syntax"><text>LDMDB</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}"><c></a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}"><q></a><text>}</text><text> </text><a link="sa_rn" hover="General-purpose base register (field "Rn")"><Rn></a><a link="sa_0d33" hover="The address adjusted by the size of data loaded is written back to the base register (field "W")">{!}</a><text>, </text><a link="sa_registers" hover="List of one or more registers to be loaded (field "register_list")"><registers></a></asmtemplate>
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<asmtemplate comment="Alternate syntax, Empty Ascending stack"><text>LDMEA</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}"><c></a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}"><q></a><text>}</text><text> </text><a link="sa_rn" hover="General-purpose base register (field "Rn")"><Rn></a><a link="sa_0d33" hover="The address adjusted by the size of data loaded is written back to the base register (field "W")">{!}</a><text>, </text><a link="sa_registers" hover="List of one or more registers to be loaded (field "register_list")"><registers></a></asmtemplate>
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</encoding>
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<ps_section howmany="1">
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<ps name="aarch32/instrs/LDMDB/T1_A.txt" mylink="aarch32.instrs.LDMDB.T1_A.txt" enclabels="" sections="1" secttype="noheading">
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<pstext mayhavelinks="1" section="Decode" rep_section="decode">n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rn); registers = P:M:register_list; wback = (W == '1');
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if n == 15 || <a link="impl-shared.BitCount.1" file="shared_pseudocode.xml" hover="function: integer BitCount(bits(N) x)">BitCount</a>(registers) < 2 || (P == '1' && M == '1') then UNPREDICTABLE;
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if wback && registers<n> == '1' then UNPREDICTABLE;
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if registers<13> == '1' then UNPREDICTABLE;
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if registers<15> == '1' && <a link="impl-aarch32.InITBlock.0" file="shared_pseudocode.xml" hover="function: boolean InITBlock()">InITBlock</a>() && !<a link="impl-aarch32.LastInITBlock.0" file="shared_pseudocode.xml" hover="function: boolean LastInITBlock()">LastInITBlock</a>() then UNPREDICTABLE;</pstext>
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</ps>
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</ps_section>
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<constrained_unpredictables encoding="T1" ps_block="Decode">
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<cu_case>
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<cu_cause>
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<pstext mayhavelinks="1">wback && registers<n> == '1'</pstext>
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</cu_cause>
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<cu_type constraint="Constraint_UNDEF" />
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<cu_type constraint="Constraint_NOP" />
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<cu_type>
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<cu_type_text>The instruction performs all of the loads using the specified addressing mode and the content of the register that is written back is <arm-defined-word>unknown</arm-defined-word>. In addition, if an exception occurs during such an instruction, the base address might be corrupted so that the instruction cannot be repeated.</cu_type_text>
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</cu_type>
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</cu_case>
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<cu_case>
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<cu_cause>
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<pstext mayhavelinks="1">BitCount(registers) < 1</pstext>
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</cu_cause>
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<cu_type constraint="Constraint_UNDEF" />
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<cu_type constraint="Constraint_NOP" />
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<cu_type>
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<cu_type_text>The instruction executes as <instruction>LDM</instruction> with the same addressing mode but targeting an unspecified set of registers. These registers might include R15. If the instruction specifies writeback, the modification to the base address on writeback might differ from the number of registers loaded.</cu_type_text>
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</cu_type>
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</cu_case>
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<cu_case>
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<cu_cause>
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<pstext mayhavelinks="1">BitCount(registers) == 1</pstext>
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</cu_cause>
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<cu_type constraint="Constraint_UNDEF" />
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<cu_type constraint="Constraint_NOP" />
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<cu_type>
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<cu_type_text>The instruction loads a single register using the specified addressing modes.</cu_type_text>
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</cu_type>
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<cu_type>
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<cu_type_text>The instruction executes as <instruction>LDM</instruction> with the same addressing mode but targeting an unspecified set of registers. These registers might include R15.</cu_type_text>
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</cu_type>
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</cu_case>
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<cu_case>
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<cu_cause>
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<pstext mayhavelinks="1">registers<13> == '1'</pstext>
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</cu_cause>
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<cu_type constraint="Constraint_UNDEF" />
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<cu_type constraint="Constraint_NOP" />
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<cu_type>
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<cu_type_text>The instruction performs all of the loads using the specified addressing mode, but R13 is <arm-defined-word>unknown</arm-defined-word>.</cu_type_text>
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</cu_type>
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</cu_case>
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<cu_case>
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<cu_cause>
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<pstext mayhavelinks="1">P == '1' && M == '1'</pstext>
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</cu_cause>
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<cu_type constraint="Constraint_UNDEF" />
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<cu_type constraint="Constraint_NOP" />
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<cu_type>
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<cu_type_text>The instruction loads the register list and either R14 or R15, both R14 and R15, or neither of these registers.</cu_type_text>
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</cu_type>
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</cu_case>
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</constrained_unpredictables>
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</iclass>
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</classes>
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<explanations scope="all">
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<explanation enclist="LDMDB_A1, LDMDB_T1" symboldefcount="1">
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<symbol link="sa_c"><c></symbol>
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<account encodedin="">
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<intro>
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<para>See <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
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</intro>
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</account>
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</explanation>
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<explanation enclist="LDMDB_A1, LDMDB_T1" symboldefcount="1">
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<symbol link="sa_q"><q></symbol>
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<account encodedin="">
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<intro>
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<para>See <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
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</intro>
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</account>
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</explanation>
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<explanation enclist="LDMDB_A1, LDMDB_T1" symboldefcount="1">
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<symbol link="sa_rn"><Rn></symbol>
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<account encodedin="Rn">
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<intro>
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<para>Is the general-purpose base register, encoded in the "Rn" field.</para>
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</intro>
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</account>
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</explanation>
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<explanation enclist="LDMDB_A1, LDMDB_T1" symboldefcount="1">
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<symbol link="sa_0d33">!</symbol>
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<account encodedin="W">
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<intro>
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<para>The address adjusted by the size of the data loaded is written back to the base register. If specified, it is encoded in the "W" field as 1, otherwise this field defaults to 0.</para>
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</intro>
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</account>
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</explanation>
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<explanation enclist="LDMDB_A1" symboldefcount="1">
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<symbol link="sa_registers_1"><registers></symbol>
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<account encodedin="">
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<docvars>
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<docvar key="armarmheading" value="A1" />
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<docvar key="isa" value="A32" />
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</docvars>
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<intro>
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<para>For encoding A1: is a list of one or more registers to be loaded, separated by commas and surrounded by { and }.</para>
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<para>The PC can be in the list.</para>
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<para>Arm deprecates using these instructions with both the LR and the PC in the list.</para>
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</intro>
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</account>
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</explanation>
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<explanation enclist="LDMDB_T1" symboldefcount="2">
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<symbol link="sa_registers"><registers></symbol>
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<account encodedin="register_list">
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<docvars>
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<docvar key="armarmheading" value="T1" />
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<docvar key="isa" value="T32" />
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</docvars>
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<intro>
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<para>For encoding T1: is a list of one or more registers to be loaded, separated by commas and surrounded by { and }. The registers in the list must be in the range R0-R12, encoded in the "register_list" field, and can optionally contain one of the LR or the PC. If the LR is in the list, the "M" field is set to 1, otherwise it defaults to 0. If the PC is in the list, the "P" field is set to 1, otherwise it defaults to 0.</para>
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<para>If the PC is in the list:</para>
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<list type="unordered">
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<listitem><content>The LR must not be in the list.</content></listitem>
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<listitem><content>The instruction must be either outside any IT block, or the last instruction in an IT block.</content></listitem>
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</list>
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</intro>
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</account>
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</explanation>
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</explanations>
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<ps_section howmany="1">
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<ps name="aarch32/instrs/LDMDB/Op_A.txt" mylink="execute" enclabels="" sections="1" secttype="Operation">
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<pstext mayhavelinks="1" section="Execute" rep_section="execute">if <a link="impl-aarch32.ConditionPassed.0" file="shared_pseudocode.xml" hover="function: boolean ConditionPassed()">ConditionPassed</a>() then
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EncodingSpecificOperations();
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address = <a link="impl-aarch32.R.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) R[integer n]">R</a>[n] - 4*<a link="impl-shared.BitCount.1" file="shared_pseudocode.xml" hover="function: integer BitCount(bits(N) x)">BitCount</a>(registers);
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for i = 0 to 14
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if registers<i> == '1' then
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<a link="impl-aarch32.R.write.1" file="shared_pseudocode.xml" hover="accessor: R[integer n] = bits(32) value">R</a>[i] = <a link="impl-aarch32.MemS.read.2" file="shared_pseudocode.xml" hover="accessor: bits(8*size) MemS[bits(32) address, integer size]">MemS</a>[address,4]; address = address + 4;
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if registers<15> == '1' then
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<a link="impl-aarch32.LoadWritePC.1" file="shared_pseudocode.xml" hover="function: LoadWritePC(bits(32) address)">LoadWritePC</a>(<a link="impl-aarch32.MemS.read.2" file="shared_pseudocode.xml" hover="accessor: bits(8*size) MemS[bits(32) address, integer size]">MemS</a>[address,4]);
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if wback && registers<n> == '0' then <a link="impl-aarch32.R.write.1" file="shared_pseudocode.xml" hover="accessor: R[integer n] = bits(32) value">R</a>[n] = <a link="impl-aarch32.R.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) R[integer n]">R</a>[n] - 4*<a link="impl-shared.BitCount.1" file="shared_pseudocode.xml" hover="function: integer BitCount(bits(N) x)">BitCount</a>(registers);
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if wback && registers<n> == '1' then <a link="impl-aarch32.R.write.1" file="shared_pseudocode.xml" hover="accessor: R[integer n] = bits(32) value">R</a>[n] = bits(32) UNKNOWN;</pstext>
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</ps>
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</ps_section>
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</instructionsection>
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