8366 lines
310 KiB
XML
8366 lines
310 KiB
XML
<?xml version="1.0" encoding="utf-8"?>
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<?xml-stylesheet type="text/xsl" encoding="UTF-8" href="accounts.xsl" version="1.0"?>
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<!DOCTYPE accounts PUBLIC "-//ARM//DTD accounts //EN" "accounts.dtd">
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<!-- Copyright (c) 2010-2022 Arm Limited or its affiliates. All rights reserved. -->
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<!-- This document is Non-Confidential. This document may only be used and distributed in accordance with the terms of the agreement entered into by Arm and the party that Arm delivered this document to. -->
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<accounts>
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<account iclass="ldstsimdfp" symbol="+/-" iclass_long="Advanced SIMD and floating-point load/store">
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<encodings>
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<encoding encname="VLDR_A1_D" />
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<encoding encname="VLDR_A1_H" />
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<encoding encname="VLDR_A1_S" />
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<encoding encname="VLDR_l_A1_D" />
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<encoding encname="VLDR_l_A1_H" />
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<encoding encname="VLDR_l_A1_S" />
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<encoding encname="VSTR_A1_D" />
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<encoding encname="VSTR_A1_H" />
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<encoding encname="VSTR_A1_S" />
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</encodings>
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<orig>Specifies the offset is added to or subtracted from the base register, defaulting to + if omitted and encoded in the "U" field, where 0->-, 1->+.</orig>
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<definition encodedin="U">
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<intro>Specifies the offset is added to or subtracted from the base register, defaulting to + if omitted and </intro>
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<table class="valuetable">
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<tgroup cols="2">
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<thead>
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<row>
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<entry class="bitfield" bitwidth="1">U</entry>
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<entry class="symbol">+/-</entry>
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</row>
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</thead>
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<tbody>
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<row>
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<entry class="bitfield">0</entry>
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<entry class="symbol">-</entry>
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</row>
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<row>
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<entry class="bitfield">1</entry>
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<entry class="symbol">+</entry>
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</row>
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</tbody>
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</tgroup>
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</table>
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</definition>
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</account>
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<account iclass="simdfp_ldst" symbol="+/-" iclass_long="Advanced SIMD and floating-point load/store">
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<encodings>
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<encoding encname="VLDR_T1_D" />
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<encoding encname="VLDR_T1_H" />
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<encoding encname="VLDR_T1_S" />
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<encoding encname="VLDR_l_T1_D" />
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<encoding encname="VLDR_l_T1_H" />
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<encoding encname="VLDR_l_T1_S" />
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<encoding encname="VSTR_T1_D" />
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<encoding encname="VSTR_T1_H" />
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<encoding encname="VSTR_T1_S" />
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</encodings>
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<orig>Specifies the offset is added to or subtracted from the base register, defaulting to + if omitted and encoded in the "U" field, where 0->-, 1->+.</orig>
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<definition encodedin="U">
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<intro>Specifies the offset is added to or subtracted from the base register, defaulting to + if omitted and </intro>
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<table class="valuetable">
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<tgroup cols="2">
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<thead>
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<row>
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<entry class="bitfield" bitwidth="1">U</entry>
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<entry class="symbol">+/-</entry>
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</row>
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</thead>
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<tbody>
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<row>
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<entry class="bitfield">0</entry>
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<entry class="symbol">-</entry>
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</row>
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<row>
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<entry class="bitfield">1</entry>
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<entry class="symbol">+</entry>
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</row>
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</tbody>
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</tgroup>
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</table>
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</definition>
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</account>
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<account iclass="floatdpmac" symbol="<bt>" iclass_long="Advanced SIMD and floating-point multiply with accumulate">
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<encodings>
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<encoding encname="VFMA_bfs_A1_Q" />
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</encodings>
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<orig>Is the bottom or top element specifier, encoded in "Q" where 0->B, 1->T.</orig>
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<definition encodedin="Q">
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<intro>Is the bottom or top element specifier, </intro>
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<table class="valuetable">
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<tgroup cols="2">
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<thead>
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<row>
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<entry class="bitfield" bitwidth="1">Q</entry>
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<entry class="symbol"><bt></entry>
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</row>
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</thead>
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<tbody>
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<row>
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<entry class="bitfield">0</entry>
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<entry class="symbol">B</entry>
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</row>
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<row>
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<entry class="bitfield">1</entry>
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<entry class="symbol">T</entry>
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</row>
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</tbody>
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</tgroup>
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</table>
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</definition>
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</account>
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<account iclass="tfloatdpmac" symbol="<bt>" iclass_long="Advanced SIMD and floating-point multiply with accumulate">
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<encodings>
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<encoding encname="VFMA_bfs_T1_Q" />
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</encodings>
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<orig>Is the bottom or top element specifier, encoded in "Q" where 0->B, 1->T.</orig>
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<definition encodedin="Q">
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<intro>Is the bottom or top element specifier, </intro>
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<table class="valuetable">
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<tgroup cols="2">
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<thead>
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<row>
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<entry class="bitfield" bitwidth="1">Q</entry>
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<entry class="symbol"><bt></entry>
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</row>
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</thead>
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<tbody>
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<row>
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<entry class="bitfield">0</entry>
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<entry class="symbol">B</entry>
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</row>
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<row>
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<entry class="bitfield">1</entry>
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<entry class="symbol">T</entry>
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</row>
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</tbody>
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</tgroup>
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</table>
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</definition>
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</account>
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<account iclass="floatdpmac" symbol="<rotate>" iclass_long="Advanced SIMD and floating-point multiply with accumulate">
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<encodings>
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<encoding encname="VCMLA_s_A1_DH" />
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<encoding encname="VCMLA_s_A1_DS" />
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<encoding encname="VCMLA_s_A1_QH" />
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<encoding encname="VCMLA_s_A1_QS" />
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</encodings>
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<orig>Is the rotation to be applied to elements in the second SIMD&FP source register, encoded in "rot", where 00->0, 01->90, 10->180, 11->270.</orig>
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<definition encodedin="rot">
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<intro>Is the rotation to be applied to elements in the second SIMD&FP source register, </intro>
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<table class="valuetable">
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<tgroup cols="2">
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<thead>
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<row>
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<entry class="bitfield" bitwidth="2">rot</entry>
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<entry class="symbol"><rotate></entry>
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</row>
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</thead>
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<tbody>
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<row>
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<entry class="bitfield">00</entry>
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<entry class="symbol">0</entry>
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</row>
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<row>
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<entry class="bitfield">01</entry>
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<entry class="symbol">90</entry>
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</row>
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<row>
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<entry class="bitfield">10</entry>
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<entry class="symbol">180</entry>
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</row>
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<row>
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<entry class="bitfield">11</entry>
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<entry class="symbol">270</entry>
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</row>
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</tbody>
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</tgroup>
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</table>
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</definition>
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</account>
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<account iclass="tfloatdpmac" symbol="<rotate>" iclass_long="Advanced SIMD and floating-point multiply with accumulate">
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<encodings>
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<encoding encname="VCMLA_s_T1_DH" />
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<encoding encname="VCMLA_s_T1_DS" />
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<encoding encname="VCMLA_s_T1_QH" />
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<encoding encname="VCMLA_s_T1_QS" />
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</encodings>
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<orig>Is the rotation to be applied to elements in the second SIMD&FP source register, encoded in "rot", where 00->0, 01->90, 10->180, 11->270.</orig>
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<definition encodedin="rot">
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<intro>Is the rotation to be applied to elements in the second SIMD&FP source register, </intro>
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<table class="valuetable">
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<tgroup cols="2">
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<thead>
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<row>
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<entry class="bitfield" bitwidth="2">rot</entry>
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<entry class="symbol"><rotate></entry>
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</row>
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</thead>
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<tbody>
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<row>
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<entry class="bitfield">00</entry>
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<entry class="symbol">0</entry>
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</row>
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<row>
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<entry class="bitfield">01</entry>
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<entry class="symbol">90</entry>
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</row>
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<row>
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<entry class="bitfield">10</entry>
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<entry class="symbol">180</entry>
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</row>
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<row>
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<entry class="bitfield">11</entry>
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<entry class="symbol">270</entry>
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</row>
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</tbody>
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</tgroup>
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</table>
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</definition>
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</account>
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<account iclass="ldv_ssall" symbol="<size>" iclass_long="Advanced SIMD load single structure to all lanes">
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<encodings>
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<encoding encname="VLD1_a_A1_nowb" />
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<encoding encname="VLD1_a_A1_posti" />
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<encoding encname="VLD1_a_A1_postr" />
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<encoding encname="VLD2_a_A1_nowb" />
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<encoding encname="VLD2_a_A1_posti" />
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<encoding encname="VLD2_a_A1_postr" />
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<encoding encname="VLD3_a_A1_nowb" />
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<encoding encname="VLD3_a_A1_posti" />
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<encoding encname="VLD3_a_A1_postr" />
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</encodings>
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<orig>Is the data size, encoded in "size", where 00->8, 01->16, 10->32, otherwise UNDEFINED.</orig>
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<definition encodedin="size">
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<intro>Is the data size, </intro>
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<table class="valuetable">
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<tgroup cols="2">
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<thead>
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<row>
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<entry class="bitfield" bitwidth="2">size</entry>
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<entry class="symbol"><size></entry>
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</row>
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</thead>
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<tbody>
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<row>
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<entry class="bitfield">00</entry>
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<entry class="symbol">8</entry>
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</row>
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<row>
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<entry class="bitfield">01</entry>
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<entry class="symbol">16</entry>
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</row>
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<row>
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<entry class="bitfield">10</entry>
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<entry class="symbol">32</entry>
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</row>
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<row>
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<entry class="bitfield">11</entry>
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<entry class="symbol">RESERVED</entry>
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</row>
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</tbody>
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</tgroup>
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</table>
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</definition>
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</account>
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<account iclass="asimldall" symbol="<size>" iclass_long="Advanced SIMD load single structure to all lanes">
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<encodings>
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<encoding encname="VLD1_a_T1_nowb" />
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<encoding encname="VLD1_a_T1_posti" />
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<encoding encname="VLD1_a_T1_postr" />
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<encoding encname="VLD2_a_T1_nowb" />
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<encoding encname="VLD2_a_T1_posti" />
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<encoding encname="VLD2_a_T1_postr" />
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<encoding encname="VLD3_a_T1_nowb" />
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<encoding encname="VLD3_a_T1_posti" />
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<encoding encname="VLD3_a_T1_postr" />
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</encodings>
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<orig>Is the data size, encoded in "size", where 00->8, 01->16, 10->32, otherwise UNDEFINED.</orig>
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<definition encodedin="size">
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<intro>Is the data size, </intro>
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<table class="valuetable">
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<tgroup cols="2">
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<thead>
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<row>
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<entry class="bitfield" bitwidth="2">size</entry>
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<entry class="symbol"><size></entry>
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</row>
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</thead>
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<tbody>
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<row>
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<entry class="bitfield">00</entry>
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<entry class="symbol">8</entry>
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</row>
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<row>
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<entry class="bitfield">01</entry>
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<entry class="symbol">16</entry>
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</row>
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<row>
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<entry class="bitfield">10</entry>
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<entry class="symbol">32</entry>
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</row>
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<row>
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<entry class="bitfield">11</entry>
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<entry class="symbol">RESERVED</entry>
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</row>
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</tbody>
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</tgroup>
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</table>
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</definition>
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</account>
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<account iclass="ldv_ssall" symbol="<size>" iclass_long="Advanced SIMD load single structure to all lanes">
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<encodings>
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<encoding encname="VLD4_a_A1_nowb" />
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<encoding encname="VLD4_a_A1_posti" />
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<encoding encname="VLD4_a_A1_postr" />
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</encodings>
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<orig>Is the data size, encoded in "size", where 00->8, 01->16, 1x->32, otherwise UNDEFINED.</orig>
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<definition encodedin="size">
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<intro>Is the data size, </intro>
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<table class="valuetable">
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<tgroup cols="2">
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<thead>
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<row>
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<entry class="bitfield" bitwidth="2">size</entry>
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<entry class="symbol"><size></entry>
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</row>
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</thead>
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<tbody>
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<row>
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<entry class="bitfield">00</entry>
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<entry class="symbol">8</entry>
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</row>
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<row>
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<entry class="bitfield">01</entry>
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<entry class="symbol">16</entry>
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</row>
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<row>
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<entry class="bitfield">1x</entry>
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<entry class="symbol">32</entry>
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</row>
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</tbody>
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</tgroup>
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</table>
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</definition>
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</account>
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<account iclass="asimldall" symbol="<size>" iclass_long="Advanced SIMD load single structure to all lanes">
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<encodings>
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<encoding encname="VLD4_a_T1_nowb" />
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<encoding encname="VLD4_a_T1_posti" />
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<encoding encname="VLD4_a_T1_postr" />
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</encodings>
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<orig>Is the data size, encoded in "size", where 00->8, 01->16, 1x->32, otherwise UNDEFINED.</orig>
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<definition encodedin="size">
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<intro>Is the data size, </intro>
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<table class="valuetable">
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<tgroup cols="2">
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<thead>
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<row>
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<entry class="bitfield" bitwidth="2">size</entry>
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<entry class="symbol"><size></entry>
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</row>
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</thead>
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<tbody>
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<row>
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<entry class="bitfield">00</entry>
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<entry class="symbol">8</entry>
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</row>
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<row>
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<entry class="bitfield">01</entry>
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<entry class="symbol">16</entry>
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</row>
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<row>
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<entry class="bitfield">1x</entry>
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<entry class="symbol">32</entry>
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</row>
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</tbody>
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</tgroup>
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</table>
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</definition>
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</account>
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<account iclass="ldstv_ms" symbol="<size>" iclass_long="Advanced SIMD load/store multiple structures">
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<encodings>
|
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<encoding encname="VLD1_m_A1_nowb" />
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|
<encoding encname="VLD1_m_A1_posti" />
|
|
<encoding encname="VLD1_m_A1_postr" />
|
|
<encoding encname="VLD1_m_A2_nowb" />
|
|
<encoding encname="VLD1_m_A2_posti" />
|
|
<encoding encname="VLD1_m_A2_postr" />
|
|
<encoding encname="VLD1_m_A3_nowb" />
|
|
<encoding encname="VLD1_m_A3_posti" />
|
|
<encoding encname="VLD1_m_A3_postr" />
|
|
<encoding encname="VLD1_m_A4_nowb" />
|
|
<encoding encname="VLD1_m_A4_posti" />
|
|
<encoding encname="VLD1_m_A4_postr" />
|
|
<encoding encname="VST1_m_A1_nowb" />
|
|
<encoding encname="VST1_m_A1_posti" />
|
|
<encoding encname="VST1_m_A1_postr" />
|
|
<encoding encname="VST1_m_A2_nowb" />
|
|
<encoding encname="VST1_m_A2_posti" />
|
|
<encoding encname="VST1_m_A2_postr" />
|
|
<encoding encname="VST1_m_A3_nowb" />
|
|
<encoding encname="VST1_m_A3_posti" />
|
|
<encoding encname="VST1_m_A3_postr" />
|
|
<encoding encname="VST1_m_A4_nowb" />
|
|
<encoding encname="VST1_m_A4_posti" />
|
|
<encoding encname="VST1_m_A4_postr" />
|
|
</encodings>
|
|
<orig>Is the data size, encoded in "size", where 00->8, 01->16, 10->32, 11->64.</orig>
|
|
<definition encodedin="size">
|
|
<intro>Is the data size, </intro>
|
|
<table class="valuetable">
|
|
<tgroup cols="2">
|
|
<thead>
|
|
<row>
|
|
<entry class="bitfield" bitwidth="2">size</entry>
|
|
<entry class="symbol"><size></entry>
|
|
</row>
|
|
</thead>
|
|
<tbody>
|
|
<row>
|
|
<entry class="bitfield">00</entry>
|
|
<entry class="symbol">8</entry>
|
|
</row>
|
|
<row>
|
|
<entry class="bitfield">01</entry>
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|
<entry class="symbol">16</entry>
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</row>
|
|
<row>
|
|
<entry class="bitfield">10</entry>
|
|
<entry class="symbol">32</entry>
|
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</row>
|
|
<row>
|
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<entry class="bitfield">11</entry>
|
|
<entry class="symbol">64</entry>
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</row>
|
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</tbody>
|
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</tgroup>
|
|
</table>
|
|
</definition>
|
|
</account>
|
|
<account iclass="asimldstms" symbol="<size>" iclass_long="Advanced SIMD load/store multiple structures">
|
|
<encodings>
|
|
<encoding encname="VLD1_m_T1_nowb" />
|
|
<encoding encname="VLD1_m_T1_posti" />
|
|
<encoding encname="VLD1_m_T1_postr" />
|
|
<encoding encname="VLD1_m_T2_nowb" />
|
|
<encoding encname="VLD1_m_T2_posti" />
|
|
<encoding encname="VLD1_m_T2_postr" />
|
|
<encoding encname="VLD1_m_T3_nowb" />
|
|
<encoding encname="VLD1_m_T3_posti" />
|
|
<encoding encname="VLD1_m_T3_postr" />
|
|
<encoding encname="VLD1_m_T4_nowb" />
|
|
<encoding encname="VLD1_m_T4_posti" />
|
|
<encoding encname="VLD1_m_T4_postr" />
|
|
<encoding encname="VST1_m_T1_nowb" />
|
|
<encoding encname="VST1_m_T1_posti" />
|
|
<encoding encname="VST1_m_T1_postr" />
|
|
<encoding encname="VST1_m_T2_nowb" />
|
|
<encoding encname="VST1_m_T2_posti" />
|
|
<encoding encname="VST1_m_T2_postr" />
|
|
<encoding encname="VST1_m_T3_nowb" />
|
|
<encoding encname="VST1_m_T3_posti" />
|
|
<encoding encname="VST1_m_T3_postr" />
|
|
<encoding encname="VST1_m_T4_nowb" />
|
|
<encoding encname="VST1_m_T4_posti" />
|
|
<encoding encname="VST1_m_T4_postr" />
|
|
</encodings>
|
|
<orig>Is the data size, encoded in "size", where 00->8, 01->16, 10->32, 11->64.</orig>
|
|
<definition encodedin="size">
|
|
<intro>Is the data size, </intro>
|
|
<table class="valuetable">
|
|
<tgroup cols="2">
|
|
<thead>
|
|
<row>
|
|
<entry class="bitfield" bitwidth="2">size</entry>
|
|
<entry class="symbol"><size></entry>
|
|
</row>
|
|
</thead>
|
|
<tbody>
|
|
<row>
|
|
<entry class="bitfield">00</entry>
|
|
<entry class="symbol">8</entry>
|
|
</row>
|
|
<row>
|
|
<entry class="bitfield">01</entry>
|
|
<entry class="symbol">16</entry>
|
|
</row>
|
|
<row>
|
|
<entry class="bitfield">10</entry>
|
|
<entry class="symbol">32</entry>
|
|
</row>
|
|
<row>
|
|
<entry class="bitfield">11</entry>
|
|
<entry class="symbol">64</entry>
|
|
</row>
|
|
</tbody>
|
|
</tgroup>
|
|
</table>
|
|
</definition>
|
|
</account>
|
|
<account iclass="ldstv_ms" symbol="<size>" iclass_long="Advanced SIMD load/store multiple structures">
|
|
<encodings>
|
|
<encoding encname="VLD2_m_A1_nowb" />
|
|
<encoding encname="VLD2_m_A1_posti" />
|
|
<encoding encname="VLD2_m_A1_postr" />
|
|
<encoding encname="VLD2_m_A2_nowb" />
|
|
<encoding encname="VLD2_m_A2_posti" />
|
|
<encoding encname="VLD2_m_A2_postr" />
|
|
<encoding encname="VLD3_m_A1_nowb" />
|
|
<encoding encname="VLD3_m_A1_posti" />
|
|
<encoding encname="VLD3_m_A1_postr" />
|
|
<encoding encname="VLD4_m_A1_nowb" />
|
|
<encoding encname="VLD4_m_A1_posti" />
|
|
<encoding encname="VLD4_m_A1_postr" />
|
|
<encoding encname="VST2_m_A1_nowb" />
|
|
<encoding encname="VST2_m_A1_posti" />
|
|
<encoding encname="VST2_m_A1_postr" />
|
|
<encoding encname="VST2_m_A2_nowb" />
|
|
<encoding encname="VST2_m_A2_posti" />
|
|
<encoding encname="VST2_m_A2_postr" />
|
|
<encoding encname="VST3_m_A1_nowb" />
|
|
<encoding encname="VST3_m_A1_posti" />
|
|
<encoding encname="VST3_m_A1_postr" />
|
|
<encoding encname="VST4_m_A1_nowb" />
|
|
<encoding encname="VST4_m_A1_posti" />
|
|
<encoding encname="VST4_m_A1_postr" />
|
|
</encodings>
|
|
<orig>Is the data size, encoded in "size", where 00->8, 01->16, 10->32, otherwise UNDEFINED.</orig>
|
|
<definition encodedin="size">
|
|
<intro>Is the data size, </intro>
|
|
<table class="valuetable">
|
|
<tgroup cols="2">
|
|
<thead>
|
|
<row>
|
|
<entry class="bitfield" bitwidth="2">size</entry>
|
|
<entry class="symbol"><size></entry>
|
|
</row>
|
|
</thead>
|
|
<tbody>
|
|
<row>
|
|
<entry class="bitfield">00</entry>
|
|
<entry class="symbol">8</entry>
|
|
</row>
|
|
<row>
|
|
<entry class="bitfield">01</entry>
|
|
<entry class="symbol">16</entry>
|
|
</row>
|
|
<row>
|
|
<entry class="bitfield">10</entry>
|
|
<entry class="symbol">32</entry>
|
|
</row>
|
|
<row>
|
|
<entry class="bitfield">11</entry>
|
|
<entry class="symbol">RESERVED</entry>
|
|
</row>
|
|
</tbody>
|
|
</tgroup>
|
|
</table>
|
|
</definition>
|
|
</account>
|
|
<account iclass="asimldstms" symbol="<size>" iclass_long="Advanced SIMD load/store multiple structures">
|
|
<encodings>
|
|
<encoding encname="VLD2_m_T1_nowb" />
|
|
<encoding encname="VLD2_m_T1_posti" />
|
|
<encoding encname="VLD2_m_T1_postr" />
|
|
<encoding encname="VLD2_m_T2_nowb" />
|
|
<encoding encname="VLD2_m_T2_posti" />
|
|
<encoding encname="VLD2_m_T2_postr" />
|
|
<encoding encname="VLD3_m_T1_nowb" />
|
|
<encoding encname="VLD3_m_T1_posti" />
|
|
<encoding encname="VLD3_m_T1_postr" />
|
|
<encoding encname="VLD4_m_T1_nowb" />
|
|
<encoding encname="VLD4_m_T1_posti" />
|
|
<encoding encname="VLD4_m_T1_postr" />
|
|
<encoding encname="VST2_m_T1_nowb" />
|
|
<encoding encname="VST2_m_T1_posti" />
|
|
<encoding encname="VST2_m_T1_postr" />
|
|
<encoding encname="VST2_m_T2_nowb" />
|
|
<encoding encname="VST2_m_T2_posti" />
|
|
<encoding encname="VST2_m_T2_postr" />
|
|
<encoding encname="VST3_m_T1_nowb" />
|
|
<encoding encname="VST3_m_T1_posti" />
|
|
<encoding encname="VST3_m_T1_postr" />
|
|
<encoding encname="VST4_m_T1_nowb" />
|
|
<encoding encname="VST4_m_T1_posti" />
|
|
<encoding encname="VST4_m_T1_postr" />
|
|
</encodings>
|
|
<orig>Is the data size, encoded in "size", where 00->8, 01->16, 10->32, otherwise UNDEFINED.</orig>
|
|
<definition encodedin="size">
|
|
<intro>Is the data size, </intro>
|
|
<table class="valuetable">
|
|
<tgroup cols="2">
|
|
<thead>
|
|
<row>
|
|
<entry class="bitfield" bitwidth="2">size</entry>
|
|
<entry class="symbol"><size></entry>
|
|
</row>
|
|
</thead>
|
|
<tbody>
|
|
<row>
|
|
<entry class="bitfield">00</entry>
|
|
<entry class="symbol">8</entry>
|
|
</row>
|
|
<row>
|
|
<entry class="bitfield">01</entry>
|
|
<entry class="symbol">16</entry>
|
|
</row>
|
|
<row>
|
|
<entry class="bitfield">10</entry>
|
|
<entry class="symbol">32</entry>
|
|
</row>
|
|
<row>
|
|
<entry class="bitfield">11</entry>
|
|
<entry class="symbol">RESERVED</entry>
|
|
</row>
|
|
</tbody>
|
|
</tgroup>
|
|
</table>
|
|
</definition>
|
|
</account>
|
|
<account iclass="ldstv_ssone" symbol="<size>" iclass_long="Advanced SIMD load/store single structure to one lane">
|
|
<encodings>
|
|
<encoding encname="VLD1_1_A1_nowb" />
|
|
<encoding encname="VLD1_1_A1_posti" />
|
|
<encoding encname="VLD1_1_A1_postr" />
|
|
<encoding encname="VLD1_1_A2_nowb" />
|
|
<encoding encname="VLD1_1_A2_posti" />
|
|
<encoding encname="VLD1_1_A2_postr" />
|
|
<encoding encname="VLD1_1_A3_nowb" />
|
|
<encoding encname="VLD1_1_A3_posti" />
|
|
<encoding encname="VLD1_1_A3_postr" />
|
|
<encoding encname="VLD2_1_A1_nowb" />
|
|
<encoding encname="VLD2_1_A1_posti" />
|
|
<encoding encname="VLD2_1_A1_postr" />
|
|
<encoding encname="VLD2_1_A2_nowb" />
|
|
<encoding encname="VLD2_1_A2_posti" />
|
|
<encoding encname="VLD2_1_A2_postr" />
|
|
<encoding encname="VLD2_1_A3_nowb" />
|
|
<encoding encname="VLD2_1_A3_posti" />
|
|
<encoding encname="VLD2_1_A3_postr" />
|
|
<encoding encname="VLD3_1_A1_nowb" />
|
|
<encoding encname="VLD3_1_A1_posti" />
|
|
<encoding encname="VLD3_1_A1_postr" />
|
|
<encoding encname="VLD3_1_A2_nowb" />
|
|
<encoding encname="VLD3_1_A2_posti" />
|
|
<encoding encname="VLD3_1_A2_postr" />
|
|
<encoding encname="VLD3_1_A3_nowb" />
|
|
<encoding encname="VLD3_1_A3_posti" />
|
|
<encoding encname="VLD3_1_A3_postr" />
|
|
<encoding encname="VLD4_1_A1_nowb" />
|
|
<encoding encname="VLD4_1_A1_posti" />
|
|
<encoding encname="VLD4_1_A1_postr" />
|
|
<encoding encname="VLD4_1_A2_nowb" />
|
|
<encoding encname="VLD4_1_A2_posti" />
|
|
<encoding encname="VLD4_1_A2_postr" />
|
|
<encoding encname="VLD4_1_A3_nowb" />
|
|
<encoding encname="VLD4_1_A3_posti" />
|
|
<encoding encname="VLD4_1_A3_postr" />
|
|
<encoding encname="VST1_1_A1_nowb" />
|
|
<encoding encname="VST1_1_A1_posti" />
|
|
<encoding encname="VST1_1_A1_postr" />
|
|
<encoding encname="VST1_1_A2_nowb" />
|
|
<encoding encname="VST1_1_A2_posti" />
|
|
<encoding encname="VST1_1_A2_postr" />
|
|
<encoding encname="VST1_1_A3_nowb" />
|
|
<encoding encname="VST1_1_A3_posti" />
|
|
<encoding encname="VST1_1_A3_postr" />
|
|
<encoding encname="VST2_1_A1_nowb" />
|
|
<encoding encname="VST2_1_A1_posti" />
|
|
<encoding encname="VST2_1_A1_postr" />
|
|
<encoding encname="VST2_1_A2_nowb" />
|
|
<encoding encname="VST2_1_A2_posti" />
|
|
<encoding encname="VST2_1_A2_postr" />
|
|
<encoding encname="VST2_1_A3_nowb" />
|
|
<encoding encname="VST2_1_A3_posti" />
|
|
<encoding encname="VST2_1_A3_postr" />
|
|
<encoding encname="VST3_1_A1_nowb" />
|
|
<encoding encname="VST3_1_A1_posti" />
|
|
<encoding encname="VST3_1_A1_postr" />
|
|
<encoding encname="VST3_1_A2_nowb" />
|
|
<encoding encname="VST3_1_A2_posti" />
|
|
<encoding encname="VST3_1_A2_postr" />
|
|
<encoding encname="VST3_1_A3_nowb" />
|
|
<encoding encname="VST3_1_A3_posti" />
|
|
<encoding encname="VST3_1_A3_postr" />
|
|
<encoding encname="VST4_1_A1_nowb" />
|
|
<encoding encname="VST4_1_A1_posti" />
|
|
<encoding encname="VST4_1_A1_postr" />
|
|
<encoding encname="VST4_1_A2_nowb" />
|
|
<encoding encname="VST4_1_A2_posti" />
|
|
<encoding encname="VST4_1_A2_postr" />
|
|
<encoding encname="VST4_1_A3_nowb" />
|
|
<encoding encname="VST4_1_A3_posti" />
|
|
<encoding encname="VST4_1_A3_postr" />
|
|
</encodings>
|
|
<orig>Is the data size, encoded in "size", where 00->8, 01->16, 10->32.</orig>
|
|
<definition encodedin="size">
|
|
<intro>Is the data size, </intro>
|
|
<table class="valuetable">
|
|
<tgroup cols="2">
|
|
<thead>
|
|
<row>
|
|
<entry class="bitfield" bitwidth="2">size</entry>
|
|
<entry class="symbol"><size></entry>
|
|
</row>
|
|
</thead>
|
|
<tbody>
|
|
<row>
|
|
<entry class="bitfield">00</entry>
|
|
<entry class="symbol">8</entry>
|
|
</row>
|
|
<row>
|
|
<entry class="bitfield">01</entry>
|
|
<entry class="symbol">16</entry>
|
|
</row>
|
|
<row>
|
|
<entry class="bitfield">10</entry>
|
|
<entry class="symbol">32</entry>
|
|
</row>
|
|
</tbody>
|
|
</tgroup>
|
|
</table>
|
|
</definition>
|
|
</account>
|
|
<account iclass="asimldstss" symbol="<size>" iclass_long="Advanced SIMD load/store single structure to one lane">
|
|
<encodings>
|
|
<encoding encname="VLD1_1_T1_nowb" />
|
|
<encoding encname="VLD1_1_T1_posti" />
|
|
<encoding encname="VLD1_1_T1_postr" />
|
|
<encoding encname="VLD1_1_T2_nowb" />
|
|
<encoding encname="VLD1_1_T2_posti" />
|
|
<encoding encname="VLD1_1_T2_postr" />
|
|
<encoding encname="VLD1_1_T3_nowb" />
|
|
<encoding encname="VLD1_1_T3_posti" />
|
|
<encoding encname="VLD1_1_T3_postr" />
|
|
<encoding encname="VLD2_1_T1_nowb" />
|
|
<encoding encname="VLD2_1_T1_posti" />
|
|
<encoding encname="VLD2_1_T1_postr" />
|
|
<encoding encname="VLD2_1_T2_nowb" />
|
|
<encoding encname="VLD2_1_T2_posti" />
|
|
<encoding encname="VLD2_1_T2_postr" />
|
|
<encoding encname="VLD2_1_T3_nowb" />
|
|
<encoding encname="VLD2_1_T3_posti" />
|
|
<encoding encname="VLD2_1_T3_postr" />
|
|
<encoding encname="VLD3_1_T1_nowb" />
|
|
<encoding encname="VLD3_1_T1_posti" />
|
|
<encoding encname="VLD3_1_T1_postr" />
|
|
<encoding encname="VLD3_1_T2_nowb" />
|
|
<encoding encname="VLD3_1_T2_posti" />
|
|
<encoding encname="VLD3_1_T2_postr" />
|
|
<encoding encname="VLD3_1_T3_nowb" />
|
|
<encoding encname="VLD3_1_T3_posti" />
|
|
<encoding encname="VLD3_1_T3_postr" />
|
|
<encoding encname="VLD4_1_T1_nowb" />
|
|
<encoding encname="VLD4_1_T1_posti" />
|
|
<encoding encname="VLD4_1_T1_postr" />
|
|
<encoding encname="VLD4_1_T2_nowb" />
|
|
<encoding encname="VLD4_1_T2_posti" />
|
|
<encoding encname="VLD4_1_T2_postr" />
|
|
<encoding encname="VLD4_1_T3_nowb" />
|
|
<encoding encname="VLD4_1_T3_posti" />
|
|
<encoding encname="VLD4_1_T3_postr" />
|
|
<encoding encname="VST1_1_T1_nowb" />
|
|
<encoding encname="VST1_1_T1_posti" />
|
|
<encoding encname="VST1_1_T1_postr" />
|
|
<encoding encname="VST1_1_T2_nowb" />
|
|
<encoding encname="VST1_1_T2_posti" />
|
|
<encoding encname="VST1_1_T2_postr" />
|
|
<encoding encname="VST1_1_T3_nowb" />
|
|
<encoding encname="VST1_1_T3_posti" />
|
|
<encoding encname="VST1_1_T3_postr" />
|
|
<encoding encname="VST2_1_T1_nowb" />
|
|
<encoding encname="VST2_1_T1_posti" />
|
|
<encoding encname="VST2_1_T1_postr" />
|
|
<encoding encname="VST2_1_T2_nowb" />
|
|
<encoding encname="VST2_1_T2_posti" />
|
|
<encoding encname="VST2_1_T2_postr" />
|
|
<encoding encname="VST2_1_T3_nowb" />
|
|
<encoding encname="VST2_1_T3_posti" />
|
|
<encoding encname="VST2_1_T3_postr" />
|
|
<encoding encname="VST3_1_T1_nowb" />
|
|
<encoding encname="VST3_1_T1_posti" />
|
|
<encoding encname="VST3_1_T1_postr" />
|
|
<encoding encname="VST3_1_T2_nowb" />
|
|
<encoding encname="VST3_1_T2_posti" />
|
|
<encoding encname="VST3_1_T2_postr" />
|
|
<encoding encname="VST3_1_T3_nowb" />
|
|
<encoding encname="VST3_1_T3_posti" />
|
|
<encoding encname="VST3_1_T3_postr" />
|
|
<encoding encname="VST4_1_T1_nowb" />
|
|
<encoding encname="VST4_1_T1_posti" />
|
|
<encoding encname="VST4_1_T1_postr" />
|
|
<encoding encname="VST4_1_T2_nowb" />
|
|
<encoding encname="VST4_1_T2_posti" />
|
|
<encoding encname="VST4_1_T2_postr" />
|
|
<encoding encname="VST4_1_T3_nowb" />
|
|
<encoding encname="VST4_1_T3_posti" />
|
|
<encoding encname="VST4_1_T3_postr" />
|
|
</encodings>
|
|
<orig>Is the data size, encoded in "size", where 00->8, 01->16, 10->32.</orig>
|
|
<definition encodedin="size">
|
|
<intro>Is the data size, </intro>
|
|
<table class="valuetable">
|
|
<tgroup cols="2">
|
|
<thead>
|
|
<row>
|
|
<entry class="bitfield" bitwidth="2">size</entry>
|
|
<entry class="symbol"><size></entry>
|
|
</row>
|
|
</thead>
|
|
<tbody>
|
|
<row>
|
|
<entry class="bitfield">00</entry>
|
|
<entry class="symbol">8</entry>
|
|
</row>
|
|
<row>
|
|
<entry class="bitfield">01</entry>
|
|
<entry class="symbol">16</entry>
|
|
</row>
|
|
<row>
|
|
<entry class="bitfield">10</entry>
|
|
<entry class="symbol">32</entry>
|
|
</row>
|
|
</tbody>
|
|
</tgroup>
|
|
</table>
|
|
</definition>
|
|
</account>
|
|
<account iclass="simd1reg_imm" symbol="<dt>" iclass_long="Advanced SIMD one register and modified immediate">
|
|
<encodings>
|
|
<encoding encname="VMOV_i_A4_D" />
|
|
<encoding encname="VMOV_i_A4_Q" />
|
|
</encodings>
|
|
<orig>The data type, encoded in "cmode", where 110x->I32, 1110->I8, 1111->F32.</orig>
|
|
<definition encodedin="cmode">
|
|
<intro>The data type, </intro>
|
|
<table class="valuetable">
|
|
<tgroup cols="2">
|
|
<thead>
|
|
<row>
|
|
<entry class="bitfield" bitwidth="4">cmode</entry>
|
|
<entry class="symbol"><dt></entry>
|
|
</row>
|
|
</thead>
|
|
<tbody>
|
|
<row>
|
|
<entry class="bitfield">110x</entry>
|
|
<entry class="symbol">I32</entry>
|
|
</row>
|
|
<row>
|
|
<entry class="bitfield">1110</entry>
|
|
<entry class="symbol">I8</entry>
|
|
</row>
|
|
<row>
|
|
<entry class="bitfield">1111</entry>
|
|
<entry class="symbol">F32</entry>
|
|
</row>
|
|
</tbody>
|
|
</tgroup>
|
|
</table>
|
|
</definition>
|
|
</account>
|
|
<account iclass="simd_1r_imm" symbol="<dt>" iclass_long="Advanced SIMD one register and modified immediate">
|
|
<encodings>
|
|
<encoding encname="VMOV_i_T4_D" />
|
|
<encoding encname="VMOV_i_T4_Q" />
|
|
</encodings>
|
|
<orig>The data type, encoded in "cmode", where 110x->I32, 1110->I8, 1111->F32.</orig>
|
|
<definition encodedin="cmode">
|
|
<intro>The data type, </intro>
|
|
<table class="valuetable">
|
|
<tgroup cols="2">
|
|
<thead>
|
|
<row>
|
|
<entry class="bitfield" bitwidth="4">cmode</entry>
|
|
<entry class="symbol"><dt></entry>
|
|
</row>
|
|
</thead>
|
|
<tbody>
|
|
<row>
|
|
<entry class="bitfield">110x</entry>
|
|
<entry class="symbol">I32</entry>
|
|
</row>
|
|
<row>
|
|
<entry class="bitfield">1110</entry>
|
|
<entry class="symbol">I8</entry>
|
|
</row>
|
|
<row>
|
|
<entry class="bitfield">1111</entry>
|
|
<entry class="symbol">F32</entry>
|
|
</row>
|
|
</tbody>
|
|
</tgroup>
|
|
</table>
|
|
</definition>
|
|
</account>
|
|
<account iclass="simd3reg_diff" symbol="<dt>" iclass_long="Advanced SIMD three registers of different lengths">
|
|
<encodings>
|
|
<encoding encname="VABAL_A1" />
|
|
<encoding encname="VABDL_i_A1" />
|
|
<encoding encname="VMLAL_i_A1" />
|
|
<encoding encname="VMLSL_i_A1" />
|
|
</encodings>
|
|
<orig>Is the data type for the elements of the operands, encoded in "U:size", where 000->S8, 001->S16, 010->S32, 100->U8, 101->U16, 110->U32</orig>
|
|
<definition encodedin="U:size">
|
|
<intro>Is the data type for the elements of the operands, </intro>
|
|
<table class="valuetable">
|
|
<tgroup cols="3">
|
|
<thead>
|
|
<row>
|
|
<entry class="bitfield" bitwidth="1">U</entry>
|
|
<entry class="bitfield" bitwidth="2">size</entry>
|
|
<entry class="symbol"><dt></entry>
|
|
</row>
|
|
</thead>
|
|
<tbody>
|
|
<row>
|
|
<entry class="bitfield">0</entry>
|
|
<entry class="bitfield">00</entry>
|
|
<entry class="symbol">S8</entry>
|
|
</row>
|
|
<row>
|
|
<entry class="bitfield">0</entry>
|
|
<entry class="bitfield">01</entry>
|
|
<entry class="symbol">S16</entry>
|
|
</row>
|
|
<row>
|
|
<entry class="bitfield">0</entry>
|
|
<entry class="bitfield">10</entry>
|
|
<entry class="symbol">S32</entry>
|
|
</row>
|
|
<row>
|
|
<entry class="bitfield">1</entry>
|
|
<entry class="bitfield">00</entry>
|
|
<entry class="symbol">U8</entry>
|
|
</row>
|
|
<row>
|
|
<entry class="bitfield">1</entry>
|
|
<entry class="bitfield">01</entry>
|
|
<entry class="symbol">U16</entry>
|
|
</row>
|
|
<row>
|
|
<entry class="bitfield">1</entry>
|
|
<entry class="bitfield">10</entry>
|
|
<entry class="symbol">U32</entry>
|
|
</row>
|
|
</tbody>
|
|
</tgroup>
|
|
</table>
|
|
</definition>
|
|
</account>
|
|
<account iclass="simd_3diff" symbol="<dt>" iclass_long="Advanced SIMD three registers of different lengths">
|
|
<encodings>
|
|
<encoding encname="VABAL_T1" />
|
|
<encoding encname="VABDL_i_T1" />
|
|
<encoding encname="VMLAL_i_T1" />
|
|
<encoding encname="VMLSL_i_T1" />
|
|
</encodings>
|
|
<orig>Is the data type for the elements of the operands, encoded in "U:size", where 000->S8, 001->S16, 010->S32, 100->U8, 101->U16, 110->U32</orig>
|
|
<definition encodedin="U:size">
|
|
<intro>Is the data type for the elements of the operands, </intro>
|
|
<table class="valuetable">
|
|
<tgroup cols="3">
|
|
<thead>
|
|
<row>
|
|
<entry class="bitfield" bitwidth="1">U</entry>
|
|
<entry class="bitfield" bitwidth="2">size</entry>
|
|
<entry class="symbol"><dt></entry>
|
|
</row>
|
|
</thead>
|
|
<tbody>
|
|
<row>
|
|
<entry class="bitfield">0</entry>
|
|
<entry class="bitfield">00</entry>
|
|
<entry class="symbol">S8</entry>
|
|
</row>
|
|
<row>
|
|
<entry class="bitfield">0</entry>
|
|
<entry class="bitfield">01</entry>
|
|
<entry class="symbol">S16</entry>
|
|
</row>
|
|
<row>
|
|
<entry class="bitfield">0</entry>
|
|
<entry class="bitfield">10</entry>
|
|
<entry class="symbol">S32</entry>
|
|
</row>
|
|
<row>
|
|
<entry class="bitfield">1</entry>
|
|
<entry class="bitfield">00</entry>
|
|
<entry class="symbol">U8</entry>
|
|
</row>
|
|
<row>
|
|
<entry class="bitfield">1</entry>
|
|
<entry class="bitfield">01</entry>
|
|
<entry class="symbol">U16</entry>
|
|
</row>
|
|
<row>
|
|
<entry class="bitfield">1</entry>
|
|
<entry class="bitfield">10</entry>
|
|
<entry class="symbol">U32</entry>
|
|
</row>
|
|
</tbody>
|
|
</tgroup>
|
|
</table>
|
|
</definition>
|
|
</account>
|
|
<account iclass="simd3reg_diff" symbol="<dt>" iclass_long="Advanced SIMD three registers of different lengths">
|
|
<encodings>
|
|
<encoding encname="VMULL_i_A1" />
|
|
</encodings>
|
|
<orig>Is the data type for the elements of the operands, encoded in "op:U:size", where 0000->S8, 0001->S16, 0010->S32, 0100->U8, 0101->U16, 0110->U32, 1000->P8, 1010->P64</orig>
|
|
<definition encodedin="op:U:size">
|
|
<intro>Is the data type for the elements of the operands, </intro>
|
|
<table class="valuetable">
|
|
<tgroup cols="4">
|
|
<thead>
|
|
<row>
|
|
<entry class="bitfield" bitwidth="1">op</entry>
|
|
<entry class="bitfield" bitwidth="1">U</entry>
|
|
<entry class="bitfield" bitwidth="2">size</entry>
|
|
<entry class="symbol"><dt></entry>
|
|
</row>
|
|
</thead>
|
|
<tbody>
|
|
<row>
|
|
<entry class="bitfield">0</entry>
|
|
<entry class="bitfield">0</entry>
|
|
<entry class="bitfield">00</entry>
|
|
<entry class="symbol">S8</entry>
|
|
</row>
|
|
<row>
|
|
<entry class="bitfield">0</entry>
|
|
<entry class="bitfield">0</entry>
|
|
<entry class="bitfield">01</entry>
|
|
<entry class="symbol">S16</entry>
|
|
</row>
|
|
<row>
|
|
<entry class="bitfield">0</entry>
|
|
<entry class="bitfield">0</entry>
|
|
<entry class="bitfield">10</entry>
|
|
<entry class="symbol">S32</entry>
|
|
</row>
|
|
<row>
|
|
<entry class="bitfield">0</entry>
|
|
<entry class="bitfield">1</entry>
|
|
<entry class="bitfield">00</entry>
|
|
<entry class="symbol">U8</entry>
|
|
</row>
|
|
<row>
|
|
<entry class="bitfield">0</entry>
|
|
<entry class="bitfield">1</entry>
|
|
<entry class="bitfield">01</entry>
|
|
<entry class="symbol">U16</entry>
|
|
</row>
|
|
<row>
|
|
<entry class="bitfield">0</entry>
|
|
<entry class="bitfield">1</entry>
|
|
<entry class="bitfield">10</entry>
|
|
<entry class="symbol">U32</entry>
|
|
</row>
|
|
<row>
|
|
<entry class="bitfield">1</entry>
|
|
<entry class="bitfield">0</entry>
|
|
<entry class="bitfield">00</entry>
|
|
<entry class="symbol">P8</entry>
|
|
</row>
|
|
<row>
|
|
<entry class="bitfield">1</entry>
|
|
<entry class="bitfield">0</entry>
|
|
<entry class="bitfield">10</entry>
|
|
<entry class="symbol">P64</entry>
|
|
</row>
|
|
</tbody>
|
|
</tgroup>
|
|
</table>
|
|
</definition>
|
|
</account>
|
|
<account iclass="simd_3diff" symbol="<dt>" iclass_long="Advanced SIMD three registers of different lengths">
|
|
<encodings>
|
|
<encoding encname="VMULL_i_T1" />
|
|
</encodings>
|
|
<orig>Is the data type for the elements of the operands, encoded in "op:U:size", where 0000->S8, 0001->S16, 0010->S32, 0100->U8, 0101->U16, 0110->U32, 1000->P8, 1010->P64</orig>
|
|
<definition encodedin="op:U:size">
|
|
<intro>Is the data type for the elements of the operands, </intro>
|
|
<table class="valuetable">
|
|
<tgroup cols="4">
|
|
<thead>
|
|
<row>
|
|
<entry class="bitfield" bitwidth="1">op</entry>
|
|
<entry class="bitfield" bitwidth="1">U</entry>
|
|
<entry class="bitfield" bitwidth="2">size</entry>
|
|
<entry class="symbol"><dt></entry>
|
|
</row>
|
|
</thead>
|
|
<tbody>
|
|
<row>
|
|
<entry class="bitfield">0</entry>
|
|
<entry class="bitfield">0</entry>
|
|
<entry class="bitfield">00</entry>
|
|
<entry class="symbol">S8</entry>
|
|
</row>
|
|
<row>
|
|
<entry class="bitfield">0</entry>
|
|
<entry class="bitfield">0</entry>
|
|
<entry class="bitfield">01</entry>
|
|
<entry class="symbol">S16</entry>
|
|
</row>
|
|
<row>
|
|
<entry class="bitfield">0</entry>
|
|
<entry class="bitfield">0</entry>
|
|
<entry class="bitfield">10</entry>
|
|
<entry class="symbol">S32</entry>
|
|
</row>
|
|
<row>
|
|
<entry class="bitfield">0</entry>
|
|
<entry class="bitfield">1</entry>
|
|
<entry class="bitfield">00</entry>
|
|
<entry class="symbol">U8</entry>
|
|
</row>
|
|
<row>
|
|
<entry class="bitfield">0</entry>
|
|
<entry class="bitfield">1</entry>
|
|
<entry class="bitfield">01</entry>
|
|
<entry class="symbol">U16</entry>
|
|
</row>
|
|
<row>
|
|
<entry class="bitfield">0</entry>
|
|
<entry class="bitfield">1</entry>
|
|
<entry class="bitfield">10</entry>
|
|
<entry class="symbol">U32</entry>
|
|
</row>
|
|
<row>
|
|
<entry class="bitfield">1</entry>
|
|
<entry class="bitfield">0</entry>
|
|
<entry class="bitfield">00</entry>
|
|
<entry class="symbol">P8</entry>
|
|
</row>
|
|
<row>
|
|
<entry class="bitfield">1</entry>
|
|
<entry class="bitfield">0</entry>
|
|
<entry class="bitfield">10</entry>
|
|
<entry class="symbol">P64</entry>
|
|
</row>
|
|
</tbody>
|
|
</tgroup>
|
|
</table>
|
|
</definition>
|
|
</account>
|
|
<account iclass="simd3reg_diff" symbol="<dt>" iclass_long="Advanced SIMD three registers of different lengths">
|
|
<encodings>
|
|
<encoding encname="VADDHN_A1" />
|
|
<encoding encname="VRADDHN_A1" />
|
|
<encoding encname="VRSUBHN_A1" />
|
|
<encoding encname="VSUBHN_A1" />
|
|
</encodings>
|
|
<orig>Is the data type for the elements of the operands, encoded in "size", where 00->I16, 01->I32, 10->I64</orig>
|
|
<definition encodedin="size">
|
|
<intro>Is the data type for the elements of the operands, </intro>
|
|
<table class="valuetable">
|
|
<tgroup cols="2">
|
|
<thead>
|
|
<row>
|
|
<entry class="bitfield" bitwidth="2">size</entry>
|
|
<entry class="symbol"><dt></entry>
|
|
</row>
|
|
</thead>
|
|
<tbody>
|
|
<row>
|
|
<entry class="bitfield">00</entry>
|
|
<entry class="symbol">I16</entry>
|
|
</row>
|
|
<row>
|
|
<entry class="bitfield">01</entry>
|
|
<entry class="symbol">I32</entry>
|
|
</row>
|
|
<row>
|
|
<entry class="bitfield">10</entry>
|
|
<entry class="symbol">I64</entry>
|
|
</row>
|
|
</tbody>
|
|
</tgroup>
|
|
</table>
|
|
</definition>
|
|
</account>
|
|
<account iclass="simd_3diff" symbol="<dt>" iclass_long="Advanced SIMD three registers of different lengths">
|
|
<encodings>
|
|
<encoding encname="VADDHN_T1" />
|
|
<encoding encname="VRADDHN_T1" />
|
|
<encoding encname="VRSUBHN_T1" />
|
|
<encoding encname="VSUBHN_T1" />
|
|
</encodings>
|
|
<orig>Is the data type for the elements of the operands, encoded in "size", where 00->I16, 01->I32, 10->I64</orig>
|
|
<definition encodedin="size">
|
|
<intro>Is the data type for the elements of the operands, </intro>
|
|
<table class="valuetable">
|
|
<tgroup cols="2">
|
|
<thead>
|
|
<row>
|
|
<entry class="bitfield" bitwidth="2">size</entry>
|
|
<entry class="symbol"><dt></entry>
|
|
</row>
|
|
</thead>
|
|
<tbody>
|
|
<row>
|
|
<entry class="bitfield">00</entry>
|
|
<entry class="symbol">I16</entry>
|
|
</row>
|
|
<row>
|
|
<entry class="bitfield">01</entry>
|
|
<entry class="symbol">I32</entry>
|
|
</row>
|
|
<row>
|
|
<entry class="bitfield">10</entry>
|
|
<entry class="symbol">I64</entry>
|
|
</row>
|
|
</tbody>
|
|
</tgroup>
|
|
</table>
|
|
</definition>
|
|
</account>
|
|
<account iclass="simd3reg_diff" symbol="<dt>" iclass_long="Advanced SIMD three registers of different lengths">
|
|
<encodings>
|
|
<encoding encname="VQDMLAL_A1" />
|
|
<encoding encname="VQDMLSL_A1" />
|
|
<encoding encname="VQDMULL_A1" />
|
|
</encodings>
|
|
<orig>Is the data type for the elements of the operands, encoded in "size", where 01->S16, 10->S32</orig>
|
|
<definition encodedin="size">
|
|
<intro>Is the data type for the elements of the operands, </intro>
|
|
<table class="valuetable">
|
|
<tgroup cols="2">
|
|
<thead>
|
|
<row>
|
|
<entry class="bitfield" bitwidth="2">size</entry>
|
|
<entry class="symbol"><dt></entry>
|
|
</row>
|
|
</thead>
|
|
<tbody>
|
|
<row>
|
|
<entry class="bitfield">01</entry>
|
|
<entry class="symbol">S16</entry>
|
|
</row>
|
|
<row>
|
|
<entry class="bitfield">10</entry>
|
|
<entry class="symbol">S32</entry>
|
|
</row>
|
|
</tbody>
|
|
</tgroup>
|
|
</table>
|
|
</definition>
|
|
</account>
|
|
<account iclass="simd_3diff" symbol="<dt>" iclass_long="Advanced SIMD three registers of different lengths">
|
|
<encodings>
|
|
<encoding encname="VQDMLAL_T1" />
|
|
<encoding encname="VQDMLSL_T1" />
|
|
<encoding encname="VQDMULL_T1" />
|
|
</encodings>
|
|
<orig>Is the data type for the elements of the operands, encoded in "size", where 01->S16, 10->S32</orig>
|
|
<definition encodedin="size">
|
|
<intro>Is the data type for the elements of the operands, </intro>
|
|
<table class="valuetable">
|
|
<tgroup cols="2">
|
|
<thead>
|
|
<row>
|
|
<entry class="bitfield" bitwidth="2">size</entry>
|
|
<entry class="symbol"><dt></entry>
|
|
</row>
|
|
</thead>
|
|
<tbody>
|
|
<row>
|
|
<entry class="bitfield">01</entry>
|
|
<entry class="symbol">S16</entry>
|
|
</row>
|
|
<row>
|
|
<entry class="bitfield">10</entry>
|
|
<entry class="symbol">S32</entry>
|
|
</row>
|
|
</tbody>
|
|
</tgroup>
|
|
</table>
|
|
</definition>
|
|
</account>
|
|
<account iclass="simd3reg_diff" symbol="<dt>" iclass_long="Advanced SIMD three registers of different lengths">
|
|
<encodings>
|
|
<encoding encname="VADDL_A1" />
|
|
<encoding encname="VADDW_A1" />
|
|
</encodings>
|
|
<orig>Is the data type for the elements of the second operand vector, encoded in "U:size", where 000->S8, 001->S16, 010->S32, 100->U8, 101->U16, 110->U32</orig>
|
|
<definition encodedin="U:size">
|
|
<intro>Is the data type for the elements of the second operand vector, </intro>
|
|
<table class="valuetable">
|
|
<tgroup cols="3">
|
|
<thead>
|
|
<row>
|
|
<entry class="bitfield" bitwidth="1">U</entry>
|
|
<entry class="bitfield" bitwidth="2">size</entry>
|
|
<entry class="symbol"><dt></entry>
|
|
</row>
|
|
</thead>
|
|
<tbody>
|
|
<row>
|
|
<entry class="bitfield">0</entry>
|
|
<entry class="bitfield">00</entry>
|
|
<entry class="symbol">S8</entry>
|
|
</row>
|
|
<row>
|
|
<entry class="bitfield">0</entry>
|
|
<entry class="bitfield">01</entry>
|
|
<entry class="symbol">S16</entry>
|
|
</row>
|
|
<row>
|
|
<entry class="bitfield">0</entry>
|
|
<entry class="bitfield">10</entry>
|
|
<entry class="symbol">S32</entry>
|
|
</row>
|
|
<row>
|
|
<entry class="bitfield">1</entry>
|
|
<entry class="bitfield">00</entry>
|
|
<entry class="symbol">U8</entry>
|
|
</row>
|
|
<row>
|
|
<entry class="bitfield">1</entry>
|
|
<entry class="bitfield">01</entry>
|
|
<entry class="symbol">U16</entry>
|
|
</row>
|
|
<row>
|
|
<entry class="bitfield">1</entry>
|
|
<entry class="bitfield">10</entry>
|
|
<entry class="symbol">U32</entry>
|
|
</row>
|
|
</tbody>
|
|
</tgroup>
|
|
</table>
|
|
</definition>
|
|
</account>
|
|
<account iclass="simd_3diff" symbol="<dt>" iclass_long="Advanced SIMD three registers of different lengths">
|
|
<encodings>
|
|
<encoding encname="VADDL_T1" />
|
|
<encoding encname="VADDW_T1" />
|
|
</encodings>
|
|
<orig>Is the data type for the elements of the second operand vector, encoded in "U:size", where 000->S8, 001->S16, 010->S32, 100->U8, 101->U16, 110->U32</orig>
|
|
<definition encodedin="U:size">
|
|
<intro>Is the data type for the elements of the second operand vector, </intro>
|
|
<table class="valuetable">
|
|
<tgroup cols="3">
|
|
<thead>
|
|
<row>
|
|
<entry class="bitfield" bitwidth="1">U</entry>
|
|
<entry class="bitfield" bitwidth="2">size</entry>
|
|
<entry class="symbol"><dt></entry>
|
|
</row>
|
|
</thead>
|
|
<tbody>
|
|
<row>
|
|
<entry class="bitfield">0</entry>
|
|
<entry class="bitfield">00</entry>
|
|
<entry class="symbol">S8</entry>
|
|
</row>
|
|
<row>
|
|
<entry class="bitfield">0</entry>
|
|
<entry class="bitfield">01</entry>
|
|
<entry class="symbol">S16</entry>
|
|
</row>
|
|
<row>
|
|
<entry class="bitfield">0</entry>
|
|
<entry class="bitfield">10</entry>
|
|
<entry class="symbol">S32</entry>
|
|
</row>
|
|
<row>
|
|
<entry class="bitfield">1</entry>
|
|
<entry class="bitfield">00</entry>
|
|
<entry class="symbol">U8</entry>
|
|
</row>
|
|
<row>
|
|
<entry class="bitfield">1</entry>
|
|
<entry class="bitfield">01</entry>
|
|
<entry class="symbol">U16</entry>
|
|
</row>
|
|
<row>
|
|
<entry class="bitfield">1</entry>
|
|
<entry class="bitfield">10</entry>
|
|
<entry class="symbol">U32</entry>
|
|
</row>
|
|
</tbody>
|
|
</tgroup>
|
|
</table>
|
|
</definition>
|
|
</account>
|
|
<account iclass="simd3reg_diff" symbol="<dt>" iclass_long="Advanced SIMD three registers of different lengths">
|
|
<encodings>
|
|
<encoding encname="VSUBL_A1" />
|
|
<encoding encname="VSUBW_A1" />
|
|
</encodings>
|
|
<orig>Is the data type for the elements of the second operand vector, encoded in "U:size", where 000->S8, 001->S16, 010->S32, 100->U8, 101->U16, 110->U32.</orig>
|
|
<definition encodedin="U:size">
|
|
<intro>Is the data type for the elements of the second operand vector, </intro>
|
|
<table class="valuetable">
|
|
<tgroup cols="3">
|
|
<thead>
|
|
<row>
|
|
<entry class="bitfield" bitwidth="1">U</entry>
|
|
<entry class="bitfield" bitwidth="2">size</entry>
|
|
<entry class="symbol"><dt></entry>
|
|
</row>
|
|
</thead>
|
|
<tbody>
|
|
<row>
|
|
<entry class="bitfield">0</entry>
|
|
<entry class="bitfield">00</entry>
|
|
<entry class="symbol">S8</entry>
|
|
</row>
|
|
<row>
|
|
<entry class="bitfield">0</entry>
|
|
<entry class="bitfield">01</entry>
|
|
<entry class="symbol">S16</entry>
|
|
</row>
|
|
<row>
|
|
<entry class="bitfield">0</entry>
|
|
<entry class="bitfield">10</entry>
|
|
<entry class="symbol">S32</entry>
|
|
</row>
|
|
<row>
|
|
<entry class="bitfield">1</entry>
|
|
<entry class="bitfield">00</entry>
|
|
<entry class="symbol">U8</entry>
|
|
</row>
|
|
<row>
|
|
<entry class="bitfield">1</entry>
|
|
<entry class="bitfield">01</entry>
|
|
<entry class="symbol">U16</entry>
|
|
</row>
|
|
<row>
|
|
<entry class="bitfield">1</entry>
|
|
<entry class="bitfield">10</entry>
|
|
<entry class="symbol">U32</entry>
|
|
</row>
|
|
</tbody>
|
|
</tgroup>
|
|
</table>
|
|
</definition>
|
|
</account>
|
|
<account iclass="simd_3diff" symbol="<dt>" iclass_long="Advanced SIMD three registers of different lengths">
|
|
<encodings>
|
|
<encoding encname="VSUBL_T1" />
|
|
<encoding encname="VSUBW_T1" />
|
|
</encodings>
|
|
<orig>Is the data type for the elements of the second operand vector, encoded in "U:size", where 000->S8, 001->S16, 010->S32, 100->U8, 101->U16, 110->U32.</orig>
|
|
<definition encodedin="U:size">
|
|
<intro>Is the data type for the elements of the second operand vector, </intro>
|
|
<table class="valuetable">
|
|
<tgroup cols="3">
|
|
<thead>
|
|
<row>
|
|
<entry class="bitfield" bitwidth="1">U</entry>
|
|
<entry class="bitfield" bitwidth="2">size</entry>
|
|
<entry class="symbol"><dt></entry>
|
|
</row>
|
|
</thead>
|
|
<tbody>
|
|
<row>
|
|
<entry class="bitfield">0</entry>
|
|
<entry class="bitfield">00</entry>
|
|
<entry class="symbol">S8</entry>
|
|
</row>
|
|
<row>
|
|
<entry class="bitfield">0</entry>
|
|
<entry class="bitfield">01</entry>
|
|
<entry class="symbol">S16</entry>
|
|
</row>
|
|
<row>
|
|
<entry class="bitfield">0</entry>
|
|
<entry class="bitfield">10</entry>
|
|
<entry class="symbol">S32</entry>
|
|
</row>
|
|
<row>
|
|
<entry class="bitfield">1</entry>
|
|
<entry class="bitfield">00</entry>
|
|
<entry class="symbol">U8</entry>
|
|
</row>
|
|
<row>
|
|
<entry class="bitfield">1</entry>
|
|
<entry class="bitfield">01</entry>
|
|
<entry class="symbol">U16</entry>
|
|
</row>
|
|
<row>
|
|
<entry class="bitfield">1</entry>
|
|
<entry class="bitfield">10</entry>
|
|
<entry class="symbol">U32</entry>
|
|
</row>
|
|
</tbody>
|
|
</tgroup>
|
|
</table>
|
|
</definition>
|
|
</account>
|
|
<account iclass="simd3reg_same" symbol="<dt>" iclass_long="Advanced SIMD three registers of the same length">
|
|
<encodings>
|
|
<encoding encname="VABA_A1_D" />
|
|
<encoding encname="VABA_A1_Q" />
|
|
<encoding encname="VABD_i_A1_D" />
|
|
<encoding encname="VABD_i_A1_Q" />
|
|
<encoding encname="VCGE_r_A1_D" />
|
|
<encoding encname="VCGE_r_A1_Q" />
|
|
<encoding encname="VCGT_r_A1_D" />
|
|
<encoding encname="VCGT_r_A1_Q" />
|
|
<encoding encname="VCLE_VCGE_r_A1_D" />
|
|
<encoding encname="VCLE_VCGE_r_A1_Q" />
|
|
<encoding encname="VCLT_VCGT_r_A1_D" />
|
|
<encoding encname="VCLT_VCGT_r_A1_Q" />
|
|
<encoding encname="VHADD_A1_D" />
|
|
<encoding encname="VHADD_A1_Q" />
|
|
<encoding encname="VHSUB_A1_D" />
|
|
<encoding encname="VHSUB_A1_Q" />
|
|
<encoding encname="VMAX_i_A1_D" />
|
|
<encoding encname="VMAX_i_A1_Q" />
|
|
<encoding encname="VMIN_i_A1_D" />
|
|
<encoding encname="VMIN_i_A1_Q" />
|
|
<encoding encname="VPMAX_i_A1" />
|
|
<encoding encname="VPMIN_i_A1" />
|
|
<encoding encname="VRHADD_A1_D" />
|
|
<encoding encname="VRHADD_A1_Q" />
|
|
</encodings>
|
|
<orig>Is the data type for the elements of the operands, encoded in "U:size", where 000->S8, 001->S16, 010->S32, 100->U8, 101->U16, 110->U32</orig>
|
|
<definition encodedin="U:size">
|
|
<intro>Is the data type for the elements of the operands, </intro>
|
|
<table class="valuetable">
|
|
<tgroup cols="3">
|
|
<thead>
|
|
<row>
|
|
<entry class="bitfield" bitwidth="1">U</entry>
|
|
<entry class="bitfield" bitwidth="2">size</entry>
|
|
<entry class="symbol"><dt></entry>
|
|
</row>
|
|
</thead>
|
|
<tbody>
|
|
<row>
|
|
<entry class="bitfield">0</entry>
|
|
<entry class="bitfield">00</entry>
|
|
<entry class="symbol">S8</entry>
|
|
</row>
|
|
<row>
|
|
<entry class="bitfield">0</entry>
|
|
<entry class="bitfield">01</entry>
|
|
<entry class="symbol">S16</entry>
|
|
</row>
|
|
<row>
|
|
<entry class="bitfield">0</entry>
|
|
<entry class="bitfield">10</entry>
|
|
<entry class="symbol">S32</entry>
|
|
</row>
|
|
<row>
|
|
<entry class="bitfield">1</entry>
|
|
<entry class="bitfield">00</entry>
|
|
<entry class="symbol">U8</entry>
|
|
</row>
|
|
<row>
|
|
<entry class="bitfield">1</entry>
|
|
<entry class="bitfield">01</entry>
|
|
<entry class="symbol">U16</entry>
|
|
</row>
|
|
<row>
|
|
<entry class="bitfield">1</entry>
|
|
<entry class="bitfield">10</entry>
|
|
<entry class="symbol">U32</entry>
|
|
</row>
|
|
</tbody>
|
|
</tgroup>
|
|
</table>
|
|
</definition>
|
|
</account>
|
|
<account iclass="simd_3same" symbol="<dt>" iclass_long="Advanced SIMD three registers of the same length">
|
|
<encodings>
|
|
<encoding encname="VABA_T1_D" />
|
|
<encoding encname="VABA_T1_Q" />
|
|
<encoding encname="VABD_i_T1_D" />
|
|
<encoding encname="VABD_i_T1_Q" />
|
|
<encoding encname="VCGE_r_T1_D" />
|
|
<encoding encname="VCGE_r_T1_Q" />
|
|
<encoding encname="VCGT_r_T1_D" />
|
|
<encoding encname="VCGT_r_T1_Q" />
|
|
<encoding encname="VCLE_VCGE_r_T1_D" />
|
|
<encoding encname="VCLE_VCGE_r_T1_Q" />
|
|
<encoding encname="VCLT_VCGT_r_T1_D" />
|
|
<encoding encname="VCLT_VCGT_r_T1_Q" />
|
|
<encoding encname="VHADD_T1_D" />
|
|
<encoding encname="VHADD_T1_Q" />
|
|
<encoding encname="VHSUB_T1_D" />
|
|
<encoding encname="VHSUB_T1_Q" />
|
|
<encoding encname="VMAX_i_T1_D" />
|
|
<encoding encname="VMAX_i_T1_Q" />
|
|
<encoding encname="VMIN_i_T1_D" />
|
|
<encoding encname="VMIN_i_T1_Q" />
|
|
<encoding encname="VPMAX_i_T1" />
|
|
<encoding encname="VPMIN_i_T1" />
|
|
<encoding encname="VRHADD_T1_D" />
|
|
<encoding encname="VRHADD_T1_Q" />
|
|
</encodings>
|
|
<orig>Is the data type for the elements of the operands, encoded in "U:size", where 000->S8, 001->S16, 010->S32, 100->U8, 101->U16, 110->U32</orig>
|
|
<definition encodedin="U:size">
|
|
<intro>Is the data type for the elements of the operands, </intro>
|
|
<table class="valuetable">
|
|
<tgroup cols="3">
|
|
<thead>
|
|
<row>
|
|
<entry class="bitfield" bitwidth="1">U</entry>
|
|
<entry class="bitfield" bitwidth="2">size</entry>
|
|
<entry class="symbol"><dt></entry>
|
|
</row>
|
|
</thead>
|
|
<tbody>
|
|
<row>
|
|
<entry class="bitfield">0</entry>
|
|
<entry class="bitfield">00</entry>
|
|
<entry class="symbol">S8</entry>
|
|
</row>
|
|
<row>
|
|
<entry class="bitfield">0</entry>
|
|
<entry class="bitfield">01</entry>
|
|
<entry class="symbol">S16</entry>
|
|
</row>
|
|
<row>
|
|
<entry class="bitfield">0</entry>
|
|
<entry class="bitfield">10</entry>
|
|
<entry class="symbol">S32</entry>
|
|
</row>
|
|
<row>
|
|
<entry class="bitfield">1</entry>
|
|
<entry class="bitfield">00</entry>
|
|
<entry class="symbol">U8</entry>
|
|
</row>
|
|
<row>
|
|
<entry class="bitfield">1</entry>
|
|
<entry class="bitfield">01</entry>
|
|
<entry class="symbol">U16</entry>
|
|
</row>
|
|
<row>
|
|
<entry class="bitfield">1</entry>
|
|
<entry class="bitfield">10</entry>
|
|
<entry class="symbol">U32</entry>
|
|
</row>
|
|
</tbody>
|
|
</tgroup>
|
|
</table>
|
|
</definition>
|
|
</account>
|
|
<account iclass="simd3reg_same" symbol="<dt>" iclass_long="Advanced SIMD three registers of the same length">
|
|
<encodings>
|
|
<encoding encname="VMUL_i_A1_D" />
|
|
<encoding encname="VMUL_i_A1_Q" />
|
|
</encodings>
|
|
<orig>Is the data type for the elements of the operands, encoded in "op:size", where 000->I8, 001->I16, 010->I32, 100->P8</orig>
|
|
<definition encodedin="op:size">
|
|
<intro>Is the data type for the elements of the operands, </intro>
|
|
<table class="valuetable">
|
|
<tgroup cols="3">
|
|
<thead>
|
|
<row>
|
|
<entry class="bitfield" bitwidth="1">op</entry>
|
|
<entry class="bitfield" bitwidth="2">size</entry>
|
|
<entry class="symbol"><dt></entry>
|
|
</row>
|
|
</thead>
|
|
<tbody>
|
|
<row>
|
|
<entry class="bitfield">0</entry>
|
|
<entry class="bitfield">00</entry>
|
|
<entry class="symbol">I8</entry>
|
|
</row>
|
|
<row>
|
|
<entry class="bitfield">0</entry>
|
|
<entry class="bitfield">01</entry>
|
|
<entry class="symbol">I16</entry>
|
|
</row>
|
|
<row>
|
|
<entry class="bitfield">0</entry>
|
|
<entry class="bitfield">10</entry>
|
|
<entry class="symbol">I32</entry>
|
|
</row>
|
|
<row>
|
|
<entry class="bitfield">1</entry>
|
|
<entry class="bitfield">00</entry>
|
|
<entry class="symbol">P8</entry>
|
|
</row>
|
|
</tbody>
|
|
</tgroup>
|
|
</table>
|
|
</definition>
|
|
</account>
|
|
<account iclass="simd_3same" symbol="<dt>" iclass_long="Advanced SIMD three registers of the same length">
|
|
<encodings>
|
|
<encoding encname="VMUL_i_T1_D" />
|
|
<encoding encname="VMUL_i_T1_Q" />
|
|
</encodings>
|
|
<orig>Is the data type for the elements of the operands, encoded in "op:size", where 000->I8, 001->I16, 010->I32, 100->P8</orig>
|
|
<definition encodedin="op:size">
|
|
<intro>Is the data type for the elements of the operands, </intro>
|
|
<table class="valuetable">
|
|
<tgroup cols="3">
|
|
<thead>
|
|
<row>
|
|
<entry class="bitfield" bitwidth="1">op</entry>
|
|
<entry class="bitfield" bitwidth="2">size</entry>
|
|
<entry class="symbol"><dt></entry>
|
|
</row>
|
|
</thead>
|
|
<tbody>
|
|
<row>
|
|
<entry class="bitfield">0</entry>
|
|
<entry class="bitfield">00</entry>
|
|
<entry class="symbol">I8</entry>
|
|
</row>
|
|
<row>
|
|
<entry class="bitfield">0</entry>
|
|
<entry class="bitfield">01</entry>
|
|
<entry class="symbol">I16</entry>
|
|
</row>
|
|
<row>
|
|
<entry class="bitfield">0</entry>
|
|
<entry class="bitfield">10</entry>
|
|
<entry class="symbol">I32</entry>
|
|
</row>
|
|
<row>
|
|
<entry class="bitfield">1</entry>
|
|
<entry class="bitfield">00</entry>
|
|
<entry class="symbol">P8</entry>
|
|
</row>
|
|
</tbody>
|
|
</tgroup>
|
|
</table>
|
|
</definition>
|
|
</account>
|
|
<account iclass="simd3reg_same" symbol="<dt>" iclass_long="Advanced SIMD three registers of the same length">
|
|
<encodings>
|
|
<encoding encname="VTST_A1_D" />
|
|
<encoding encname="VTST_A1_Q" />
|
|
</encodings>
|
|
<orig>Is the data type for the elements of the operands, encoded in "size", where 00->8, 01->16, 10->32</orig>
|
|
<definition encodedin="size">
|
|
<intro>Is the data type for the elements of the operands, </intro>
|
|
<table class="valuetable">
|
|
<tgroup cols="2">
|
|
<thead>
|
|
<row>
|
|
<entry class="bitfield" bitwidth="2">size</entry>
|
|
<entry class="symbol"><dt></entry>
|
|
</row>
|
|
</thead>
|
|
<tbody>
|
|
<row>
|
|
<entry class="bitfield">00</entry>
|
|
<entry class="symbol">8</entry>
|
|
</row>
|
|
<row>
|
|
<entry class="bitfield">01</entry>
|
|
<entry class="symbol">16</entry>
|
|
</row>
|
|
<row>
|
|
<entry class="bitfield">10</entry>
|
|
<entry class="symbol">32</entry>
|
|
</row>
|
|
</tbody>
|
|
</tgroup>
|
|
</table>
|
|
</definition>
|
|
</account>
|
|
<account iclass="simd_3same" symbol="<dt>" iclass_long="Advanced SIMD three registers of the same length">
|
|
<encodings>
|
|
<encoding encname="VTST_T1_D" />
|
|
<encoding encname="VTST_T1_Q" />
|
|
</encodings>
|
|
<orig>Is the data type for the elements of the operands, encoded in "size", where 00->8, 01->16, 10->32</orig>
|
|
<definition encodedin="size">
|
|
<intro>Is the data type for the elements of the operands, </intro>
|
|
<table class="valuetable">
|
|
<tgroup cols="2">
|
|
<thead>
|
|
<row>
|
|
<entry class="bitfield" bitwidth="2">size</entry>
|
|
<entry class="symbol"><dt></entry>
|
|
</row>
|
|
</thead>
|
|
<tbody>
|
|
<row>
|
|
<entry class="bitfield">00</entry>
|
|
<entry class="symbol">8</entry>
|
|
</row>
|
|
<row>
|
|
<entry class="bitfield">01</entry>
|
|
<entry class="symbol">16</entry>
|
|
</row>
|
|
<row>
|
|
<entry class="bitfield">10</entry>
|
|
<entry class="symbol">32</entry>
|
|
</row>
|
|
</tbody>
|
|
</tgroup>
|
|
</table>
|
|
</definition>
|
|
</account>
|
|
<account iclass="simd3reg_same" symbol="<dt>" iclass_long="Advanced SIMD three registers of the same length">
|
|
<encodings>
|
|
<encoding encname="VMLA_i_A1_D" />
|
|
<encoding encname="VMLA_i_A1_Q" />
|
|
<encoding encname="VMLS_i_A1_D" />
|
|
<encoding encname="VMLS_i_A1_Q" />
|
|
</encodings>
|
|
<orig>Is the data type for the elements of the operands, encoded in "size", where 00->I8, 01->I16, 10->I32</orig>
|
|
<definition encodedin="size">
|
|
<intro>Is the data type for the elements of the operands, </intro>
|
|
<table class="valuetable">
|
|
<tgroup cols="2">
|
|
<thead>
|
|
<row>
|
|
<entry class="bitfield" bitwidth="2">size</entry>
|
|
<entry class="symbol"><dt></entry>
|
|
</row>
|
|
</thead>
|
|
<tbody>
|
|
<row>
|
|
<entry class="bitfield">00</entry>
|
|
<entry class="symbol">I8</entry>
|
|
</row>
|
|
<row>
|
|
<entry class="bitfield">01</entry>
|
|
<entry class="symbol">I16</entry>
|
|
</row>
|
|
<row>
|
|
<entry class="bitfield">10</entry>
|
|
<entry class="symbol">I32</entry>
|
|
</row>
|
|
</tbody>
|
|
</tgroup>
|
|
</table>
|
|
</definition>
|
|
</account>
|
|
<account iclass="simd_3same" symbol="<dt>" iclass_long="Advanced SIMD three registers of the same length">
|
|
<encodings>
|
|
<encoding encname="VMLA_i_T1_D" />
|
|
<encoding encname="VMLA_i_T1_Q" />
|
|
<encoding encname="VMLS_i_T1_D" />
|
|
<encoding encname="VMLS_i_T1_Q" />
|
|
</encodings>
|
|
<orig>Is the data type for the elements of the operands, encoded in "size", where 00->I8, 01->I16, 10->I32</orig>
|
|
<definition encodedin="size">
|
|
<intro>Is the data type for the elements of the operands, </intro>
|
|
<table class="valuetable">
|
|
<tgroup cols="2">
|
|
<thead>
|
|
<row>
|
|
<entry class="bitfield" bitwidth="2">size</entry>
|
|
<entry class="symbol"><dt></entry>
|
|
</row>
|
|
</thead>
|
|
<tbody>
|
|
<row>
|
|
<entry class="bitfield">00</entry>
|
|
<entry class="symbol">I8</entry>
|
|
</row>
|
|
<row>
|
|
<entry class="bitfield">01</entry>
|
|
<entry class="symbol">I16</entry>
|
|
</row>
|
|
<row>
|
|
<entry class="bitfield">10</entry>
|
|
<entry class="symbol">I32</entry>
|
|
</row>
|
|
</tbody>
|
|
</tgroup>
|
|
</table>
|
|
</definition>
|
|
</account>
|
|
<account iclass="simd3reg_same" symbol="<dt>" iclass_long="Advanced SIMD three registers of the same length">
|
|
<encodings>
|
|
<encoding encname="VQDMULH_A1_D" />
|
|
<encoding encname="VQDMULH_A1_Q" />
|
|
<encoding encname="VQRDMLAH_A1_D" />
|
|
<encoding encname="VQRDMLAH_A1_Q" />
|
|
<encoding encname="VQRDMLSH_A1_D" />
|
|
<encoding encname="VQRDMLSH_A1_Q" />
|
|
<encoding encname="VQRDMULH_A1_D" />
|
|
<encoding encname="VQRDMULH_A1_Q" />
|
|
</encodings>
|
|
<orig>Is the data type for the elements of the operands, encoded in "size", where 01->S16, 10->S32</orig>
|
|
<definition encodedin="size">
|
|
<intro>Is the data type for the elements of the operands, </intro>
|
|
<table class="valuetable">
|
|
<tgroup cols="2">
|
|
<thead>
|
|
<row>
|
|
<entry class="bitfield" bitwidth="2">size</entry>
|
|
<entry class="symbol"><dt></entry>
|
|
</row>
|
|
</thead>
|
|
<tbody>
|
|
<row>
|
|
<entry class="bitfield">01</entry>
|
|
<entry class="symbol">S16</entry>
|
|
</row>
|
|
<row>
|
|
<entry class="bitfield">10</entry>
|
|
<entry class="symbol">S32</entry>
|
|
</row>
|
|
</tbody>
|
|
</tgroup>
|
|
</table>
|
|
</definition>
|
|
</account>
|
|
<account iclass="simd_3same" symbol="<dt>" iclass_long="Advanced SIMD three registers of the same length">
|
|
<encodings>
|
|
<encoding encname="VQDMULH_T1_D" />
|
|
<encoding encname="VQDMULH_T1_Q" />
|
|
<encoding encname="VQRDMLAH_T1_D" />
|
|
<encoding encname="VQRDMLAH_T1_Q" />
|
|
<encoding encname="VQRDMLSH_T1_D" />
|
|
<encoding encname="VQRDMLSH_T1_Q" />
|
|
<encoding encname="VQRDMULH_T1_D" />
|
|
<encoding encname="VQRDMULH_T1_Q" />
|
|
</encodings>
|
|
<orig>Is the data type for the elements of the operands, encoded in "size", where 01->S16, 10->S32</orig>
|
|
<definition encodedin="size">
|
|
<intro>Is the data type for the elements of the operands, </intro>
|
|
<table class="valuetable">
|
|
<tgroup cols="2">
|
|
<thead>
|
|
<row>
|
|
<entry class="bitfield" bitwidth="2">size</entry>
|
|
<entry class="symbol"><dt></entry>
|
|
</row>
|
|
</thead>
|
|
<tbody>
|
|
<row>
|
|
<entry class="bitfield">01</entry>
|
|
<entry class="symbol">S16</entry>
|
|
</row>
|
|
<row>
|
|
<entry class="bitfield">10</entry>
|
|
<entry class="symbol">S32</entry>
|
|
</row>
|
|
</tbody>
|
|
</tgroup>
|
|
</table>
|
|
</definition>
|
|
</account>
|
|
<account iclass="simd3reg_same" symbol="<dt>" iclass_long="Advanced SIMD three registers of the same length">
|
|
<encodings>
|
|
<encoding encname="VQADD_A1_D" />
|
|
<encoding encname="VQADD_A1_Q" />
|
|
<encoding encname="VQRSHL_A1_D" />
|
|
<encoding encname="VQRSHL_A1_Q" />
|
|
<encoding encname="VQSHL_r_A1_D" />
|
|
<encoding encname="VQSHL_r_A1_Q" />
|
|
<encoding encname="VQSUB_A1_D" />
|
|
<encoding encname="VQSUB_A1_Q" />
|
|
<encoding encname="VRSHL_A1_D" />
|
|
<encoding encname="VRSHL_A1_Q" />
|
|
<encoding encname="VSHL_r_A1_D" />
|
|
<encoding encname="VSHL_r_A1_Q" />
|
|
</encodings>
|
|
<orig>Is the data type for the elements of the vectors, encoded in "U:size", where 000->S8, 001->S16, 010->S32, 011->S64, 100->U8, 101->U16, 110->U32, 111->U64.</orig>
|
|
<definition encodedin="U:size">
|
|
<intro>Is the data type for the elements of the vectors, </intro>
|
|
<table class="valuetable">
|
|
<tgroup cols="3">
|
|
<thead>
|
|
<row>
|
|
<entry class="bitfield" bitwidth="1">U</entry>
|
|
<entry class="bitfield" bitwidth="2">size</entry>
|
|
<entry class="symbol"><dt></entry>
|
|
</row>
|
|
</thead>
|
|
<tbody>
|
|
<row>
|
|
<entry class="bitfield">0</entry>
|
|
<entry class="bitfield">00</entry>
|
|
<entry class="symbol">S8</entry>
|
|
</row>
|
|
<row>
|
|
<entry class="bitfield">0</entry>
|
|
<entry class="bitfield">01</entry>
|
|
<entry class="symbol">S16</entry>
|
|
</row>
|
|
<row>
|
|
<entry class="bitfield">0</entry>
|
|
<entry class="bitfield">10</entry>
|
|
<entry class="symbol">S32</entry>
|
|
</row>
|
|
<row>
|
|
<entry class="bitfield">0</entry>
|
|
<entry class="bitfield">11</entry>
|
|
<entry class="symbol">S64</entry>
|
|
</row>
|
|
<row>
|
|
<entry class="bitfield">1</entry>
|
|
<entry class="bitfield">00</entry>
|
|
<entry class="symbol">U8</entry>
|
|
</row>
|
|
<row>
|
|
<entry class="bitfield">1</entry>
|
|
<entry class="bitfield">01</entry>
|
|
<entry class="symbol">U16</entry>
|
|
</row>
|
|
<row>
|
|
<entry class="bitfield">1</entry>
|
|
<entry class="bitfield">10</entry>
|
|
<entry class="symbol">U32</entry>
|
|
</row>
|
|
<row>
|
|
<entry class="bitfield">1</entry>
|
|
<entry class="bitfield">11</entry>
|
|
<entry class="symbol">U64</entry>
|
|
</row>
|
|
</tbody>
|
|
</tgroup>
|
|
</table>
|
|
</definition>
|
|
</account>
|
|
<account iclass="simd_3same" symbol="<dt>" iclass_long="Advanced SIMD three registers of the same length">
|
|
<encodings>
|
|
<encoding encname="VQADD_T1_D" />
|
|
<encoding encname="VQADD_T1_Q" />
|
|
<encoding encname="VQRSHL_T1_D" />
|
|
<encoding encname="VQRSHL_T1_Q" />
|
|
<encoding encname="VQSHL_r_T1_D" />
|
|
<encoding encname="VQSHL_r_T1_Q" />
|
|
<encoding encname="VQSUB_T1_D" />
|
|
<encoding encname="VQSUB_T1_Q" />
|
|
<encoding encname="VRSHL_T1_D" />
|
|
<encoding encname="VRSHL_T1_Q" />
|
|
<encoding encname="VSHL_r_T1_D" />
|
|
<encoding encname="VSHL_r_T1_Q" />
|
|
</encodings>
|
|
<orig>Is the data type for the elements of the vectors, encoded in "U:size", where 000->S8, 001->S16, 010->S32, 011->S64, 100->U8, 101->U16, 110->U32, 111->U64.</orig>
|
|
<definition encodedin="U:size">
|
|
<intro>Is the data type for the elements of the vectors, </intro>
|
|
<table class="valuetable">
|
|
<tgroup cols="3">
|
|
<thead>
|
|
<row>
|
|
<entry class="bitfield" bitwidth="1">U</entry>
|
|
<entry class="bitfield" bitwidth="2">size</entry>
|
|
<entry class="symbol"><dt></entry>
|
|
</row>
|
|
</thead>
|
|
<tbody>
|
|
<row>
|
|
<entry class="bitfield">0</entry>
|
|
<entry class="bitfield">00</entry>
|
|
<entry class="symbol">S8</entry>
|
|
</row>
|
|
<row>
|
|
<entry class="bitfield">0</entry>
|
|
<entry class="bitfield">01</entry>
|
|
<entry class="symbol">S16</entry>
|
|
</row>
|
|
<row>
|
|
<entry class="bitfield">0</entry>
|
|
<entry class="bitfield">10</entry>
|
|
<entry class="symbol">S32</entry>
|
|
</row>
|
|
<row>
|
|
<entry class="bitfield">0</entry>
|
|
<entry class="bitfield">11</entry>
|
|
<entry class="symbol">S64</entry>
|
|
</row>
|
|
<row>
|
|
<entry class="bitfield">1</entry>
|
|
<entry class="bitfield">00</entry>
|
|
<entry class="symbol">U8</entry>
|
|
</row>
|
|
<row>
|
|
<entry class="bitfield">1</entry>
|
|
<entry class="bitfield">01</entry>
|
|
<entry class="symbol">U16</entry>
|
|
</row>
|
|
<row>
|
|
<entry class="bitfield">1</entry>
|
|
<entry class="bitfield">10</entry>
|
|
<entry class="symbol">U32</entry>
|
|
</row>
|
|
<row>
|
|
<entry class="bitfield">1</entry>
|
|
<entry class="bitfield">11</entry>
|
|
<entry class="symbol">U64</entry>
|
|
</row>
|
|
</tbody>
|
|
</tgroup>
|
|
</table>
|
|
</definition>
|
|
</account>
|
|
<account iclass="simd3reg_same" symbol="<dt>" iclass_long="Advanced SIMD three registers of the same length">
|
|
<encodings>
|
|
<encoding encname="VCEQ_r_A1_D" />
|
|
<encoding encname="VCEQ_r_A1_Q" />
|
|
<encoding encname="VPADD_i_A1" />
|
|
</encodings>
|
|
<orig>Is the data type for the elements of the vectors, encoded in "size", where 00->I8, 01->I16, 10->I32</orig>
|
|
<definition encodedin="size">
|
|
<intro>Is the data type for the elements of the vectors, </intro>
|
|
<table class="valuetable">
|
|
<tgroup cols="2">
|
|
<thead>
|
|
<row>
|
|
<entry class="bitfield" bitwidth="2">size</entry>
|
|
<entry class="symbol"><dt></entry>
|
|
</row>
|
|
</thead>
|
|
<tbody>
|
|
<row>
|
|
<entry class="bitfield">00</entry>
|
|
<entry class="symbol">I8</entry>
|
|
</row>
|
|
<row>
|
|
<entry class="bitfield">01</entry>
|
|
<entry class="symbol">I16</entry>
|
|
</row>
|
|
<row>
|
|
<entry class="bitfield">10</entry>
|
|
<entry class="symbol">I32</entry>
|
|
</row>
|
|
</tbody>
|
|
</tgroup>
|
|
</table>
|
|
</definition>
|
|
</account>
|
|
<account iclass="simd_3same" symbol="<dt>" iclass_long="Advanced SIMD three registers of the same length">
|
|
<encodings>
|
|
<encoding encname="VCEQ_r_T1_D" />
|
|
<encoding encname="VCEQ_r_T1_Q" />
|
|
<encoding encname="VPADD_i_T1" />
|
|
</encodings>
|
|
<orig>Is the data type for the elements of the vectors, encoded in "size", where 00->I8, 01->I16, 10->I32</orig>
|
|
<definition encodedin="size">
|
|
<intro>Is the data type for the elements of the vectors, </intro>
|
|
<table class="valuetable">
|
|
<tgroup cols="2">
|
|
<thead>
|
|
<row>
|
|
<entry class="bitfield" bitwidth="2">size</entry>
|
|
<entry class="symbol"><dt></entry>
|
|
</row>
|
|
</thead>
|
|
<tbody>
|
|
<row>
|
|
<entry class="bitfield">00</entry>
|
|
<entry class="symbol">I8</entry>
|
|
</row>
|
|
<row>
|
|
<entry class="bitfield">01</entry>
|
|
<entry class="symbol">I16</entry>
|
|
</row>
|
|
<row>
|
|
<entry class="bitfield">10</entry>
|
|
<entry class="symbol">I32</entry>
|
|
</row>
|
|
</tbody>
|
|
</tgroup>
|
|
</table>
|
|
</definition>
|
|
</account>
|
|
<account iclass="simd3reg_same" symbol="<dt>" iclass_long="Advanced SIMD three registers of the same length">
|
|
<encodings>
|
|
<encoding encname="VADD_i_A1_D" />
|
|
<encoding encname="VADD_i_A1_Q" />
|
|
<encoding encname="VSUB_i_A1_D" />
|
|
<encoding encname="VSUB_i_A1_Q" />
|
|
</encodings>
|
|
<orig>Is the data type for the elements of the vectors, encoded in "size", where 00->I8, 01->I16, 10->I32, 11->I64.</orig>
|
|
<definition encodedin="size">
|
|
<intro>Is the data type for the elements of the vectors, </intro>
|
|
<table class="valuetable">
|
|
<tgroup cols="2">
|
|
<thead>
|
|
<row>
|
|
<entry class="bitfield" bitwidth="2">size</entry>
|
|
<entry class="symbol"><dt></entry>
|
|
</row>
|
|
</thead>
|
|
<tbody>
|
|
<row>
|
|
<entry class="bitfield">00</entry>
|
|
<entry class="symbol">I8</entry>
|
|
</row>
|
|
<row>
|
|
<entry class="bitfield">01</entry>
|
|
<entry class="symbol">I16</entry>
|
|
</row>
|
|
<row>
|
|
<entry class="bitfield">10</entry>
|
|
<entry class="symbol">I32</entry>
|
|
</row>
|
|
<row>
|
|
<entry class="bitfield">11</entry>
|
|
<entry class="symbol">I64</entry>
|
|
</row>
|
|
</tbody>
|
|
</tgroup>
|
|
</table>
|
|
</definition>
|
|
</account>
|
|
<account iclass="simd_3same" symbol="<dt>" iclass_long="Advanced SIMD three registers of the same length">
|
|
<encodings>
|
|
<encoding encname="VADD_i_T1_D" />
|
|
<encoding encname="VADD_i_T1_Q" />
|
|
<encoding encname="VSUB_i_T1_D" />
|
|
<encoding encname="VSUB_i_T1_Q" />
|
|
</encodings>
|
|
<orig>Is the data type for the elements of the vectors, encoded in "size", where 00->I8, 01->I16, 10->I32, 11->I64.</orig>
|
|
<definition encodedin="size">
|
|
<intro>Is the data type for the elements of the vectors, </intro>
|
|
<table class="valuetable">
|
|
<tgroup cols="2">
|
|
<thead>
|
|
<row>
|
|
<entry class="bitfield" bitwidth="2">size</entry>
|
|
<entry class="symbol"><dt></entry>
|
|
</row>
|
|
</thead>
|
|
<tbody>
|
|
<row>
|
|
<entry class="bitfield">00</entry>
|
|
<entry class="symbol">I8</entry>
|
|
</row>
|
|
<row>
|
|
<entry class="bitfield">01</entry>
|
|
<entry class="symbol">I16</entry>
|
|
</row>
|
|
<row>
|
|
<entry class="bitfield">10</entry>
|
|
<entry class="symbol">I32</entry>
|
|
</row>
|
|
<row>
|
|
<entry class="bitfield">11</entry>
|
|
<entry class="symbol">I64</entry>
|
|
</row>
|
|
</tbody>
|
|
</tgroup>
|
|
</table>
|
|
</definition>
|
|
</account>
|
|
<account iclass="simd3reg_same" symbol="<dt>" iclass_long="Advanced SIMD three registers of the same length">
|
|
<encodings>
|
|
<encoding encname="VABD_f_A1_D" />
|
|
<encoding encname="VABD_f_A1_Q" />
|
|
<encoding encname="VACGE_A1_D" />
|
|
<encoding encname="VACGE_A1_Q" />
|
|
<encoding encname="VACGT_A1_D" />
|
|
<encoding encname="VACGT_A1_Q" />
|
|
<encoding encname="VACLE_VACGE_A1_D" />
|
|
<encoding encname="VACLE_VACGE_A1_Q" />
|
|
<encoding encname="VACLT_VACGT_A1_D" />
|
|
<encoding encname="VACLT_VACGT_A1_Q" />
|
|
<encoding encname="VADD_f_A1_D" />
|
|
<encoding encname="VADD_f_A1_Q" />
|
|
<encoding encname="VCEQ_r_A2_D" />
|
|
<encoding encname="VCEQ_r_A2_Q" />
|
|
<encoding encname="VCGE_r_A2_D" />
|
|
<encoding encname="VCGE_r_A2_Q" />
|
|
<encoding encname="VCGT_r_A2_D" />
|
|
<encoding encname="VCGT_r_A2_Q" />
|
|
<encoding encname="VCLE_VCGE_r_A2_D" />
|
|
<encoding encname="VCLE_VCGE_r_A2_Q" />
|
|
<encoding encname="VCLT_VCGT_r_A2_D" />
|
|
<encoding encname="VCLT_VCGT_r_A2_Q" />
|
|
<encoding encname="VFMA_A1_D" />
|
|
<encoding encname="VFMA_A1_Q" />
|
|
<encoding encname="VFMS_A1_D" />
|
|
<encoding encname="VFMS_A1_Q" />
|
|
<encoding encname="VMAXNM_A1_D" />
|
|
<encoding encname="VMAXNM_A1_Q" />
|
|
<encoding encname="VMAX_f_A1_D" />
|
|
<encoding encname="VMAX_f_A1_Q" />
|
|
<encoding encname="VMINNM_A1_D" />
|
|
<encoding encname="VMINNM_A1_Q" />
|
|
<encoding encname="VMIN_f_A1_D" />
|
|
<encoding encname="VMIN_f_A1_Q" />
|
|
<encoding encname="VMLA_f_A1_D" />
|
|
<encoding encname="VMLA_f_A1_Q" />
|
|
<encoding encname="VMLS_f_A1_D" />
|
|
<encoding encname="VMLS_f_A1_Q" />
|
|
<encoding encname="VMUL_f_A1_D" />
|
|
<encoding encname="VMUL_f_A1_Q" />
|
|
<encoding encname="VPADD_f_A1" />
|
|
<encoding encname="VPMAX_f_A1" />
|
|
<encoding encname="VPMIN_f_A1" />
|
|
<encoding encname="VRECPS_A1_D" />
|
|
<encoding encname="VRECPS_A1_Q" />
|
|
<encoding encname="VRSQRTS_A1_D" />
|
|
<encoding encname="VRSQRTS_A1_Q" />
|
|
<encoding encname="VSUB_f_A1_D" />
|
|
<encoding encname="VSUB_f_A1_Q" />
|
|
</encodings>
|
|
<orig>Is the data type for the elements of the vectors, encoded in "sz", where 0->F32, 1->F16.</orig>
|
|
<definition encodedin="sz">
|
|
<intro>Is the data type for the elements of the vectors, </intro>
|
|
<table class="valuetable">
|
|
<tgroup cols="2">
|
|
<thead>
|
|
<row>
|
|
<entry class="bitfield" bitwidth="1">sz</entry>
|
|
<entry class="symbol"><dt></entry>
|
|
</row>
|
|
</thead>
|
|
<tbody>
|
|
<row>
|
|
<entry class="bitfield">0</entry>
|
|
<entry class="symbol">F32</entry>
|
|
</row>
|
|
<row>
|
|
<entry class="bitfield">1</entry>
|
|
<entry class="symbol">F16</entry>
|
|
</row>
|
|
</tbody>
|
|
</tgroup>
|
|
</table>
|
|
</definition>
|
|
</account>
|
|
<account iclass="simd_3same" symbol="<dt>" iclass_long="Advanced SIMD three registers of the same length">
|
|
<encodings>
|
|
<encoding encname="VABD_f_T1_D" />
|
|
<encoding encname="VABD_f_T1_Q" />
|
|
<encoding encname="VACGE_T1_D" />
|
|
<encoding encname="VACGE_T1_Q" />
|
|
<encoding encname="VACGT_T1_D" />
|
|
<encoding encname="VACGT_T1_Q" />
|
|
<encoding encname="VACLE_VACGE_T1_D" />
|
|
<encoding encname="VACLE_VACGE_T1_Q" />
|
|
<encoding encname="VACLT_VACGT_T1_D" />
|
|
<encoding encname="VACLT_VACGT_T1_Q" />
|
|
<encoding encname="VADD_f_T1_D" />
|
|
<encoding encname="VADD_f_T1_Q" />
|
|
<encoding encname="VCEQ_r_T2_D" />
|
|
<encoding encname="VCEQ_r_T2_Q" />
|
|
<encoding encname="VCGE_r_T2_D" />
|
|
<encoding encname="VCGE_r_T2_Q" />
|
|
<encoding encname="VCGT_r_T2_D" />
|
|
<encoding encname="VCGT_r_T2_Q" />
|
|
<encoding encname="VCLE_VCGE_r_T2_D" />
|
|
<encoding encname="VCLE_VCGE_r_T2_Q" />
|
|
<encoding encname="VCLT_VCGT_r_T2_D" />
|
|
<encoding encname="VCLT_VCGT_r_T2_Q" />
|
|
<encoding encname="VFMA_T1_D" />
|
|
<encoding encname="VFMA_T1_Q" />
|
|
<encoding encname="VFMS_T1_D" />
|
|
<encoding encname="VFMS_T1_Q" />
|
|
<encoding encname="VMAXNM_T1_D" />
|
|
<encoding encname="VMAXNM_T1_Q" />
|
|
<encoding encname="VMAX_f_T1_D" />
|
|
<encoding encname="VMAX_f_T1_Q" />
|
|
<encoding encname="VMINNM_T1_D" />
|
|
<encoding encname="VMINNM_T1_Q" />
|
|
<encoding encname="VMIN_f_T1_D" />
|
|
<encoding encname="VMIN_f_T1_Q" />
|
|
<encoding encname="VMLA_f_T1_D" />
|
|
<encoding encname="VMLA_f_T1_Q" />
|
|
<encoding encname="VMLS_f_T1_D" />
|
|
<encoding encname="VMLS_f_T1_Q" />
|
|
<encoding encname="VMUL_f_T1_D" />
|
|
<encoding encname="VMUL_f_T1_Q" />
|
|
<encoding encname="VPADD_f_T1" />
|
|
<encoding encname="VPMAX_f_T1" />
|
|
<encoding encname="VPMIN_f_T1" />
|
|
<encoding encname="VRECPS_T1_D" />
|
|
<encoding encname="VRECPS_T1_Q" />
|
|
<encoding encname="VRSQRTS_T1_D" />
|
|
<encoding encname="VRSQRTS_T1_Q" />
|
|
<encoding encname="VSUB_f_T1_D" />
|
|
<encoding encname="VSUB_f_T1_Q" />
|
|
</encodings>
|
|
<orig>Is the data type for the elements of the vectors, encoded in "sz", where 0->F32, 1->F16.</orig>
|
|
<definition encodedin="sz">
|
|
<intro>Is the data type for the elements of the vectors, </intro>
|
|
<table class="valuetable">
|
|
<tgroup cols="2">
|
|
<thead>
|
|
<row>
|
|
<entry class="bitfield" bitwidth="1">sz</entry>
|
|
<entry class="symbol"><dt></entry>
|
|
</row>
|
|
</thead>
|
|
<tbody>
|
|
<row>
|
|
<entry class="bitfield">0</entry>
|
|
<entry class="symbol">F32</entry>
|
|
</row>
|
|
<row>
|
|
<entry class="bitfield">1</entry>
|
|
<entry class="symbol">F16</entry>
|
|
</row>
|
|
</tbody>
|
|
</tgroup>
|
|
</table>
|
|
</definition>
|
|
</account>
|
|
<account iclass="simd3reg_sameext" symbol="<bt>" iclass_long="Advanced SIMD three registers of the same length extension">
|
|
<encodings>
|
|
<encoding encname="VFMA_bf_A1_Q" />
|
|
</encodings>
|
|
<orig>Is the bottom or top element specifier, encoded in "Q" where 0->B, 1->T.</orig>
|
|
<definition encodedin="Q">
|
|
<intro>Is the bottom or top element specifier, </intro>
|
|
<table class="valuetable">
|
|
<tgroup cols="2">
|
|
<thead>
|
|
<row>
|
|
<entry class="bitfield" bitwidth="1">Q</entry>
|
|
<entry class="symbol"><bt></entry>
|
|
</row>
|
|
</thead>
|
|
<tbody>
|
|
<row>
|
|
<entry class="bitfield">0</entry>
|
|
<entry class="symbol">B</entry>
|
|
</row>
|
|
<row>
|
|
<entry class="bitfield">1</entry>
|
|
<entry class="symbol">T</entry>
|
|
</row>
|
|
</tbody>
|
|
</tgroup>
|
|
</table>
|
|
</definition>
|
|
</account>
|
|
<account iclass="simd_3sameext" symbol="<bt>" iclass_long="Advanced SIMD three registers of the same length extension">
|
|
<encodings>
|
|
<encoding encname="VFMA_bf_T1_Q" />
|
|
</encodings>
|
|
<orig>Is the bottom or top element specifier, encoded in "Q" where 0->B, 1->T.</orig>
|
|
<definition encodedin="Q">
|
|
<intro>Is the bottom or top element specifier, </intro>
|
|
<table class="valuetable">
|
|
<tgroup cols="2">
|
|
<thead>
|
|
<row>
|
|
<entry class="bitfield" bitwidth="1">Q</entry>
|
|
<entry class="symbol"><bt></entry>
|
|
</row>
|
|
</thead>
|
|
<tbody>
|
|
<row>
|
|
<entry class="bitfield">0</entry>
|
|
<entry class="symbol">B</entry>
|
|
</row>
|
|
<row>
|
|
<entry class="bitfield">1</entry>
|
|
<entry class="symbol">T</entry>
|
|
</row>
|
|
</tbody>
|
|
</tgroup>
|
|
</table>
|
|
</definition>
|
|
</account>
|
|
<account iclass="simd3reg_sameext" symbol="<dt>" iclass_long="Advanced SIMD three registers of the same length extension">
|
|
<encodings>
|
|
<encoding encname="VCADD_A1_D" />
|
|
<encoding encname="VCADD_A1_Q" />
|
|
<encoding encname="VCMLA_A1_D" />
|
|
<encoding encname="VCMLA_A1_Q" />
|
|
</encodings>
|
|
<orig>Is the data type for the elements of the vectors, encoded in "S", where 0->F16, 1->F32.</orig>
|
|
<definition encodedin="S">
|
|
<intro>Is the data type for the elements of the vectors, </intro>
|
|
<table class="valuetable">
|
|
<tgroup cols="2">
|
|
<thead>
|
|
<row>
|
|
<entry class="bitfield" bitwidth="1">S</entry>
|
|
<entry class="symbol"><dt></entry>
|
|
</row>
|
|
</thead>
|
|
<tbody>
|
|
<row>
|
|
<entry class="bitfield">0</entry>
|
|
<entry class="symbol">F16</entry>
|
|
</row>
|
|
<row>
|
|
<entry class="bitfield">1</entry>
|
|
<entry class="symbol">F32</entry>
|
|
</row>
|
|
</tbody>
|
|
</tgroup>
|
|
</table>
|
|
</definition>
|
|
</account>
|
|
<account iclass="simd_3sameext" symbol="<dt>" iclass_long="Advanced SIMD three registers of the same length extension">
|
|
<encodings>
|
|
<encoding encname="VCADD_T1_D" />
|
|
<encoding encname="VCADD_T1_Q" />
|
|
<encoding encname="VCMLA_T1_D" />
|
|
<encoding encname="VCMLA_T1_Q" />
|
|
</encodings>
|
|
<orig>Is the data type for the elements of the vectors, encoded in "S", where 0->F16, 1->F32.</orig>
|
|
<definition encodedin="S">
|
|
<intro>Is the data type for the elements of the vectors, </intro>
|
|
<table class="valuetable">
|
|
<tgroup cols="2">
|
|
<thead>
|
|
<row>
|
|
<entry class="bitfield" bitwidth="1">S</entry>
|
|
<entry class="symbol"><dt></entry>
|
|
</row>
|
|
</thead>
|
|
<tbody>
|
|
<row>
|
|
<entry class="bitfield">0</entry>
|
|
<entry class="symbol">F16</entry>
|
|
</row>
|
|
<row>
|
|
<entry class="bitfield">1</entry>
|
|
<entry class="symbol">F32</entry>
|
|
</row>
|
|
</tbody>
|
|
</tgroup>
|
|
</table>
|
|
</definition>
|
|
</account>
|
|
<account iclass="simd3reg_sameext" symbol="<rotate>" iclass_long="Advanced SIMD three registers of the same length extension">
|
|
<encodings>
|
|
<encoding encname="VCADD_A1_D" />
|
|
<encoding encname="VCADD_A1_Q" />
|
|
</encodings>
|
|
<orig>Is the rotation to be applied to elements in the second SIMD&FP source register, encoded in "rot", where 0->90, 1->270.</orig>
|
|
<definition encodedin="rot">
|
|
<intro>Is the rotation to be applied to elements in the second SIMD&FP source register, </intro>
|
|
<table class="valuetable">
|
|
<tgroup cols="2">
|
|
<thead>
|
|
<row>
|
|
<entry class="bitfield" bitwidth="1">rot</entry>
|
|
<entry class="symbol"><rotate></entry>
|
|
</row>
|
|
</thead>
|
|
<tbody>
|
|
<row>
|
|
<entry class="bitfield">0</entry>
|
|
<entry class="symbol">90</entry>
|
|
</row>
|
|
<row>
|
|
<entry class="bitfield">1</entry>
|
|
<entry class="symbol">270</entry>
|
|
</row>
|
|
</tbody>
|
|
</tgroup>
|
|
</table>
|
|
</definition>
|
|
</account>
|
|
<account iclass="simd_3sameext" symbol="<rotate>" iclass_long="Advanced SIMD three registers of the same length extension">
|
|
<encodings>
|
|
<encoding encname="VCADD_T1_D" />
|
|
<encoding encname="VCADD_T1_Q" />
|
|
</encodings>
|
|
<orig>Is the rotation to be applied to elements in the second SIMD&FP source register, encoded in "rot", where 0->90, 1->270.</orig>
|
|
<definition encodedin="rot">
|
|
<intro>Is the rotation to be applied to elements in the second SIMD&FP source register, </intro>
|
|
<table class="valuetable">
|
|
<tgroup cols="2">
|
|
<thead>
|
|
<row>
|
|
<entry class="bitfield" bitwidth="1">rot</entry>
|
|
<entry class="symbol"><rotate></entry>
|
|
</row>
|
|
</thead>
|
|
<tbody>
|
|
<row>
|
|
<entry class="bitfield">0</entry>
|
|
<entry class="symbol">90</entry>
|
|
</row>
|
|
<row>
|
|
<entry class="bitfield">1</entry>
|
|
<entry class="symbol">270</entry>
|
|
</row>
|
|
</tbody>
|
|
</tgroup>
|
|
</table>
|
|
</definition>
|
|
</account>
|
|
<account iclass="simd3reg_sameext" symbol="<rotate>" iclass_long="Advanced SIMD three registers of the same length extension">
|
|
<encodings>
|
|
<encoding encname="VCMLA_A1_D" />
|
|
<encoding encname="VCMLA_A1_Q" />
|
|
</encodings>
|
|
<orig>Is the rotation to be applied to elements in the second SIMD&FP source register, encoded in "rot", where 00->0, 01->90, 10->180, 11->270.</orig>
|
|
<definition encodedin="rot">
|
|
<intro>Is the rotation to be applied to elements in the second SIMD&FP source register, </intro>
|
|
<table class="valuetable">
|
|
<tgroup cols="2">
|
|
<thead>
|
|
<row>
|
|
<entry class="bitfield" bitwidth="2">rot</entry>
|
|
<entry class="symbol"><rotate></entry>
|
|
</row>
|
|
</thead>
|
|
<tbody>
|
|
<row>
|
|
<entry class="bitfield">00</entry>
|
|
<entry class="symbol">0</entry>
|
|
</row>
|
|
<row>
|
|
<entry class="bitfield">01</entry>
|
|
<entry class="symbol">90</entry>
|
|
</row>
|
|
<row>
|
|
<entry class="bitfield">10</entry>
|
|
<entry class="symbol">180</entry>
|
|
</row>
|
|
<row>
|
|
<entry class="bitfield">11</entry>
|
|
<entry class="symbol">270</entry>
|
|
</row>
|
|
</tbody>
|
|
</tgroup>
|
|
</table>
|
|
</definition>
|
|
</account>
|
|
<account iclass="simd_3sameext" symbol="<rotate>" iclass_long="Advanced SIMD three registers of the same length extension">
|
|
<encodings>
|
|
<encoding encname="VCMLA_T1_D" />
|
|
<encoding encname="VCMLA_T1_Q" />
|
|
</encodings>
|
|
<orig>Is the rotation to be applied to elements in the second SIMD&FP source register, encoded in "rot", where 00->0, 01->90, 10->180, 11->270.</orig>
|
|
<definition encodedin="rot">
|
|
<intro>Is the rotation to be applied to elements in the second SIMD&FP source register, </intro>
|
|
<table class="valuetable">
|
|
<tgroup cols="2">
|
|
<thead>
|
|
<row>
|
|
<entry class="bitfield" bitwidth="2">rot</entry>
|
|
<entry class="symbol"><rotate></entry>
|
|
</row>
|
|
</thead>
|
|
<tbody>
|
|
<row>
|
|
<entry class="bitfield">00</entry>
|
|
<entry class="symbol">0</entry>
|
|
</row>
|
|
<row>
|
|
<entry class="bitfield">01</entry>
|
|
<entry class="symbol">90</entry>
|
|
</row>
|
|
<row>
|
|
<entry class="bitfield">10</entry>
|
|
<entry class="symbol">180</entry>
|
|
</row>
|
|
<row>
|
|
<entry class="bitfield">11</entry>
|
|
<entry class="symbol">270</entry>
|
|
</row>
|
|
</tbody>
|
|
</tgroup>
|
|
</table>
|
|
</definition>
|
|
</account>
|
|
<account iclass="simd2reg_scalar" symbol="<dt>" iclass_long="Advanced SIMD two registers and a scalar">
|
|
<encodings>
|
|
<encoding encname="VQDMLAL_A2" />
|
|
<encoding encname="VQDMLSL_A2" />
|
|
<encoding encname="VQDMULH_A2_D" />
|
|
<encoding encname="VQDMULH_A2_Q" />
|
|
<encoding encname="VQDMULL_A2" />
|
|
<encoding encname="VQRDMLAH_A2_D" />
|
|
<encoding encname="VQRDMLAH_A2_Q" />
|
|
<encoding encname="VQRDMLSH_A2_D" />
|
|
<encoding encname="VQRDMLSH_A2_Q" />
|
|
<encoding encname="VQRDMULH_A2_D" />
|
|
<encoding encname="VQRDMULH_A2_Q" />
|
|
</encodings>
|
|
<orig>Is the data type for the elements of the operands, encoded in "size", where 01->S16, 10->S32</orig>
|
|
<definition encodedin="size">
|
|
<intro>Is the data type for the elements of the operands, </intro>
|
|
<table class="valuetable">
|
|
<tgroup cols="2">
|
|
<thead>
|
|
<row>
|
|
<entry class="bitfield" bitwidth="2">size</entry>
|
|
<entry class="symbol"><dt></entry>
|
|
</row>
|
|
</thead>
|
|
<tbody>
|
|
<row>
|
|
<entry class="bitfield">01</entry>
|
|
<entry class="symbol">S16</entry>
|
|
</row>
|
|
<row>
|
|
<entry class="bitfield">10</entry>
|
|
<entry class="symbol">S32</entry>
|
|
</row>
|
|
</tbody>
|
|
</tgroup>
|
|
</table>
|
|
</definition>
|
|
</account>
|
|
<account iclass="simd_2r_sc" symbol="<dt>" iclass_long="Advanced SIMD two registers and a scalar">
|
|
<encodings>
|
|
<encoding encname="VQDMLAL_T2" />
|
|
<encoding encname="VQDMLSL_T2" />
|
|
<encoding encname="VQDMULH_T2_D" />
|
|
<encoding encname="VQDMULH_T2_Q" />
|
|
<encoding encname="VQDMULL_T2" />
|
|
<encoding encname="VQRDMLAH_T2_D" />
|
|
<encoding encname="VQRDMLAH_T2_Q" />
|
|
<encoding encname="VQRDMLSH_T2_D" />
|
|
<encoding encname="VQRDMLSH_T2_Q" />
|
|
<encoding encname="VQRDMULH_T2_D" />
|
|
<encoding encname="VQRDMULH_T2_Q" />
|
|
</encodings>
|
|
<orig>Is the data type for the elements of the operands, encoded in "size", where 01->S16, 10->S32</orig>
|
|
<definition encodedin="size">
|
|
<intro>Is the data type for the elements of the operands, </intro>
|
|
<table class="valuetable">
|
|
<tgroup cols="2">
|
|
<thead>
|
|
<row>
|
|
<entry class="bitfield" bitwidth="2">size</entry>
|
|
<entry class="symbol"><dt></entry>
|
|
</row>
|
|
</thead>
|
|
<tbody>
|
|
<row>
|
|
<entry class="bitfield">01</entry>
|
|
<entry class="symbol">S16</entry>
|
|
</row>
|
|
<row>
|
|
<entry class="bitfield">10</entry>
|
|
<entry class="symbol">S32</entry>
|
|
</row>
|
|
</tbody>
|
|
</tgroup>
|
|
</table>
|
|
</definition>
|
|
</account>
|
|
<account iclass="simd2reg_scalar" symbol="<dt>" iclass_long="Advanced SIMD two registers and a scalar">
|
|
<encodings>
|
|
<encoding encname="VMLA_s_A1_D" />
|
|
<encoding encname="VMLA_s_A1_Q" />
|
|
<encoding encname="VMLS_s_A1_D" />
|
|
<encoding encname="VMLS_s_A1_Q" />
|
|
<encoding encname="VMUL_s_A1_D" />
|
|
<encoding encname="VMUL_s_A1_Q" />
|
|
</encodings>
|
|
<orig>Is the data type for the scalar and the elements of the operand vector, encoded in "F:size", where 001->I16, 010->I32, 101->F16, 110->F32</orig>
|
|
<definition encodedin="F:size">
|
|
<intro>Is the data type for the scalar and the elements of the operand vector, </intro>
|
|
<table class="valuetable">
|
|
<tgroup cols="3">
|
|
<thead>
|
|
<row>
|
|
<entry class="bitfield" bitwidth="1">F</entry>
|
|
<entry class="bitfield" bitwidth="2">size</entry>
|
|
<entry class="symbol"><dt></entry>
|
|
</row>
|
|
</thead>
|
|
<tbody>
|
|
<row>
|
|
<entry class="bitfield">0</entry>
|
|
<entry class="bitfield">01</entry>
|
|
<entry class="symbol">I16</entry>
|
|
</row>
|
|
<row>
|
|
<entry class="bitfield">0</entry>
|
|
<entry class="bitfield">10</entry>
|
|
<entry class="symbol">I32</entry>
|
|
</row>
|
|
<row>
|
|
<entry class="bitfield">1</entry>
|
|
<entry class="bitfield">01</entry>
|
|
<entry class="symbol">F16</entry>
|
|
</row>
|
|
<row>
|
|
<entry class="bitfield">1</entry>
|
|
<entry class="bitfield">10</entry>
|
|
<entry class="symbol">F32</entry>
|
|
</row>
|
|
</tbody>
|
|
</tgroup>
|
|
</table>
|
|
</definition>
|
|
</account>
|
|
<account iclass="simd_2r_sc" symbol="<dt>" iclass_long="Advanced SIMD two registers and a scalar">
|
|
<encodings>
|
|
<encoding encname="VMLA_s_T1_D" />
|
|
<encoding encname="VMLA_s_T1_Q" />
|
|
<encoding encname="VMLS_s_T1_D" />
|
|
<encoding encname="VMLS_s_T1_Q" />
|
|
<encoding encname="VMUL_s_T1_D" />
|
|
<encoding encname="VMUL_s_T1_Q" />
|
|
</encodings>
|
|
<orig>Is the data type for the scalar and the elements of the operand vector, encoded in "F:size", where 001->I16, 010->I32, 101->F16, 110->F32</orig>
|
|
<definition encodedin="F:size">
|
|
<intro>Is the data type for the scalar and the elements of the operand vector, </intro>
|
|
<table class="valuetable">
|
|
<tgroup cols="3">
|
|
<thead>
|
|
<row>
|
|
<entry class="bitfield" bitwidth="1">F</entry>
|
|
<entry class="bitfield" bitwidth="2">size</entry>
|
|
<entry class="symbol"><dt></entry>
|
|
</row>
|
|
</thead>
|
|
<tbody>
|
|
<row>
|
|
<entry class="bitfield">0</entry>
|
|
<entry class="bitfield">01</entry>
|
|
<entry class="symbol">I16</entry>
|
|
</row>
|
|
<row>
|
|
<entry class="bitfield">0</entry>
|
|
<entry class="bitfield">10</entry>
|
|
<entry class="symbol">I32</entry>
|
|
</row>
|
|
<row>
|
|
<entry class="bitfield">1</entry>
|
|
<entry class="bitfield">01</entry>
|
|
<entry class="symbol">F16</entry>
|
|
</row>
|
|
<row>
|
|
<entry class="bitfield">1</entry>
|
|
<entry class="bitfield">10</entry>
|
|
<entry class="symbol">F32</entry>
|
|
</row>
|
|
</tbody>
|
|
</tgroup>
|
|
</table>
|
|
</definition>
|
|
</account>
|
|
<account iclass="simd2reg_scalar" symbol="<dt>" iclass_long="Advanced SIMD two registers and a scalar">
|
|
<encodings>
|
|
<encoding encname="VMLAL_s_A1" />
|
|
<encoding encname="VMLSL_s_A1" />
|
|
<encoding encname="VMULL_s_A1" />
|
|
</encodings>
|
|
<orig>Is the data type for the scalar and the elements of the operand vector, encoded in "U:size", where 001->S16, 010->S32, 101->U16, 110->U32</orig>
|
|
<definition encodedin="U:size">
|
|
<intro>Is the data type for the scalar and the elements of the operand vector, </intro>
|
|
<table class="valuetable">
|
|
<tgroup cols="3">
|
|
<thead>
|
|
<row>
|
|
<entry class="bitfield" bitwidth="1">U</entry>
|
|
<entry class="bitfield" bitwidth="2">size</entry>
|
|
<entry class="symbol"><dt></entry>
|
|
</row>
|
|
</thead>
|
|
<tbody>
|
|
<row>
|
|
<entry class="bitfield">0</entry>
|
|
<entry class="bitfield">01</entry>
|
|
<entry class="symbol">S16</entry>
|
|
</row>
|
|
<row>
|
|
<entry class="bitfield">0</entry>
|
|
<entry class="bitfield">10</entry>
|
|
<entry class="symbol">S32</entry>
|
|
</row>
|
|
<row>
|
|
<entry class="bitfield">1</entry>
|
|
<entry class="bitfield">01</entry>
|
|
<entry class="symbol">U16</entry>
|
|
</row>
|
|
<row>
|
|
<entry class="bitfield">1</entry>
|
|
<entry class="bitfield">10</entry>
|
|
<entry class="symbol">U32</entry>
|
|
</row>
|
|
</tbody>
|
|
</tgroup>
|
|
</table>
|
|
</definition>
|
|
</account>
|
|
<account iclass="simd_2r_sc" symbol="<dt>" iclass_long="Advanced SIMD two registers and a scalar">
|
|
<encodings>
|
|
<encoding encname="VMLAL_s_T1" />
|
|
<encoding encname="VMLSL_s_T1" />
|
|
<encoding encname="VMULL_s_T1" />
|
|
</encodings>
|
|
<orig>Is the data type for the scalar and the elements of the operand vector, encoded in "U:size", where 001->S16, 010->S32, 101->U16, 110->U32</orig>
|
|
<definition encodedin="U:size">
|
|
<intro>Is the data type for the scalar and the elements of the operand vector, </intro>
|
|
<table class="valuetable">
|
|
<tgroup cols="3">
|
|
<thead>
|
|
<row>
|
|
<entry class="bitfield" bitwidth="1">U</entry>
|
|
<entry class="bitfield" bitwidth="2">size</entry>
|
|
<entry class="symbol"><dt></entry>
|
|
</row>
|
|
</thead>
|
|
<tbody>
|
|
<row>
|
|
<entry class="bitfield">0</entry>
|
|
<entry class="bitfield">01</entry>
|
|
<entry class="symbol">S16</entry>
|
|
</row>
|
|
<row>
|
|
<entry class="bitfield">0</entry>
|
|
<entry class="bitfield">10</entry>
|
|
<entry class="symbol">S32</entry>
|
|
</row>
|
|
<row>
|
|
<entry class="bitfield">1</entry>
|
|
<entry class="bitfield">01</entry>
|
|
<entry class="symbol">U16</entry>
|
|
</row>
|
|
<row>
|
|
<entry class="bitfield">1</entry>
|
|
<entry class="bitfield">10</entry>
|
|
<entry class="symbol">U32</entry>
|
|
</row>
|
|
</tbody>
|
|
</tgroup>
|
|
</table>
|
|
</definition>
|
|
</account>
|
|
<account iclass="simd2reg_shift" symbol="<size>" iclass_long="Advanced SIMD two registers and shift amount">
|
|
<encodings>
|
|
<encoding encname="VQSHLU_i_A1_D" />
|
|
<encoding encname="VQSHLU_i_A1_Q" />
|
|
<encoding encname="VQSHL_i_A1_D" />
|
|
<encoding encname="VQSHL_i_A1_Q" />
|
|
<encoding encname="VRSHR_A1_D" />
|
|
<encoding encname="VRSHR_A1_Q" />
|
|
<encoding encname="VRSRA_A1_D" />
|
|
<encoding encname="VRSRA_A1_Q" />
|
|
<encoding encname="VSHL_i_A1_D" />
|
|
<encoding encname="VSHL_i_A1_Q" />
|
|
<encoding encname="VSHR_A1_D" />
|
|
<encoding encname="VSHR_A1_Q" />
|
|
<encoding encname="VSLI_A1_D" />
|
|
<encoding encname="VSLI_A1_Q" />
|
|
<encoding encname="VSRA_A1_D" />
|
|
<encoding encname="VSRA_A1_Q" />
|
|
<encoding encname="VSRI_A1_D" />
|
|
<encoding encname="VSRI_A1_Q" />
|
|
</encodings>
|
|
<orig>Is the data size for the elements of the vectors, encoded in the "L:imm6<5:3>" field, where 0001->8, 001x->16, 01xx->32, 1xxx->64.</orig>
|
|
<definition encodedin="L:imm6<5:3>">
|
|
<intro>Is the data size for the elements of the vectors, </intro>
|
|
<table class="valuetable">
|
|
<tgroup cols="3">
|
|
<thead>
|
|
<row>
|
|
<entry class="bitfield" bitwidth="1">L</entry>
|
|
<entry class="bitfield" bitwidth="3">imm6<5:3></entry>
|
|
<entry class="symbol"><size></entry>
|
|
</row>
|
|
</thead>
|
|
<tbody>
|
|
<row>
|
|
<entry class="bitfield">0</entry>
|
|
<entry class="bitfield">001</entry>
|
|
<entry class="symbol">8</entry>
|
|
</row>
|
|
<row>
|
|
<entry class="bitfield">0</entry>
|
|
<entry class="bitfield">01x</entry>
|
|
<entry class="symbol">16</entry>
|
|
</row>
|
|
<row>
|
|
<entry class="bitfield">0</entry>
|
|
<entry class="bitfield">1xx</entry>
|
|
<entry class="symbol">32</entry>
|
|
</row>
|
|
<row>
|
|
<entry class="bitfield">1</entry>
|
|
<entry class="bitfield">xxx</entry>
|
|
<entry class="symbol">64</entry>
|
|
</row>
|
|
</tbody>
|
|
</tgroup>
|
|
</table>
|
|
</definition>
|
|
</account>
|
|
<account iclass="simd_2r_shift" symbol="<size>" iclass_long="Advanced SIMD two registers and shift amount">
|
|
<encodings>
|
|
<encoding encname="VQSHLU_i_T1_D" />
|
|
<encoding encname="VQSHLU_i_T1_Q" />
|
|
<encoding encname="VQSHL_i_T1_D" />
|
|
<encoding encname="VQSHL_i_T1_Q" />
|
|
<encoding encname="VRSHR_T1_D" />
|
|
<encoding encname="VRSHR_T1_Q" />
|
|
<encoding encname="VRSRA_T1_D" />
|
|
<encoding encname="VRSRA_T1_Q" />
|
|
<encoding encname="VSHL_i_T1_D" />
|
|
<encoding encname="VSHL_i_T1_Q" />
|
|
<encoding encname="VSHR_T1_D" />
|
|
<encoding encname="VSHR_T1_Q" />
|
|
<encoding encname="VSLI_T1_D" />
|
|
<encoding encname="VSLI_T1_Q" />
|
|
<encoding encname="VSRA_T1_D" />
|
|
<encoding encname="VSRA_T1_Q" />
|
|
<encoding encname="VSRI_T1_D" />
|
|
<encoding encname="VSRI_T1_Q" />
|
|
</encodings>
|
|
<orig>Is the data size for the elements of the vectors, encoded in the "L:imm6<5:3>" field, where 0001->8, 001x->16, 01xx->32, 1xxx->64.</orig>
|
|
<definition encodedin="L:imm6<5:3>">
|
|
<intro>Is the data size for the elements of the vectors, </intro>
|
|
<table class="valuetable">
|
|
<tgroup cols="3">
|
|
<thead>
|
|
<row>
|
|
<entry class="bitfield" bitwidth="1">L</entry>
|
|
<entry class="bitfield" bitwidth="3">imm6<5:3></entry>
|
|
<entry class="symbol"><size></entry>
|
|
</row>
|
|
</thead>
|
|
<tbody>
|
|
<row>
|
|
<entry class="bitfield">0</entry>
|
|
<entry class="bitfield">001</entry>
|
|
<entry class="symbol">8</entry>
|
|
</row>
|
|
<row>
|
|
<entry class="bitfield">0</entry>
|
|
<entry class="bitfield">01x</entry>
|
|
<entry class="symbol">16</entry>
|
|
</row>
|
|
<row>
|
|
<entry class="bitfield">0</entry>
|
|
<entry class="bitfield">1xx</entry>
|
|
<entry class="symbol">32</entry>
|
|
</row>
|
|
<row>
|
|
<entry class="bitfield">1</entry>
|
|
<entry class="bitfield">xxx</entry>
|
|
<entry class="symbol">64</entry>
|
|
</row>
|
|
</tbody>
|
|
</tgroup>
|
|
</table>
|
|
</definition>
|
|
</account>
|
|
<account iclass="simd2reg_shift" symbol="<size>" iclass_long="Advanced SIMD two registers and shift amount">
|
|
<encodings>
|
|
<encoding encname="VQRSHRN_A1" />
|
|
<encoding encname="VQRSHRUN_A1" />
|
|
<encoding encname="VQSHRN_A1" />
|
|
<encoding encname="VQSHRUN_A1" />
|
|
<encoding encname="VRSHRN_A1" />
|
|
<encoding encname="VSHRN_A1" />
|
|
</encodings>
|
|
<orig>Is the data size for the elements of the vectors, encoded in the "imm6<5:3>" field, where 001->16, 01x->32, 1xx->64.</orig>
|
|
<definition encodedin="imm6<5:3>">
|
|
<intro>Is the data size for the elements of the vectors, </intro>
|
|
<table class="valuetable">
|
|
<tgroup cols="2">
|
|
<thead>
|
|
<row>
|
|
<entry class="bitfield" bitwidth="3">imm6<5:3></entry>
|
|
<entry class="symbol"><size></entry>
|
|
</row>
|
|
</thead>
|
|
<tbody>
|
|
<row>
|
|
<entry class="bitfield">001</entry>
|
|
<entry class="symbol">16</entry>
|
|
</row>
|
|
<row>
|
|
<entry class="bitfield">01x</entry>
|
|
<entry class="symbol">32</entry>
|
|
</row>
|
|
<row>
|
|
<entry class="bitfield">1xx</entry>
|
|
<entry class="symbol">64</entry>
|
|
</row>
|
|
</tbody>
|
|
</tgroup>
|
|
</table>
|
|
</definition>
|
|
</account>
|
|
<account iclass="simd_2r_shift" symbol="<size>" iclass_long="Advanced SIMD two registers and shift amount">
|
|
<encodings>
|
|
<encoding encname="VQRSHRN_T1" />
|
|
<encoding encname="VQRSHRUN_T1" />
|
|
<encoding encname="VQSHRN_T1" />
|
|
<encoding encname="VQSHRUN_T1" />
|
|
<encoding encname="VRSHRN_T1" />
|
|
<encoding encname="VSHRN_T1" />
|
|
</encodings>
|
|
<orig>Is the data size for the elements of the vectors, encoded in the "imm6<5:3>" field, where 001->16, 01x->32, 1xx->64.</orig>
|
|
<definition encodedin="imm6<5:3>">
|
|
<intro>Is the data size for the elements of the vectors, </intro>
|
|
<table class="valuetable">
|
|
<tgroup cols="2">
|
|
<thead>
|
|
<row>
|
|
<entry class="bitfield" bitwidth="3">imm6<5:3></entry>
|
|
<entry class="symbol"><size></entry>
|
|
</row>
|
|
</thead>
|
|
<tbody>
|
|
<row>
|
|
<entry class="bitfield">001</entry>
|
|
<entry class="symbol">16</entry>
|
|
</row>
|
|
<row>
|
|
<entry class="bitfield">01x</entry>
|
|
<entry class="symbol">32</entry>
|
|
</row>
|
|
<row>
|
|
<entry class="bitfield">1xx</entry>
|
|
<entry class="symbol">64</entry>
|
|
</row>
|
|
</tbody>
|
|
</tgroup>
|
|
</table>
|
|
</definition>
|
|
</account>
|
|
<account iclass="simd2reg_shift" symbol="<dt1>" iclass_long="Advanced SIMD two registers and shift amount">
|
|
<encodings>
|
|
<encoding encname="VCVT_xs_A1_D" />
|
|
<encoding encname="VCVT_xs_A1_Q" />
|
|
</encodings>
|
|
<orig>Is the data type for the elements of the destination vector, encoded in "op:U" where 00x->F16, 010->S16, 011->U16, 10x->F32, 110->S32, 111->U32</orig>
|
|
<definition encodedin="op:U">
|
|
<intro>Is the data type for the elements of the destination vector, </intro>
|
|
<table class="valuetable">
|
|
<tgroup cols="3">
|
|
<thead>
|
|
<row>
|
|
<entry class="bitfield" bitwidth="2">op</entry>
|
|
<entry class="bitfield" bitwidth="1">U</entry>
|
|
<entry class="symbol"><dt1></entry>
|
|
</row>
|
|
</thead>
|
|
<tbody>
|
|
<row>
|
|
<entry class="bitfield">00</entry>
|
|
<entry class="bitfield">x</entry>
|
|
<entry class="symbol">F16</entry>
|
|
</row>
|
|
<row>
|
|
<entry class="bitfield">01</entry>
|
|
<entry class="bitfield">0</entry>
|
|
<entry class="symbol">S16</entry>
|
|
</row>
|
|
<row>
|
|
<entry class="bitfield">01</entry>
|
|
<entry class="bitfield">1</entry>
|
|
<entry class="symbol">U16</entry>
|
|
</row>
|
|
<row>
|
|
<entry class="bitfield">10</entry>
|
|
<entry class="bitfield">x</entry>
|
|
<entry class="symbol">F32</entry>
|
|
</row>
|
|
<row>
|
|
<entry class="bitfield">11</entry>
|
|
<entry class="bitfield">0</entry>
|
|
<entry class="symbol">S32</entry>
|
|
</row>
|
|
<row>
|
|
<entry class="bitfield">11</entry>
|
|
<entry class="bitfield">1</entry>
|
|
<entry class="symbol">U32</entry>
|
|
</row>
|
|
</tbody>
|
|
</tgroup>
|
|
</table>
|
|
</definition>
|
|
</account>
|
|
<account iclass="simd_2r_shift" symbol="<dt1>" iclass_long="Advanced SIMD two registers and shift amount">
|
|
<encodings>
|
|
<encoding encname="VCVT_xs_T1_D" />
|
|
<encoding encname="VCVT_xs_T1_Q" />
|
|
</encodings>
|
|
<orig>Is the data type for the elements of the destination vector, encoded in "op:U" where 00x->F16, 010->S16, 011->U16, 10x->F32, 110->S32, 111->U32</orig>
|
|
<definition encodedin="op:U">
|
|
<intro>Is the data type for the elements of the destination vector, </intro>
|
|
<table class="valuetable">
|
|
<tgroup cols="3">
|
|
<thead>
|
|
<row>
|
|
<entry class="bitfield" bitwidth="2">op</entry>
|
|
<entry class="bitfield" bitwidth="1">U</entry>
|
|
<entry class="symbol"><dt1></entry>
|
|
</row>
|
|
</thead>
|
|
<tbody>
|
|
<row>
|
|
<entry class="bitfield">00</entry>
|
|
<entry class="bitfield">x</entry>
|
|
<entry class="symbol">F16</entry>
|
|
</row>
|
|
<row>
|
|
<entry class="bitfield">01</entry>
|
|
<entry class="bitfield">0</entry>
|
|
<entry class="symbol">S16</entry>
|
|
</row>
|
|
<row>
|
|
<entry class="bitfield">01</entry>
|
|
<entry class="bitfield">1</entry>
|
|
<entry class="symbol">U16</entry>
|
|
</row>
|
|
<row>
|
|
<entry class="bitfield">10</entry>
|
|
<entry class="bitfield">x</entry>
|
|
<entry class="symbol">F32</entry>
|
|
</row>
|
|
<row>
|
|
<entry class="bitfield">11</entry>
|
|
<entry class="bitfield">0</entry>
|
|
<entry class="symbol">S32</entry>
|
|
</row>
|
|
<row>
|
|
<entry class="bitfield">11</entry>
|
|
<entry class="bitfield">1</entry>
|
|
<entry class="symbol">U32</entry>
|
|
</row>
|
|
</tbody>
|
|
</tgroup>
|
|
</table>
|
|
</definition>
|
|
</account>
|
|
<account iclass="simd2reg_shift" symbol="<dt>" iclass_long="Advanced SIMD two registers and shift amount">
|
|
<encodings>
|
|
<encoding encname="VMOVL_A1" />
|
|
</encodings>
|
|
<orig>Is the data type for the elements of the operand, encoded in "U:imm3H" where 0001->S8, 0010->S16, 0100->S32, 1001->U8, 1010->U16, 1100->U32</orig>
|
|
<definition encodedin="U:imm3H">
|
|
<intro>Is the data type for the elements of the operand, </intro>
|
|
<table class="valuetable">
|
|
<tgroup cols="3">
|
|
<thead>
|
|
<row>
|
|
<entry class="bitfield" bitwidth="1">U</entry>
|
|
<entry class="bitfield" bitwidth="3">imm3H</entry>
|
|
<entry class="symbol"><dt></entry>
|
|
</row>
|
|
</thead>
|
|
<tbody>
|
|
<row>
|
|
<entry class="bitfield">0</entry>
|
|
<entry class="bitfield">001</entry>
|
|
<entry class="symbol">S8</entry>
|
|
</row>
|
|
<row>
|
|
<entry class="bitfield">0</entry>
|
|
<entry class="bitfield">010</entry>
|
|
<entry class="symbol">S16</entry>
|
|
</row>
|
|
<row>
|
|
<entry class="bitfield">0</entry>
|
|
<entry class="bitfield">100</entry>
|
|
<entry class="symbol">S32</entry>
|
|
</row>
|
|
<row>
|
|
<entry class="bitfield">1</entry>
|
|
<entry class="bitfield">001</entry>
|
|
<entry class="symbol">U8</entry>
|
|
</row>
|
|
<row>
|
|
<entry class="bitfield">1</entry>
|
|
<entry class="bitfield">010</entry>
|
|
<entry class="symbol">U16</entry>
|
|
</row>
|
|
<row>
|
|
<entry class="bitfield">1</entry>
|
|
<entry class="bitfield">100</entry>
|
|
<entry class="symbol">U32</entry>
|
|
</row>
|
|
</tbody>
|
|
</tgroup>
|
|
</table>
|
|
</definition>
|
|
</account>
|
|
<account iclass="simd_2r_shift" symbol="<dt>" iclass_long="Advanced SIMD two registers and shift amount">
|
|
<encodings>
|
|
<encoding encname="VMOVL_T1" />
|
|
</encodings>
|
|
<orig>Is the data type for the elements of the operand, encoded in "U:imm3H" where 0001->S8, 0010->S16, 0100->S32, 1001->U8, 1010->U16, 1100->U32</orig>
|
|
<definition encodedin="U:imm3H">
|
|
<intro>Is the data type for the elements of the operand, </intro>
|
|
<table class="valuetable">
|
|
<tgroup cols="3">
|
|
<thead>
|
|
<row>
|
|
<entry class="bitfield" bitwidth="1">U</entry>
|
|
<entry class="bitfield" bitwidth="3">imm3H</entry>
|
|
<entry class="symbol"><dt></entry>
|
|
</row>
|
|
</thead>
|
|
<tbody>
|
|
<row>
|
|
<entry class="bitfield">0</entry>
|
|
<entry class="bitfield">001</entry>
|
|
<entry class="symbol">S8</entry>
|
|
</row>
|
|
<row>
|
|
<entry class="bitfield">0</entry>
|
|
<entry class="bitfield">010</entry>
|
|
<entry class="symbol">S16</entry>
|
|
</row>
|
|
<row>
|
|
<entry class="bitfield">0</entry>
|
|
<entry class="bitfield">100</entry>
|
|
<entry class="symbol">S32</entry>
|
|
</row>
|
|
<row>
|
|
<entry class="bitfield">1</entry>
|
|
<entry class="bitfield">001</entry>
|
|
<entry class="symbol">U8</entry>
|
|
</row>
|
|
<row>
|
|
<entry class="bitfield">1</entry>
|
|
<entry class="bitfield">010</entry>
|
|
<entry class="symbol">U16</entry>
|
|
</row>
|
|
<row>
|
|
<entry class="bitfield">1</entry>
|
|
<entry class="bitfield">100</entry>
|
|
<entry class="symbol">U32</entry>
|
|
</row>
|
|
</tbody>
|
|
</tgroup>
|
|
</table>
|
|
</definition>
|
|
</account>
|
|
<account iclass="simd2reg_shift" symbol="<dt2>" iclass_long="Advanced SIMD two registers and shift amount">
|
|
<encodings>
|
|
<encoding encname="VCVT_xs_A1_D" />
|
|
<encoding encname="VCVT_xs_A1_Q" />
|
|
</encodings>
|
|
<orig>Is the data type for the elements of the source vector, encoded in "op:U" where 000->S16, 001->U16, 01x->F16, 100->S32, 101->U32, 11x->F32</orig>
|
|
<definition encodedin="op:U">
|
|
<intro>Is the data type for the elements of the source vector, </intro>
|
|
<table class="valuetable">
|
|
<tgroup cols="3">
|
|
<thead>
|
|
<row>
|
|
<entry class="bitfield" bitwidth="2">op</entry>
|
|
<entry class="bitfield" bitwidth="1">U</entry>
|
|
<entry class="symbol"><dt2></entry>
|
|
</row>
|
|
</thead>
|
|
<tbody>
|
|
<row>
|
|
<entry class="bitfield">00</entry>
|
|
<entry class="bitfield">0</entry>
|
|
<entry class="symbol">S16</entry>
|
|
</row>
|
|
<row>
|
|
<entry class="bitfield">00</entry>
|
|
<entry class="bitfield">1</entry>
|
|
<entry class="symbol">U16</entry>
|
|
</row>
|
|
<row>
|
|
<entry class="bitfield">01</entry>
|
|
<entry class="bitfield">x</entry>
|
|
<entry class="symbol">F16</entry>
|
|
</row>
|
|
<row>
|
|
<entry class="bitfield">10</entry>
|
|
<entry class="bitfield">0</entry>
|
|
<entry class="symbol">S32</entry>
|
|
</row>
|
|
<row>
|
|
<entry class="bitfield">10</entry>
|
|
<entry class="bitfield">1</entry>
|
|
<entry class="symbol">U32</entry>
|
|
</row>
|
|
<row>
|
|
<entry class="bitfield">11</entry>
|
|
<entry class="bitfield">x</entry>
|
|
<entry class="symbol">F32</entry>
|
|
</row>
|
|
</tbody>
|
|
</tgroup>
|
|
</table>
|
|
</definition>
|
|
</account>
|
|
<account iclass="simd_2r_shift" symbol="<dt2>" iclass_long="Advanced SIMD two registers and shift amount">
|
|
<encodings>
|
|
<encoding encname="VCVT_xs_T1_D" />
|
|
<encoding encname="VCVT_xs_T1_Q" />
|
|
</encodings>
|
|
<orig>Is the data type for the elements of the source vector, encoded in "op:U" where 000->S16, 001->U16, 01x->F16, 100->S32, 101->U32, 11x->F32</orig>
|
|
<definition encodedin="op:U">
|
|
<intro>Is the data type for the elements of the source vector, </intro>
|
|
<table class="valuetable">
|
|
<tgroup cols="3">
|
|
<thead>
|
|
<row>
|
|
<entry class="bitfield" bitwidth="2">op</entry>
|
|
<entry class="bitfield" bitwidth="1">U</entry>
|
|
<entry class="symbol"><dt2></entry>
|
|
</row>
|
|
</thead>
|
|
<tbody>
|
|
<row>
|
|
<entry class="bitfield">00</entry>
|
|
<entry class="bitfield">0</entry>
|
|
<entry class="symbol">S16</entry>
|
|
</row>
|
|
<row>
|
|
<entry class="bitfield">00</entry>
|
|
<entry class="bitfield">1</entry>
|
|
<entry class="symbol">U16</entry>
|
|
</row>
|
|
<row>
|
|
<entry class="bitfield">01</entry>
|
|
<entry class="bitfield">x</entry>
|
|
<entry class="symbol">F16</entry>
|
|
</row>
|
|
<row>
|
|
<entry class="bitfield">10</entry>
|
|
<entry class="bitfield">0</entry>
|
|
<entry class="symbol">S32</entry>
|
|
</row>
|
|
<row>
|
|
<entry class="bitfield">10</entry>
|
|
<entry class="bitfield">1</entry>
|
|
<entry class="symbol">U32</entry>
|
|
</row>
|
|
<row>
|
|
<entry class="bitfield">11</entry>
|
|
<entry class="bitfield">x</entry>
|
|
<entry class="symbol">F32</entry>
|
|
</row>
|
|
</tbody>
|
|
</tgroup>
|
|
</table>
|
|
</definition>
|
|
</account>
|
|
<account iclass="simd2reg_shift" symbol="<type>" iclass_long="Advanced SIMD two registers and shift amount">
|
|
<encodings>
|
|
<encoding encname="VQRSHRN_A1" />
|
|
<encoding encname="VQSHLU_i_A1_D" />
|
|
<encoding encname="VQSHLU_i_A1_Q" />
|
|
<encoding encname="VQSHL_i_A1_D" />
|
|
<encoding encname="VQSHL_i_A1_Q" />
|
|
<encoding encname="VQSHRN_A1" />
|
|
<encoding encname="VRSHR_A1_D" />
|
|
<encoding encname="VRSHR_A1_Q" />
|
|
<encoding encname="VRSRA_A1_D" />
|
|
<encoding encname="VRSRA_A1_Q" />
|
|
<encoding encname="VSHR_A1_D" />
|
|
<encoding encname="VSHR_A1_Q" />
|
|
<encoding encname="VSRA_A1_D" />
|
|
<encoding encname="VSRA_A1_Q" />
|
|
</encodings>
|
|
<orig>Is the data type for the elements of the vectors, encoded in the "U" field, where 0->S, 1->U.</orig>
|
|
<definition encodedin="U">
|
|
<intro>Is the data type for the elements of the vectors, </intro>
|
|
<table class="valuetable">
|
|
<tgroup cols="2">
|
|
<thead>
|
|
<row>
|
|
<entry class="bitfield" bitwidth="1">U</entry>
|
|
<entry class="symbol"><type></entry>
|
|
</row>
|
|
</thead>
|
|
<tbody>
|
|
<row>
|
|
<entry class="bitfield">0</entry>
|
|
<entry class="symbol">S</entry>
|
|
</row>
|
|
<row>
|
|
<entry class="bitfield">1</entry>
|
|
<entry class="symbol">U</entry>
|
|
</row>
|
|
</tbody>
|
|
</tgroup>
|
|
</table>
|
|
</definition>
|
|
</account>
|
|
<account iclass="simd_2r_shift" symbol="<type>" iclass_long="Advanced SIMD two registers and shift amount">
|
|
<encodings>
|
|
<encoding encname="VQRSHRN_T1" />
|
|
<encoding encname="VQSHLU_i_T1_D" />
|
|
<encoding encname="VQSHLU_i_T1_Q" />
|
|
<encoding encname="VQSHL_i_T1_D" />
|
|
<encoding encname="VQSHL_i_T1_Q" />
|
|
<encoding encname="VQSHRN_T1" />
|
|
<encoding encname="VRSHR_T1_D" />
|
|
<encoding encname="VRSHR_T1_Q" />
|
|
<encoding encname="VRSRA_T1_D" />
|
|
<encoding encname="VRSRA_T1_Q" />
|
|
<encoding encname="VSHR_T1_D" />
|
|
<encoding encname="VSHR_T1_Q" />
|
|
<encoding encname="VSRA_T1_D" />
|
|
<encoding encname="VSRA_T1_Q" />
|
|
</encodings>
|
|
<orig>Is the data type for the elements of the vectors, encoded in the "U" field, where 0->S, 1->U.</orig>
|
|
<definition encodedin="U">
|
|
<intro>Is the data type for the elements of the vectors, </intro>
|
|
<table class="valuetable">
|
|
<tgroup cols="2">
|
|
<thead>
|
|
<row>
|
|
<entry class="bitfield" bitwidth="1">U</entry>
|
|
<entry class="symbol"><type></entry>
|
|
</row>
|
|
</thead>
|
|
<tbody>
|
|
<row>
|
|
<entry class="bitfield">0</entry>
|
|
<entry class="symbol">S</entry>
|
|
</row>
|
|
<row>
|
|
<entry class="bitfield">1</entry>
|
|
<entry class="symbol">U</entry>
|
|
</row>
|
|
</tbody>
|
|
</tgroup>
|
|
</table>
|
|
</definition>
|
|
</account>
|
|
<account iclass="simd2reg_shift" symbol="<type>" iclass_long="Advanced SIMD two registers and shift amount">
|
|
<encodings>
|
|
<encoding encname="VQRSHRUN_A1" />
|
|
<encoding encname="VQSHRUN_A1" />
|
|
</encodings>
|
|
<orig>Is the data type for the elements of the vectors, encoded in the "U" field, where 1->S.</orig>
|
|
<definition encodedin="U">
|
|
<intro>Is the data type for the elements of the vectors, </intro>
|
|
<table class="valuetable">
|
|
<tgroup cols="2">
|
|
<thead>
|
|
<row>
|
|
<entry class="bitfield" bitwidth="1">U</entry>
|
|
<entry class="symbol"><type></entry>
|
|
</row>
|
|
</thead>
|
|
<tbody>
|
|
<row>
|
|
<entry class="bitfield">1</entry>
|
|
<entry class="symbol">S</entry>
|
|
</row>
|
|
</tbody>
|
|
</tgroup>
|
|
</table>
|
|
</definition>
|
|
</account>
|
|
<account iclass="simd_2r_shift" symbol="<type>" iclass_long="Advanced SIMD two registers and shift amount">
|
|
<encodings>
|
|
<encoding encname="VQRSHRUN_T1" />
|
|
<encoding encname="VQSHRUN_T1" />
|
|
</encodings>
|
|
<orig>Is the data type for the elements of the vectors, encoded in the "U" field, where 1->S.</orig>
|
|
<definition encodedin="U">
|
|
<intro>Is the data type for the elements of the vectors, </intro>
|
|
<table class="valuetable">
|
|
<tgroup cols="2">
|
|
<thead>
|
|
<row>
|
|
<entry class="bitfield" bitwidth="1">U</entry>
|
|
<entry class="symbol"><type></entry>
|
|
</row>
|
|
</thead>
|
|
<tbody>
|
|
<row>
|
|
<entry class="bitfield">1</entry>
|
|
<entry class="symbol">S</entry>
|
|
</row>
|
|
</tbody>
|
|
</tgroup>
|
|
</table>
|
|
</definition>
|
|
</account>
|
|
<account iclass="simd2reg_misc" symbol="<dt1>" iclass_long="Advanced SIMD two registers misc">
|
|
<encodings>
|
|
<encoding encname="VCVT_is_A1_D" />
|
|
<encoding encname="VCVT_is_A1_Q" />
|
|
</encodings>
|
|
<orig>Is the data type for the elements of the destination vector, encoded in "size:op" where 010x->F16, 0110->S16, 0111->U16, 100x->F32, 1010->S32, 1011->U32</orig>
|
|
<definition encodedin="size:op">
|
|
<intro>Is the data type for the elements of the destination vector, </intro>
|
|
<table class="valuetable">
|
|
<tgroup cols="3">
|
|
<thead>
|
|
<row>
|
|
<entry class="bitfield" bitwidth="2">size</entry>
|
|
<entry class="bitfield" bitwidth="2">op</entry>
|
|
<entry class="symbol"><dt1></entry>
|
|
</row>
|
|
</thead>
|
|
<tbody>
|
|
<row>
|
|
<entry class="bitfield">01</entry>
|
|
<entry class="bitfield">0x</entry>
|
|
<entry class="symbol">F16</entry>
|
|
</row>
|
|
<row>
|
|
<entry class="bitfield">01</entry>
|
|
<entry class="bitfield">10</entry>
|
|
<entry class="symbol">S16</entry>
|
|
</row>
|
|
<row>
|
|
<entry class="bitfield">01</entry>
|
|
<entry class="bitfield">11</entry>
|
|
<entry class="symbol">U16</entry>
|
|
</row>
|
|
<row>
|
|
<entry class="bitfield">10</entry>
|
|
<entry class="bitfield">0x</entry>
|
|
<entry class="symbol">F32</entry>
|
|
</row>
|
|
<row>
|
|
<entry class="bitfield">10</entry>
|
|
<entry class="bitfield">10</entry>
|
|
<entry class="symbol">S32</entry>
|
|
</row>
|
|
<row>
|
|
<entry class="bitfield">10</entry>
|
|
<entry class="bitfield">11</entry>
|
|
<entry class="symbol">U32</entry>
|
|
</row>
|
|
</tbody>
|
|
</tgroup>
|
|
</table>
|
|
</definition>
|
|
</account>
|
|
<account iclass="simd_2r_misc" symbol="<dt1>" iclass_long="Advanced SIMD two registers misc">
|
|
<encodings>
|
|
<encoding encname="VCVT_is_T1_D" />
|
|
<encoding encname="VCVT_is_T1_Q" />
|
|
</encodings>
|
|
<orig>Is the data type for the elements of the destination vector, encoded in "size:op" where 010x->F16, 0110->S16, 0111->U16, 100x->F32, 1010->S32, 1011->U32</orig>
|
|
<definition encodedin="size:op">
|
|
<intro>Is the data type for the elements of the destination vector, </intro>
|
|
<table class="valuetable">
|
|
<tgroup cols="3">
|
|
<thead>
|
|
<row>
|
|
<entry class="bitfield" bitwidth="2">size</entry>
|
|
<entry class="bitfield" bitwidth="2">op</entry>
|
|
<entry class="symbol"><dt1></entry>
|
|
</row>
|
|
</thead>
|
|
<tbody>
|
|
<row>
|
|
<entry class="bitfield">01</entry>
|
|
<entry class="bitfield">0x</entry>
|
|
<entry class="symbol">F16</entry>
|
|
</row>
|
|
<row>
|
|
<entry class="bitfield">01</entry>
|
|
<entry class="bitfield">10</entry>
|
|
<entry class="symbol">S16</entry>
|
|
</row>
|
|
<row>
|
|
<entry class="bitfield">01</entry>
|
|
<entry class="bitfield">11</entry>
|
|
<entry class="symbol">U16</entry>
|
|
</row>
|
|
<row>
|
|
<entry class="bitfield">10</entry>
|
|
<entry class="bitfield">0x</entry>
|
|
<entry class="symbol">F32</entry>
|
|
</row>
|
|
<row>
|
|
<entry class="bitfield">10</entry>
|
|
<entry class="bitfield">10</entry>
|
|
<entry class="symbol">S32</entry>
|
|
</row>
|
|
<row>
|
|
<entry class="bitfield">10</entry>
|
|
<entry class="bitfield">11</entry>
|
|
<entry class="symbol">U32</entry>
|
|
</row>
|
|
</tbody>
|
|
</tgroup>
|
|
</table>
|
|
</definition>
|
|
</account>
|
|
<account iclass="simd2reg_misc" symbol="<dt>" iclass_long="Advanced SIMD two registers misc">
|
|
<encodings>
|
|
<encoding encname="VCVTA_asimd_A1_D" />
|
|
<encoding encname="VCVTA_asimd_A1_Q" />
|
|
<encoding encname="VCVTM_asimd_A1_D" />
|
|
<encoding encname="VCVTM_asimd_A1_Q" />
|
|
<encoding encname="VCVTN_asimd_A1_D" />
|
|
<encoding encname="VCVTN_asimd_A1_Q" />
|
|
<encoding encname="VCVTP_asimd_A1_D" />
|
|
<encoding encname="VCVTP_asimd_A1_Q" />
|
|
</encodings>
|
|
<orig>Is the data type for the elements of the destination, encoded in "op:size", where 001->S16, 010->S32, 101->U16, 110->U32</orig>
|
|
<definition encodedin="op:size">
|
|
<intro>Is the data type for the elements of the destination, </intro>
|
|
<table class="valuetable">
|
|
<tgroup cols="3">
|
|
<thead>
|
|
<row>
|
|
<entry class="bitfield" bitwidth="1">op</entry>
|
|
<entry class="bitfield" bitwidth="2">size</entry>
|
|
<entry class="symbol"><dt></entry>
|
|
</row>
|
|
</thead>
|
|
<tbody>
|
|
<row>
|
|
<entry class="bitfield">0</entry>
|
|
<entry class="bitfield">01</entry>
|
|
<entry class="symbol">S16</entry>
|
|
</row>
|
|
<row>
|
|
<entry class="bitfield">0</entry>
|
|
<entry class="bitfield">10</entry>
|
|
<entry class="symbol">S32</entry>
|
|
</row>
|
|
<row>
|
|
<entry class="bitfield">1</entry>
|
|
<entry class="bitfield">01</entry>
|
|
<entry class="symbol">U16</entry>
|
|
</row>
|
|
<row>
|
|
<entry class="bitfield">1</entry>
|
|
<entry class="bitfield">10</entry>
|
|
<entry class="symbol">U32</entry>
|
|
</row>
|
|
</tbody>
|
|
</tgroup>
|
|
</table>
|
|
</definition>
|
|
</account>
|
|
<account iclass="simd_2r_misc" symbol="<dt>" iclass_long="Advanced SIMD two registers misc">
|
|
<encodings>
|
|
<encoding encname="VCVTA_asimd_T1_D" />
|
|
<encoding encname="VCVTA_asimd_T1_Q" />
|
|
<encoding encname="VCVTM_asimd_T1_D" />
|
|
<encoding encname="VCVTM_asimd_T1_Q" />
|
|
<encoding encname="VCVTN_asimd_T1_D" />
|
|
<encoding encname="VCVTN_asimd_T1_Q" />
|
|
<encoding encname="VCVTP_asimd_T1_D" />
|
|
<encoding encname="VCVTP_asimd_T1_Q" />
|
|
</encodings>
|
|
<orig>Is the data type for the elements of the destination, encoded in "op:size", where 001->S16, 010->S32, 101->U16, 110->U32</orig>
|
|
<definition encodedin="op:size">
|
|
<intro>Is the data type for the elements of the destination, </intro>
|
|
<table class="valuetable">
|
|
<tgroup cols="3">
|
|
<thead>
|
|
<row>
|
|
<entry class="bitfield" bitwidth="1">op</entry>
|
|
<entry class="bitfield" bitwidth="2">size</entry>
|
|
<entry class="symbol"><dt></entry>
|
|
</row>
|
|
</thead>
|
|
<tbody>
|
|
<row>
|
|
<entry class="bitfield">0</entry>
|
|
<entry class="bitfield">01</entry>
|
|
<entry class="symbol">S16</entry>
|
|
</row>
|
|
<row>
|
|
<entry class="bitfield">0</entry>
|
|
<entry class="bitfield">10</entry>
|
|
<entry class="symbol">S32</entry>
|
|
</row>
|
|
<row>
|
|
<entry class="bitfield">1</entry>
|
|
<entry class="bitfield">01</entry>
|
|
<entry class="symbol">U16</entry>
|
|
</row>
|
|
<row>
|
|
<entry class="bitfield">1</entry>
|
|
<entry class="bitfield">10</entry>
|
|
<entry class="symbol">U32</entry>
|
|
</row>
|
|
</tbody>
|
|
</tgroup>
|
|
</table>
|
|
</definition>
|
|
</account>
|
|
<account iclass="simd2reg_misc" symbol="<dt>" iclass_long="Advanced SIMD two registers misc">
|
|
<encodings>
|
|
<encoding encname="VQMOVN_A1" />
|
|
<encoding encname="VQRSHRN_VQMOVN_A1" />
|
|
<encoding encname="VQSHRN_VQMOVN_A1" />
|
|
</encodings>
|
|
<orig>Is the data type for the elements of the operand, encoded in "op<0>:size", where 000->S16, 001->S32, 010->S64, 100->U16, 101->U32, 110->U64, otherwise UNDEFINED.</orig>
|
|
<definition encodedin="op<0>:size">
|
|
<intro>Is the data type for the elements of the operand, </intro>
|
|
<table class="valuetable">
|
|
<tgroup cols="3">
|
|
<thead>
|
|
<row>
|
|
<entry class="bitfield" bitwidth="1">op<0></entry>
|
|
<entry class="bitfield" bitwidth="2">size</entry>
|
|
<entry class="symbol"><dt></entry>
|
|
</row>
|
|
</thead>
|
|
<tbody>
|
|
<row>
|
|
<entry class="bitfield">0</entry>
|
|
<entry class="bitfield">00</entry>
|
|
<entry class="symbol">S16</entry>
|
|
</row>
|
|
<row>
|
|
<entry class="bitfield">0</entry>
|
|
<entry class="bitfield">01</entry>
|
|
<entry class="symbol">S32</entry>
|
|
</row>
|
|
<row>
|
|
<entry class="bitfield">0</entry>
|
|
<entry class="bitfield">10</entry>
|
|
<entry class="symbol">S64</entry>
|
|
</row>
|
|
<row>
|
|
<entry class="bitfield">0</entry>
|
|
<entry class="bitfield">11</entry>
|
|
<entry class="symbol">RESERVED</entry>
|
|
</row>
|
|
<row>
|
|
<entry class="bitfield">1</entry>
|
|
<entry class="bitfield">00</entry>
|
|
<entry class="symbol">U16</entry>
|
|
</row>
|
|
<row>
|
|
<entry class="bitfield">1</entry>
|
|
<entry class="bitfield">01</entry>
|
|
<entry class="symbol">U32</entry>
|
|
</row>
|
|
<row>
|
|
<entry class="bitfield">1</entry>
|
|
<entry class="bitfield">10</entry>
|
|
<entry class="symbol">U64</entry>
|
|
</row>
|
|
<row>
|
|
<entry class="bitfield">1</entry>
|
|
<entry class="bitfield">11</entry>
|
|
<entry class="symbol">RESERVED</entry>
|
|
</row>
|
|
</tbody>
|
|
</tgroup>
|
|
</table>
|
|
</definition>
|
|
</account>
|
|
<account iclass="simd_2r_misc" symbol="<dt>" iclass_long="Advanced SIMD two registers misc">
|
|
<encodings>
|
|
<encoding encname="VQMOVN_T1" />
|
|
<encoding encname="VQRSHRN_VQMOVN_T1" />
|
|
<encoding encname="VQSHRN_VQMOVN_T1" />
|
|
</encodings>
|
|
<orig>Is the data type for the elements of the operand, encoded in "op<0>:size", where 000->S16, 001->S32, 010->S64, 100->U16, 101->U32, 110->U64, otherwise UNDEFINED.</orig>
|
|
<definition encodedin="op<0>:size">
|
|
<intro>Is the data type for the elements of the operand, </intro>
|
|
<table class="valuetable">
|
|
<tgroup cols="3">
|
|
<thead>
|
|
<row>
|
|
<entry class="bitfield" bitwidth="1">op<0></entry>
|
|
<entry class="bitfield" bitwidth="2">size</entry>
|
|
<entry class="symbol"><dt></entry>
|
|
</row>
|
|
</thead>
|
|
<tbody>
|
|
<row>
|
|
<entry class="bitfield">0</entry>
|
|
<entry class="bitfield">00</entry>
|
|
<entry class="symbol">S16</entry>
|
|
</row>
|
|
<row>
|
|
<entry class="bitfield">0</entry>
|
|
<entry class="bitfield">01</entry>
|
|
<entry class="symbol">S32</entry>
|
|
</row>
|
|
<row>
|
|
<entry class="bitfield">0</entry>
|
|
<entry class="bitfield">10</entry>
|
|
<entry class="symbol">S64</entry>
|
|
</row>
|
|
<row>
|
|
<entry class="bitfield">0</entry>
|
|
<entry class="bitfield">11</entry>
|
|
<entry class="symbol">RESERVED</entry>
|
|
</row>
|
|
<row>
|
|
<entry class="bitfield">1</entry>
|
|
<entry class="bitfield">00</entry>
|
|
<entry class="symbol">U16</entry>
|
|
</row>
|
|
<row>
|
|
<entry class="bitfield">1</entry>
|
|
<entry class="bitfield">01</entry>
|
|
<entry class="symbol">U32</entry>
|
|
</row>
|
|
<row>
|
|
<entry class="bitfield">1</entry>
|
|
<entry class="bitfield">10</entry>
|
|
<entry class="symbol">U64</entry>
|
|
</row>
|
|
<row>
|
|
<entry class="bitfield">1</entry>
|
|
<entry class="bitfield">11</entry>
|
|
<entry class="symbol">RESERVED</entry>
|
|
</row>
|
|
</tbody>
|
|
</tgroup>
|
|
</table>
|
|
</definition>
|
|
</account>
|
|
<account iclass="simd2reg_misc" symbol="<dt>" iclass_long="Advanced SIMD two registers misc">
|
|
<encodings>
|
|
<encoding encname="VREV64_A1_D" />
|
|
<encoding encname="VREV64_A1_Q" />
|
|
</encodings>
|
|
<orig>Is the data type for the elements of the operand, encoded in "size" where 00->8, 01->16, 10->32, otherwise UNDEFINED</orig>
|
|
<definition encodedin="size">
|
|
<intro>Is the data type for the elements of the operand, </intro>
|
|
<table class="valuetable">
|
|
<tgroup cols="2">
|
|
<thead>
|
|
<row>
|
|
<entry class="bitfield" bitwidth="2">size</entry>
|
|
<entry class="symbol"><dt></entry>
|
|
</row>
|
|
</thead>
|
|
<tbody>
|
|
<row>
|
|
<entry class="bitfield">00</entry>
|
|
<entry class="symbol">8</entry>
|
|
</row>
|
|
<row>
|
|
<entry class="bitfield">01</entry>
|
|
<entry class="symbol">16</entry>
|
|
</row>
|
|
<row>
|
|
<entry class="bitfield">10</entry>
|
|
<entry class="symbol">32</entry>
|
|
</row>
|
|
<row>
|
|
<entry class="bitfield">11</entry>
|
|
<entry class="symbol">RESERVED</entry>
|
|
</row>
|
|
</tbody>
|
|
</tgroup>
|
|
</table>
|
|
</definition>
|
|
</account>
|
|
<account iclass="simd_2r_misc" symbol="<dt>" iclass_long="Advanced SIMD two registers misc">
|
|
<encodings>
|
|
<encoding encname="VREV64_T1_D" />
|
|
<encoding encname="VREV64_T1_Q" />
|
|
</encodings>
|
|
<orig>Is the data type for the elements of the operand, encoded in "size" where 00->8, 01->16, 10->32, otherwise UNDEFINED</orig>
|
|
<definition encodedin="size">
|
|
<intro>Is the data type for the elements of the operand, </intro>
|
|
<table class="valuetable">
|
|
<tgroup cols="2">
|
|
<thead>
|
|
<row>
|
|
<entry class="bitfield" bitwidth="2">size</entry>
|
|
<entry class="symbol"><dt></entry>
|
|
</row>
|
|
</thead>
|
|
<tbody>
|
|
<row>
|
|
<entry class="bitfield">00</entry>
|
|
<entry class="symbol">8</entry>
|
|
</row>
|
|
<row>
|
|
<entry class="bitfield">01</entry>
|
|
<entry class="symbol">16</entry>
|
|
</row>
|
|
<row>
|
|
<entry class="bitfield">10</entry>
|
|
<entry class="symbol">32</entry>
|
|
</row>
|
|
<row>
|
|
<entry class="bitfield">11</entry>
|
|
<entry class="symbol">RESERVED</entry>
|
|
</row>
|
|
</tbody>
|
|
</tgroup>
|
|
</table>
|
|
</definition>
|
|
</account>
|
|
<account iclass="simd2reg_misc" symbol="<dt>" iclass_long="Advanced SIMD two registers misc">
|
|
<encodings>
|
|
<encoding encname="VREV32_A1_D" />
|
|
<encoding encname="VREV32_A1_Q" />
|
|
</encodings>
|
|
<orig>Is the data type for the elements of the operand, encoded in "size" where 00->8, 01->16, otherwise UNDEFINED</orig>
|
|
<definition encodedin="size">
|
|
<intro>Is the data type for the elements of the operand, </intro>
|
|
<table class="valuetable">
|
|
<tgroup cols="2">
|
|
<thead>
|
|
<row>
|
|
<entry class="bitfield" bitwidth="2">size</entry>
|
|
<entry class="symbol"><dt></entry>
|
|
</row>
|
|
</thead>
|
|
<tbody>
|
|
<row>
|
|
<entry class="bitfield">00</entry>
|
|
<entry class="symbol">8</entry>
|
|
</row>
|
|
<row>
|
|
<entry class="bitfield">01</entry>
|
|
<entry class="symbol">16</entry>
|
|
</row>
|
|
<row>
|
|
<entry class="bitfield">1x</entry>
|
|
<entry class="symbol">RESERVED</entry>
|
|
</row>
|
|
</tbody>
|
|
</tgroup>
|
|
</table>
|
|
</definition>
|
|
</account>
|
|
<account iclass="simd_2r_misc" symbol="<dt>" iclass_long="Advanced SIMD two registers misc">
|
|
<encodings>
|
|
<encoding encname="VREV32_T1_D" />
|
|
<encoding encname="VREV32_T1_Q" />
|
|
</encodings>
|
|
<orig>Is the data type for the elements of the operand, encoded in "size" where 00->8, 01->16, otherwise UNDEFINED</orig>
|
|
<definition encodedin="size">
|
|
<intro>Is the data type for the elements of the operand, </intro>
|
|
<table class="valuetable">
|
|
<tgroup cols="2">
|
|
<thead>
|
|
<row>
|
|
<entry class="bitfield" bitwidth="2">size</entry>
|
|
<entry class="symbol"><dt></entry>
|
|
</row>
|
|
</thead>
|
|
<tbody>
|
|
<row>
|
|
<entry class="bitfield">00</entry>
|
|
<entry class="symbol">8</entry>
|
|
</row>
|
|
<row>
|
|
<entry class="bitfield">01</entry>
|
|
<entry class="symbol">16</entry>
|
|
</row>
|
|
<row>
|
|
<entry class="bitfield">1x</entry>
|
|
<entry class="symbol">RESERVED</entry>
|
|
</row>
|
|
</tbody>
|
|
</tgroup>
|
|
</table>
|
|
</definition>
|
|
</account>
|
|
<account iclass="simd2reg_misc" symbol="<dt>" iclass_long="Advanced SIMD two registers misc">
|
|
<encodings>
|
|
<encoding encname="VREV16_A1_D" />
|
|
<encoding encname="VREV16_A1_Q" />
|
|
</encodings>
|
|
<orig>Is the data type for the elements of the operand, encoded in "size" where 00->8, otherwise UNDEFINED</orig>
|
|
<definition encodedin="size">
|
|
<intro>Is the data type for the elements of the operand, </intro>
|
|
<table class="valuetable">
|
|
<tgroup cols="2">
|
|
<thead>
|
|
<row>
|
|
<entry class="bitfield" bitwidth="2">size</entry>
|
|
<entry class="symbol"><dt></entry>
|
|
</row>
|
|
</thead>
|
|
<tbody>
|
|
<row>
|
|
<entry class="bitfield">00</entry>
|
|
<entry class="symbol">8</entry>
|
|
</row>
|
|
<row>
|
|
<entry class="bitfield">01</entry>
|
|
<entry class="symbol">RESERVED</entry>
|
|
</row>
|
|
<row>
|
|
<entry class="bitfield">1x</entry>
|
|
<entry class="symbol">RESERVED</entry>
|
|
</row>
|
|
</tbody>
|
|
</tgroup>
|
|
</table>
|
|
</definition>
|
|
</account>
|
|
<account iclass="simd_2r_misc" symbol="<dt>" iclass_long="Advanced SIMD two registers misc">
|
|
<encodings>
|
|
<encoding encname="VREV16_T1_D" />
|
|
<encoding encname="VREV16_T1_Q" />
|
|
</encodings>
|
|
<orig>Is the data type for the elements of the operand, encoded in "size" where 00->8, otherwise UNDEFINED</orig>
|
|
<definition encodedin="size">
|
|
<intro>Is the data type for the elements of the operand, </intro>
|
|
<table class="valuetable">
|
|
<tgroup cols="2">
|
|
<thead>
|
|
<row>
|
|
<entry class="bitfield" bitwidth="2">size</entry>
|
|
<entry class="symbol"><dt></entry>
|
|
</row>
|
|
</thead>
|
|
<tbody>
|
|
<row>
|
|
<entry class="bitfield">00</entry>
|
|
<entry class="symbol">8</entry>
|
|
</row>
|
|
<row>
|
|
<entry class="bitfield">01</entry>
|
|
<entry class="symbol">RESERVED</entry>
|
|
</row>
|
|
<row>
|
|
<entry class="bitfield">1x</entry>
|
|
<entry class="symbol">RESERVED</entry>
|
|
</row>
|
|
</tbody>
|
|
</tgroup>
|
|
</table>
|
|
</definition>
|
|
</account>
|
|
<account iclass="simd2reg_misc" symbol="<dt>" iclass_long="Advanced SIMD two registers misc">
|
|
<encodings>
|
|
<encoding encname="VMOVN_A1" />
|
|
<encoding encname="VRSHRN_VMOVN_A1" />
|
|
<encoding encname="VSHRN_VMOVN_A1" />
|
|
</encodings>
|
|
<orig>Is the data type for the elements of the operand, encoded in "size", where 00->I16, 01->I32, 10->I64, otherwise UNDEFINED</orig>
|
|
<definition encodedin="size">
|
|
<intro>Is the data type for the elements of the operand, </intro>
|
|
<table class="valuetable">
|
|
<tgroup cols="2">
|
|
<thead>
|
|
<row>
|
|
<entry class="bitfield" bitwidth="2">size</entry>
|
|
<entry class="symbol"><dt></entry>
|
|
</row>
|
|
</thead>
|
|
<tbody>
|
|
<row>
|
|
<entry class="bitfield">00</entry>
|
|
<entry class="symbol">I16</entry>
|
|
</row>
|
|
<row>
|
|
<entry class="bitfield">01</entry>
|
|
<entry class="symbol">I32</entry>
|
|
</row>
|
|
<row>
|
|
<entry class="bitfield">10</entry>
|
|
<entry class="symbol">I64</entry>
|
|
</row>
|
|
<row>
|
|
<entry class="bitfield">11</entry>
|
|
<entry class="symbol">RESERVED</entry>
|
|
</row>
|
|
</tbody>
|
|
</tgroup>
|
|
</table>
|
|
</definition>
|
|
</account>
|
|
<account iclass="simd_2r_misc" symbol="<dt>" iclass_long="Advanced SIMD two registers misc">
|
|
<encodings>
|
|
<encoding encname="VMOVN_T1" />
|
|
<encoding encname="VRSHRN_VMOVN_T1" />
|
|
<encoding encname="VSHRN_VMOVN_T1" />
|
|
</encodings>
|
|
<orig>Is the data type for the elements of the operand, encoded in "size", where 00->I16, 01->I32, 10->I64, otherwise UNDEFINED</orig>
|
|
<definition encodedin="size">
|
|
<intro>Is the data type for the elements of the operand, </intro>
|
|
<table class="valuetable">
|
|
<tgroup cols="2">
|
|
<thead>
|
|
<row>
|
|
<entry class="bitfield" bitwidth="2">size</entry>
|
|
<entry class="symbol"><dt></entry>
|
|
</row>
|
|
</thead>
|
|
<tbody>
|
|
<row>
|
|
<entry class="bitfield">00</entry>
|
|
<entry class="symbol">I16</entry>
|
|
</row>
|
|
<row>
|
|
<entry class="bitfield">01</entry>
|
|
<entry class="symbol">I32</entry>
|
|
</row>
|
|
<row>
|
|
<entry class="bitfield">10</entry>
|
|
<entry class="symbol">I64</entry>
|
|
</row>
|
|
<row>
|
|
<entry class="bitfield">11</entry>
|
|
<entry class="symbol">RESERVED</entry>
|
|
</row>
|
|
</tbody>
|
|
</tgroup>
|
|
</table>
|
|
</definition>
|
|
</account>
|
|
<account iclass="simd2reg_misc" symbol="<dt>" iclass_long="Advanced SIMD two registers misc">
|
|
<encodings>
|
|
<encoding encname="VQMOVUN_A1" />
|
|
<encoding encname="VQRSHRUN_VQMOVUN_A1" />
|
|
<encoding encname="VQSHRUN_VQMOVUN_A1" />
|
|
</encodings>
|
|
<orig>Is the data type for the elements of the operand, encoded in "size", where 00->S16, 01->S32, 10->S64, otherwise UNDEFINED.</orig>
|
|
<definition encodedin="size">
|
|
<intro>Is the data type for the elements of the operand, </intro>
|
|
<table class="valuetable">
|
|
<tgroup cols="2">
|
|
<thead>
|
|
<row>
|
|
<entry class="bitfield" bitwidth="2">size</entry>
|
|
<entry class="symbol"><dt></entry>
|
|
</row>
|
|
</thead>
|
|
<tbody>
|
|
<row>
|
|
<entry class="bitfield">00</entry>
|
|
<entry class="symbol">S16</entry>
|
|
</row>
|
|
<row>
|
|
<entry class="bitfield">01</entry>
|
|
<entry class="symbol">S32</entry>
|
|
</row>
|
|
<row>
|
|
<entry class="bitfield">10</entry>
|
|
<entry class="symbol">S64</entry>
|
|
</row>
|
|
<row>
|
|
<entry class="bitfield">11</entry>
|
|
<entry class="symbol">RESERVED</entry>
|
|
</row>
|
|
</tbody>
|
|
</tgroup>
|
|
</table>
|
|
</definition>
|
|
</account>
|
|
<account iclass="simd_2r_misc" symbol="<dt>" iclass_long="Advanced SIMD two registers misc">
|
|
<encodings>
|
|
<encoding encname="VQMOVUN_T1" />
|
|
<encoding encname="VQRSHRUN_VQMOVUN_T1" />
|
|
<encoding encname="VQSHRUN_VQMOVUN_T1" />
|
|
</encodings>
|
|
<orig>Is the data type for the elements of the operand, encoded in "size", where 00->S16, 01->S32, 10->S64, otherwise UNDEFINED.</orig>
|
|
<definition encodedin="size">
|
|
<intro>Is the data type for the elements of the operand, </intro>
|
|
<table class="valuetable">
|
|
<tgroup cols="2">
|
|
<thead>
|
|
<row>
|
|
<entry class="bitfield" bitwidth="2">size</entry>
|
|
<entry class="symbol"><dt></entry>
|
|
</row>
|
|
</thead>
|
|
<tbody>
|
|
<row>
|
|
<entry class="bitfield">00</entry>
|
|
<entry class="symbol">S16</entry>
|
|
</row>
|
|
<row>
|
|
<entry class="bitfield">01</entry>
|
|
<entry class="symbol">S32</entry>
|
|
</row>
|
|
<row>
|
|
<entry class="bitfield">10</entry>
|
|
<entry class="symbol">S64</entry>
|
|
</row>
|
|
<row>
|
|
<entry class="bitfield">11</entry>
|
|
<entry class="symbol">RESERVED</entry>
|
|
</row>
|
|
</tbody>
|
|
</tgroup>
|
|
</table>
|
|
</definition>
|
|
</account>
|
|
<account iclass="simd2reg_misc" symbol="<dt>" iclass_long="Advanced SIMD two registers misc">
|
|
<encodings>
|
|
<encoding encname="VCEQ_i_A1_D" />
|
|
<encoding encname="VCEQ_i_A1_Q" />
|
|
</encodings>
|
|
<orig>Is the data type for the elements of the operands, encoded in "F:size", where 000->I8, 001->I16, 010->I32, 101->F16, 110->F32</orig>
|
|
<definition encodedin="F:size">
|
|
<intro>Is the data type for the elements of the operands, </intro>
|
|
<table class="valuetable">
|
|
<tgroup cols="3">
|
|
<thead>
|
|
<row>
|
|
<entry class="bitfield" bitwidth="1">F</entry>
|
|
<entry class="bitfield" bitwidth="2">size</entry>
|
|
<entry class="symbol"><dt></entry>
|
|
</row>
|
|
</thead>
|
|
<tbody>
|
|
<row>
|
|
<entry class="bitfield">0</entry>
|
|
<entry class="bitfield">00</entry>
|
|
<entry class="symbol">I8</entry>
|
|
</row>
|
|
<row>
|
|
<entry class="bitfield">0</entry>
|
|
<entry class="bitfield">01</entry>
|
|
<entry class="symbol">I16</entry>
|
|
</row>
|
|
<row>
|
|
<entry class="bitfield">0</entry>
|
|
<entry class="bitfield">10</entry>
|
|
<entry class="symbol">I32</entry>
|
|
</row>
|
|
<row>
|
|
<entry class="bitfield">1</entry>
|
|
<entry class="bitfield">01</entry>
|
|
<entry class="symbol">F16</entry>
|
|
</row>
|
|
<row>
|
|
<entry class="bitfield">1</entry>
|
|
<entry class="bitfield">10</entry>
|
|
<entry class="symbol">F32</entry>
|
|
</row>
|
|
</tbody>
|
|
</tgroup>
|
|
</table>
|
|
</definition>
|
|
</account>
|
|
<account iclass="simd_2r_misc" symbol="<dt>" iclass_long="Advanced SIMD two registers misc">
|
|
<encodings>
|
|
<encoding encname="VCEQ_i_T1_D" />
|
|
<encoding encname="VCEQ_i_T1_Q" />
|
|
</encodings>
|
|
<orig>Is the data type for the elements of the operands, encoded in "F:size", where 000->I8, 001->I16, 010->I32, 101->F16, 110->F32</orig>
|
|
<definition encodedin="F:size">
|
|
<intro>Is the data type for the elements of the operands, </intro>
|
|
<table class="valuetable">
|
|
<tgroup cols="3">
|
|
<thead>
|
|
<row>
|
|
<entry class="bitfield" bitwidth="1">F</entry>
|
|
<entry class="bitfield" bitwidth="2">size</entry>
|
|
<entry class="symbol"><dt></entry>
|
|
</row>
|
|
</thead>
|
|
<tbody>
|
|
<row>
|
|
<entry class="bitfield">0</entry>
|
|
<entry class="bitfield">00</entry>
|
|
<entry class="symbol">I8</entry>
|
|
</row>
|
|
<row>
|
|
<entry class="bitfield">0</entry>
|
|
<entry class="bitfield">01</entry>
|
|
<entry class="symbol">I16</entry>
|
|
</row>
|
|
<row>
|
|
<entry class="bitfield">0</entry>
|
|
<entry class="bitfield">10</entry>
|
|
<entry class="symbol">I32</entry>
|
|
</row>
|
|
<row>
|
|
<entry class="bitfield">1</entry>
|
|
<entry class="bitfield">01</entry>
|
|
<entry class="symbol">F16</entry>
|
|
</row>
|
|
<row>
|
|
<entry class="bitfield">1</entry>
|
|
<entry class="bitfield">10</entry>
|
|
<entry class="symbol">F32</entry>
|
|
</row>
|
|
</tbody>
|
|
</tgroup>
|
|
</table>
|
|
</definition>
|
|
</account>
|
|
<account iclass="simd2reg_misc" symbol="<dt>" iclass_long="Advanced SIMD two registers misc">
|
|
<encodings>
|
|
<encoding encname="VCGE_i_A1_D" />
|
|
<encoding encname="VCGE_i_A1_Q" />
|
|
<encoding encname="VCGT_i_A1_D" />
|
|
<encoding encname="VCGT_i_A1_Q" />
|
|
<encoding encname="VCLE_i_A1_D" />
|
|
<encoding encname="VCLE_i_A1_Q" />
|
|
<encoding encname="VCLT_i_A1_D" />
|
|
<encoding encname="VCLT_i_A1_Q" />
|
|
</encodings>
|
|
<orig>Is the data type for the elements of the operands, encoded in "F:size", where 000->S8, 001->S16, 010->S32, 101->F16, 110->F32</orig>
|
|
<definition encodedin="F:size">
|
|
<intro>Is the data type for the elements of the operands, </intro>
|
|
<table class="valuetable">
|
|
<tgroup cols="3">
|
|
<thead>
|
|
<row>
|
|
<entry class="bitfield" bitwidth="1">F</entry>
|
|
<entry class="bitfield" bitwidth="2">size</entry>
|
|
<entry class="symbol"><dt></entry>
|
|
</row>
|
|
</thead>
|
|
<tbody>
|
|
<row>
|
|
<entry class="bitfield">0</entry>
|
|
<entry class="bitfield">00</entry>
|
|
<entry class="symbol">S8</entry>
|
|
</row>
|
|
<row>
|
|
<entry class="bitfield">0</entry>
|
|
<entry class="bitfield">01</entry>
|
|
<entry class="symbol">S16</entry>
|
|
</row>
|
|
<row>
|
|
<entry class="bitfield">0</entry>
|
|
<entry class="bitfield">10</entry>
|
|
<entry class="symbol">S32</entry>
|
|
</row>
|
|
<row>
|
|
<entry class="bitfield">1</entry>
|
|
<entry class="bitfield">01</entry>
|
|
<entry class="symbol">F16</entry>
|
|
</row>
|
|
<row>
|
|
<entry class="bitfield">1</entry>
|
|
<entry class="bitfield">10</entry>
|
|
<entry class="symbol">F32</entry>
|
|
</row>
|
|
</tbody>
|
|
</tgroup>
|
|
</table>
|
|
</definition>
|
|
</account>
|
|
<account iclass="simd_2r_misc" symbol="<dt>" iclass_long="Advanced SIMD two registers misc">
|
|
<encodings>
|
|
<encoding encname="VCGE_i_T1_D" />
|
|
<encoding encname="VCGE_i_T1_Q" />
|
|
<encoding encname="VCGT_i_T1_D" />
|
|
<encoding encname="VCGT_i_T1_Q" />
|
|
<encoding encname="VCLE_i_T1_D" />
|
|
<encoding encname="VCLE_i_T1_Q" />
|
|
<encoding encname="VCLT_i_T1_D" />
|
|
<encoding encname="VCLT_i_T1_Q" />
|
|
</encodings>
|
|
<orig>Is the data type for the elements of the operands, encoded in "F:size", where 000->S8, 001->S16, 010->S32, 101->F16, 110->F32</orig>
|
|
<definition encodedin="F:size">
|
|
<intro>Is the data type for the elements of the operands, </intro>
|
|
<table class="valuetable">
|
|
<tgroup cols="3">
|
|
<thead>
|
|
<row>
|
|
<entry class="bitfield" bitwidth="1">F</entry>
|
|
<entry class="bitfield" bitwidth="2">size</entry>
|
|
<entry class="symbol"><dt></entry>
|
|
</row>
|
|
</thead>
|
|
<tbody>
|
|
<row>
|
|
<entry class="bitfield">0</entry>
|
|
<entry class="bitfield">00</entry>
|
|
<entry class="symbol">S8</entry>
|
|
</row>
|
|
<row>
|
|
<entry class="bitfield">0</entry>
|
|
<entry class="bitfield">01</entry>
|
|
<entry class="symbol">S16</entry>
|
|
</row>
|
|
<row>
|
|
<entry class="bitfield">0</entry>
|
|
<entry class="bitfield">10</entry>
|
|
<entry class="symbol">S32</entry>
|
|
</row>
|
|
<row>
|
|
<entry class="bitfield">1</entry>
|
|
<entry class="bitfield">01</entry>
|
|
<entry class="symbol">F16</entry>
|
|
</row>
|
|
<row>
|
|
<entry class="bitfield">1</entry>
|
|
<entry class="bitfield">10</entry>
|
|
<entry class="symbol">F32</entry>
|
|
</row>
|
|
</tbody>
|
|
</tgroup>
|
|
</table>
|
|
</definition>
|
|
</account>
|
|
<account iclass="simd2reg_misc" symbol="<dt>" iclass_long="Advanced SIMD two registers misc">
|
|
<encodings>
|
|
<encoding encname="VCLZ_A1_D" />
|
|
<encoding encname="VCLZ_A1_Q" />
|
|
</encodings>
|
|
<orig>Is the data type for the elements of the operands, encoded in "size", where 00->I8, 01->I16, 10->I32, otherwise UNDEFINED</orig>
|
|
<definition encodedin="size">
|
|
<intro>Is the data type for the elements of the operands, </intro>
|
|
<table class="valuetable">
|
|
<tgroup cols="2">
|
|
<thead>
|
|
<row>
|
|
<entry class="bitfield" bitwidth="2">size</entry>
|
|
<entry class="symbol"><dt></entry>
|
|
</row>
|
|
</thead>
|
|
<tbody>
|
|
<row>
|
|
<entry class="bitfield">00</entry>
|
|
<entry class="symbol">I8</entry>
|
|
</row>
|
|
<row>
|
|
<entry class="bitfield">01</entry>
|
|
<entry class="symbol">I16</entry>
|
|
</row>
|
|
<row>
|
|
<entry class="bitfield">10</entry>
|
|
<entry class="symbol">I32</entry>
|
|
</row>
|
|
<row>
|
|
<entry class="bitfield">11</entry>
|
|
<entry class="symbol">RESERVED</entry>
|
|
</row>
|
|
</tbody>
|
|
</tgroup>
|
|
</table>
|
|
</definition>
|
|
</account>
|
|
<account iclass="simd_2r_misc" symbol="<dt>" iclass_long="Advanced SIMD two registers misc">
|
|
<encodings>
|
|
<encoding encname="VCLZ_T1_D" />
|
|
<encoding encname="VCLZ_T1_Q" />
|
|
</encodings>
|
|
<orig>Is the data type for the elements of the operands, encoded in "size", where 00->I8, 01->I16, 10->I32, otherwise UNDEFINED</orig>
|
|
<definition encodedin="size">
|
|
<intro>Is the data type for the elements of the operands, </intro>
|
|
<table class="valuetable">
|
|
<tgroup cols="2">
|
|
<thead>
|
|
<row>
|
|
<entry class="bitfield" bitwidth="2">size</entry>
|
|
<entry class="symbol"><dt></entry>
|
|
</row>
|
|
</thead>
|
|
<tbody>
|
|
<row>
|
|
<entry class="bitfield">00</entry>
|
|
<entry class="symbol">I8</entry>
|
|
</row>
|
|
<row>
|
|
<entry class="bitfield">01</entry>
|
|
<entry class="symbol">I16</entry>
|
|
</row>
|
|
<row>
|
|
<entry class="bitfield">10</entry>
|
|
<entry class="symbol">I32</entry>
|
|
</row>
|
|
<row>
|
|
<entry class="bitfield">11</entry>
|
|
<entry class="symbol">RESERVED</entry>
|
|
</row>
|
|
</tbody>
|
|
</tgroup>
|
|
</table>
|
|
</definition>
|
|
</account>
|
|
<account iclass="simd2reg_misc" symbol="<dt>" iclass_long="Advanced SIMD two registers misc">
|
|
<encodings>
|
|
<encoding encname="VCLS_A1_D" />
|
|
<encoding encname="VCLS_A1_Q" />
|
|
</encodings>
|
|
<orig>Is the data type for the elements of the operands, encoded in "size", where 00->S8, 01->S16, 10->S32, otherwise UNDEFINED</orig>
|
|
<definition encodedin="size">
|
|
<intro>Is the data type for the elements of the operands, </intro>
|
|
<table class="valuetable">
|
|
<tgroup cols="2">
|
|
<thead>
|
|
<row>
|
|
<entry class="bitfield" bitwidth="2">size</entry>
|
|
<entry class="symbol"><dt></entry>
|
|
</row>
|
|
</thead>
|
|
<tbody>
|
|
<row>
|
|
<entry class="bitfield">00</entry>
|
|
<entry class="symbol">S8</entry>
|
|
</row>
|
|
<row>
|
|
<entry class="bitfield">01</entry>
|
|
<entry class="symbol">S16</entry>
|
|
</row>
|
|
<row>
|
|
<entry class="bitfield">10</entry>
|
|
<entry class="symbol">S32</entry>
|
|
</row>
|
|
<row>
|
|
<entry class="bitfield">11</entry>
|
|
<entry class="symbol">RESERVED</entry>
|
|
</row>
|
|
</tbody>
|
|
</tgroup>
|
|
</table>
|
|
</definition>
|
|
</account>
|
|
<account iclass="simd_2r_misc" symbol="<dt>" iclass_long="Advanced SIMD two registers misc">
|
|
<encodings>
|
|
<encoding encname="VCLS_T1_D" />
|
|
<encoding encname="VCLS_T1_Q" />
|
|
</encodings>
|
|
<orig>Is the data type for the elements of the operands, encoded in "size", where 00->S8, 01->S16, 10->S32, otherwise UNDEFINED</orig>
|
|
<definition encodedin="size">
|
|
<intro>Is the data type for the elements of the operands, </intro>
|
|
<table class="valuetable">
|
|
<tgroup cols="2">
|
|
<thead>
|
|
<row>
|
|
<entry class="bitfield" bitwidth="2">size</entry>
|
|
<entry class="symbol"><dt></entry>
|
|
</row>
|
|
</thead>
|
|
<tbody>
|
|
<row>
|
|
<entry class="bitfield">00</entry>
|
|
<entry class="symbol">S8</entry>
|
|
</row>
|
|
<row>
|
|
<entry class="bitfield">01</entry>
|
|
<entry class="symbol">S16</entry>
|
|
</row>
|
|
<row>
|
|
<entry class="bitfield">10</entry>
|
|
<entry class="symbol">S32</entry>
|
|
</row>
|
|
<row>
|
|
<entry class="bitfield">11</entry>
|
|
<entry class="symbol">RESERVED</entry>
|
|
</row>
|
|
</tbody>
|
|
</tgroup>
|
|
</table>
|
|
</definition>
|
|
</account>
|
|
<account iclass="simd2reg_misc" symbol="<dt2>" iclass_long="Advanced SIMD two registers misc">
|
|
<encodings>
|
|
<encoding encname="VCVTA_asimd_A1_D" />
|
|
<encoding encname="VCVTA_asimd_A1_Q" />
|
|
<encoding encname="VCVTM_asimd_A1_D" />
|
|
<encoding encname="VCVTM_asimd_A1_Q" />
|
|
<encoding encname="VCVTN_asimd_A1_D" />
|
|
<encoding encname="VCVTN_asimd_A1_Q" />
|
|
<encoding encname="VCVTP_asimd_A1_D" />
|
|
<encoding encname="VCVTP_asimd_A1_Q" />
|
|
</encodings>
|
|
<orig>Is the data type for the elements of the source vector, encoded in "size" where 01->F16, 10->F32</orig>
|
|
<definition encodedin="size">
|
|
<intro>Is the data type for the elements of the source vector, </intro>
|
|
<table class="valuetable">
|
|
<tgroup cols="2">
|
|
<thead>
|
|
<row>
|
|
<entry class="bitfield" bitwidth="2">size</entry>
|
|
<entry class="symbol"><dt2></entry>
|
|
</row>
|
|
</thead>
|
|
<tbody>
|
|
<row>
|
|
<entry class="bitfield">01</entry>
|
|
<entry class="symbol">F16</entry>
|
|
</row>
|
|
<row>
|
|
<entry class="bitfield">10</entry>
|
|
<entry class="symbol">F32</entry>
|
|
</row>
|
|
</tbody>
|
|
</tgroup>
|
|
</table>
|
|
</definition>
|
|
</account>
|
|
<account iclass="simd_2r_misc" symbol="<dt2>" iclass_long="Advanced SIMD two registers misc">
|
|
<encodings>
|
|
<encoding encname="VCVTA_asimd_T1_D" />
|
|
<encoding encname="VCVTA_asimd_T1_Q" />
|
|
<encoding encname="VCVTM_asimd_T1_D" />
|
|
<encoding encname="VCVTM_asimd_T1_Q" />
|
|
<encoding encname="VCVTN_asimd_T1_D" />
|
|
<encoding encname="VCVTN_asimd_T1_Q" />
|
|
<encoding encname="VCVTP_asimd_T1_D" />
|
|
<encoding encname="VCVTP_asimd_T1_Q" />
|
|
</encodings>
|
|
<orig>Is the data type for the elements of the source vector, encoded in "size" where 01->F16, 10->F32</orig>
|
|
<definition encodedin="size">
|
|
<intro>Is the data type for the elements of the source vector, </intro>
|
|
<table class="valuetable">
|
|
<tgroup cols="2">
|
|
<thead>
|
|
<row>
|
|
<entry class="bitfield" bitwidth="2">size</entry>
|
|
<entry class="symbol"><dt2></entry>
|
|
</row>
|
|
</thead>
|
|
<tbody>
|
|
<row>
|
|
<entry class="bitfield">01</entry>
|
|
<entry class="symbol">F16</entry>
|
|
</row>
|
|
<row>
|
|
<entry class="bitfield">10</entry>
|
|
<entry class="symbol">F32</entry>
|
|
</row>
|
|
</tbody>
|
|
</tgroup>
|
|
</table>
|
|
</definition>
|
|
</account>
|
|
<account iclass="simd2reg_misc" symbol="<dt2>" iclass_long="Advanced SIMD two registers misc">
|
|
<encodings>
|
|
<encoding encname="VCVT_is_A1_D" />
|
|
<encoding encname="VCVT_is_A1_Q" />
|
|
</encodings>
|
|
<orig>Is the data type for the elements of the source vector, encoded in "size:op" where 0100->S16, 0101->U16, 011x->F16, 1000->S32, 1001->U32, 101x->F32</orig>
|
|
<definition encodedin="size:op">
|
|
<intro>Is the data type for the elements of the source vector, </intro>
|
|
<table class="valuetable">
|
|
<tgroup cols="3">
|
|
<thead>
|
|
<row>
|
|
<entry class="bitfield" bitwidth="2">size</entry>
|
|
<entry class="bitfield" bitwidth="2">op</entry>
|
|
<entry class="symbol"><dt2></entry>
|
|
</row>
|
|
</thead>
|
|
<tbody>
|
|
<row>
|
|
<entry class="bitfield">01</entry>
|
|
<entry class="bitfield">00</entry>
|
|
<entry class="symbol">S16</entry>
|
|
</row>
|
|
<row>
|
|
<entry class="bitfield">01</entry>
|
|
<entry class="bitfield">01</entry>
|
|
<entry class="symbol">U16</entry>
|
|
</row>
|
|
<row>
|
|
<entry class="bitfield">01</entry>
|
|
<entry class="bitfield">1x</entry>
|
|
<entry class="symbol">F16</entry>
|
|
</row>
|
|
<row>
|
|
<entry class="bitfield">10</entry>
|
|
<entry class="bitfield">00</entry>
|
|
<entry class="symbol">S32</entry>
|
|
</row>
|
|
<row>
|
|
<entry class="bitfield">10</entry>
|
|
<entry class="bitfield">01</entry>
|
|
<entry class="symbol">U32</entry>
|
|
</row>
|
|
<row>
|
|
<entry class="bitfield">10</entry>
|
|
<entry class="bitfield">1x</entry>
|
|
<entry class="symbol">F32</entry>
|
|
</row>
|
|
</tbody>
|
|
</tgroup>
|
|
</table>
|
|
</definition>
|
|
</account>
|
|
<account iclass="simd_2r_misc" symbol="<dt2>" iclass_long="Advanced SIMD two registers misc">
|
|
<encodings>
|
|
<encoding encname="VCVT_is_T1_D" />
|
|
<encoding encname="VCVT_is_T1_Q" />
|
|
</encodings>
|
|
<orig>Is the data type for the elements of the source vector, encoded in "size:op" where 0100->S16, 0101->U16, 011x->F16, 1000->S32, 1001->U32, 101x->F32</orig>
|
|
<definition encodedin="size:op">
|
|
<intro>Is the data type for the elements of the source vector, </intro>
|
|
<table class="valuetable">
|
|
<tgroup cols="3">
|
|
<thead>
|
|
<row>
|
|
<entry class="bitfield" bitwidth="2">size</entry>
|
|
<entry class="bitfield" bitwidth="2">op</entry>
|
|
<entry class="symbol"><dt2></entry>
|
|
</row>
|
|
</thead>
|
|
<tbody>
|
|
<row>
|
|
<entry class="bitfield">01</entry>
|
|
<entry class="bitfield">00</entry>
|
|
<entry class="symbol">S16</entry>
|
|
</row>
|
|
<row>
|
|
<entry class="bitfield">01</entry>
|
|
<entry class="bitfield">01</entry>
|
|
<entry class="symbol">U16</entry>
|
|
</row>
|
|
<row>
|
|
<entry class="bitfield">01</entry>
|
|
<entry class="bitfield">1x</entry>
|
|
<entry class="symbol">F16</entry>
|
|
</row>
|
|
<row>
|
|
<entry class="bitfield">10</entry>
|
|
<entry class="bitfield">00</entry>
|
|
<entry class="symbol">S32</entry>
|
|
</row>
|
|
<row>
|
|
<entry class="bitfield">10</entry>
|
|
<entry class="bitfield">01</entry>
|
|
<entry class="symbol">U32</entry>
|
|
</row>
|
|
<row>
|
|
<entry class="bitfield">10</entry>
|
|
<entry class="bitfield">1x</entry>
|
|
<entry class="symbol">F32</entry>
|
|
</row>
|
|
</tbody>
|
|
</tgroup>
|
|
</table>
|
|
</definition>
|
|
</account>
|
|
<account iclass="simd2reg_misc" symbol="<dt>" iclass_long="Advanced SIMD two registers misc">
|
|
<encodings>
|
|
<encoding encname="VABS_A1_D" />
|
|
<encoding encname="VABS_A1_Q" />
|
|
<encoding encname="VNEG_A1_D" />
|
|
<encoding encname="VNEG_A1_Q" />
|
|
</encodings>
|
|
<orig>Is the data type for the elements of the vectors, encoded in "F:size", where 000->S8, 001->S16, 010->S32, 101->F16, 110->F32.</orig>
|
|
<definition encodedin="F:size">
|
|
<intro>Is the data type for the elements of the vectors, </intro>
|
|
<table class="valuetable">
|
|
<tgroup cols="3">
|
|
<thead>
|
|
<row>
|
|
<entry class="bitfield" bitwidth="1">F</entry>
|
|
<entry class="bitfield" bitwidth="2">size</entry>
|
|
<entry class="symbol"><dt></entry>
|
|
</row>
|
|
</thead>
|
|
<tbody>
|
|
<row>
|
|
<entry class="bitfield">0</entry>
|
|
<entry class="bitfield">00</entry>
|
|
<entry class="symbol">S8</entry>
|
|
</row>
|
|
<row>
|
|
<entry class="bitfield">0</entry>
|
|
<entry class="bitfield">01</entry>
|
|
<entry class="symbol">S16</entry>
|
|
</row>
|
|
<row>
|
|
<entry class="bitfield">0</entry>
|
|
<entry class="bitfield">10</entry>
|
|
<entry class="symbol">S32</entry>
|
|
</row>
|
|
<row>
|
|
<entry class="bitfield">1</entry>
|
|
<entry class="bitfield">01</entry>
|
|
<entry class="symbol">F16</entry>
|
|
</row>
|
|
<row>
|
|
<entry class="bitfield">1</entry>
|
|
<entry class="bitfield">10</entry>
|
|
<entry class="symbol">F32</entry>
|
|
</row>
|
|
</tbody>
|
|
</tgroup>
|
|
</table>
|
|
</definition>
|
|
</account>
|
|
<account iclass="simd_2r_misc" symbol="<dt>" iclass_long="Advanced SIMD two registers misc">
|
|
<encodings>
|
|
<encoding encname="VABS_T1_D" />
|
|
<encoding encname="VABS_T1_Q" />
|
|
<encoding encname="VNEG_T1_D" />
|
|
<encoding encname="VNEG_T1_Q" />
|
|
</encodings>
|
|
<orig>Is the data type for the elements of the vectors, encoded in "F:size", where 000->S8, 001->S16, 010->S32, 101->F16, 110->F32.</orig>
|
|
<definition encodedin="F:size">
|
|
<intro>Is the data type for the elements of the vectors, </intro>
|
|
<table class="valuetable">
|
|
<tgroup cols="3">
|
|
<thead>
|
|
<row>
|
|
<entry class="bitfield" bitwidth="1">F</entry>
|
|
<entry class="bitfield" bitwidth="2">size</entry>
|
|
<entry class="symbol"><dt></entry>
|
|
</row>
|
|
</thead>
|
|
<tbody>
|
|
<row>
|
|
<entry class="bitfield">0</entry>
|
|
<entry class="bitfield">00</entry>
|
|
<entry class="symbol">S8</entry>
|
|
</row>
|
|
<row>
|
|
<entry class="bitfield">0</entry>
|
|
<entry class="bitfield">01</entry>
|
|
<entry class="symbol">S16</entry>
|
|
</row>
|
|
<row>
|
|
<entry class="bitfield">0</entry>
|
|
<entry class="bitfield">10</entry>
|
|
<entry class="symbol">S32</entry>
|
|
</row>
|
|
<row>
|
|
<entry class="bitfield">1</entry>
|
|
<entry class="bitfield">01</entry>
|
|
<entry class="symbol">F16</entry>
|
|
</row>
|
|
<row>
|
|
<entry class="bitfield">1</entry>
|
|
<entry class="bitfield">10</entry>
|
|
<entry class="symbol">F32</entry>
|
|
</row>
|
|
</tbody>
|
|
</tgroup>
|
|
</table>
|
|
</definition>
|
|
</account>
|
|
<account iclass="simd2reg_misc" symbol="<dt>" iclass_long="Advanced SIMD two registers misc">
|
|
<encodings>
|
|
<encoding encname="VRECPE_A1_D" />
|
|
<encoding encname="VRECPE_A1_Q" />
|
|
<encoding encname="VRSQRTE_A1_D" />
|
|
<encoding encname="VRSQRTE_A1_Q" />
|
|
</encodings>
|
|
<orig>Is the data type for the elements of the vectors, encoded in "F:size", where 010->U32, 101->F16, 110->F32</orig>
|
|
<definition encodedin="F:size">
|
|
<intro>Is the data type for the elements of the vectors, </intro>
|
|
<table class="valuetable">
|
|
<tgroup cols="3">
|
|
<thead>
|
|
<row>
|
|
<entry class="bitfield" bitwidth="1">F</entry>
|
|
<entry class="bitfield" bitwidth="2">size</entry>
|
|
<entry class="symbol"><dt></entry>
|
|
</row>
|
|
</thead>
|
|
<tbody>
|
|
<row>
|
|
<entry class="bitfield">0</entry>
|
|
<entry class="bitfield">10</entry>
|
|
<entry class="symbol">U32</entry>
|
|
</row>
|
|
<row>
|
|
<entry class="bitfield">1</entry>
|
|
<entry class="bitfield">01</entry>
|
|
<entry class="symbol">F16</entry>
|
|
</row>
|
|
<row>
|
|
<entry class="bitfield">1</entry>
|
|
<entry class="bitfield">10</entry>
|
|
<entry class="symbol">F32</entry>
|
|
</row>
|
|
</tbody>
|
|
</tgroup>
|
|
</table>
|
|
</definition>
|
|
</account>
|
|
<account iclass="simd_2r_misc" symbol="<dt>" iclass_long="Advanced SIMD two registers misc">
|
|
<encodings>
|
|
<encoding encname="VRECPE_T1_D" />
|
|
<encoding encname="VRECPE_T1_Q" />
|
|
<encoding encname="VRSQRTE_T1_D" />
|
|
<encoding encname="VRSQRTE_T1_Q" />
|
|
</encodings>
|
|
<orig>Is the data type for the elements of the vectors, encoded in "F:size", where 010->U32, 101->F16, 110->F32</orig>
|
|
<definition encodedin="F:size">
|
|
<intro>Is the data type for the elements of the vectors, </intro>
|
|
<table class="valuetable">
|
|
<tgroup cols="3">
|
|
<thead>
|
|
<row>
|
|
<entry class="bitfield" bitwidth="1">F</entry>
|
|
<entry class="bitfield" bitwidth="2">size</entry>
|
|
<entry class="symbol"><dt></entry>
|
|
</row>
|
|
</thead>
|
|
<tbody>
|
|
<row>
|
|
<entry class="bitfield">0</entry>
|
|
<entry class="bitfield">10</entry>
|
|
<entry class="symbol">U32</entry>
|
|
</row>
|
|
<row>
|
|
<entry class="bitfield">1</entry>
|
|
<entry class="bitfield">01</entry>
|
|
<entry class="symbol">F16</entry>
|
|
</row>
|
|
<row>
|
|
<entry class="bitfield">1</entry>
|
|
<entry class="bitfield">10</entry>
|
|
<entry class="symbol">F32</entry>
|
|
</row>
|
|
</tbody>
|
|
</tgroup>
|
|
</table>
|
|
</definition>
|
|
</account>
|
|
<account iclass="simd2reg_misc" symbol="<dt>" iclass_long="Advanced SIMD two registers misc">
|
|
<encodings>
|
|
<encoding encname="VPADAL_A1_D" />
|
|
<encoding encname="VPADAL_A1_Q" />
|
|
<encoding encname="VPADDL_A1_D" />
|
|
<encoding encname="VPADDL_A1_Q" />
|
|
</encodings>
|
|
<orig>Is the data type for the elements of the vectors, encoded in "op:size", where 000->S8, 001->S16, 010->S32, 100->U8, 101->U16, 110->U32, otherwise UNDEFINED</orig>
|
|
<definition encodedin="op:size">
|
|
<intro>Is the data type for the elements of the vectors, </intro>
|
|
<table class="valuetable">
|
|
<tgroup cols="3">
|
|
<thead>
|
|
<row>
|
|
<entry class="bitfield" bitwidth="1">op</entry>
|
|
<entry class="bitfield" bitwidth="2">size</entry>
|
|
<entry class="symbol"><dt></entry>
|
|
</row>
|
|
</thead>
|
|
<tbody>
|
|
<row>
|
|
<entry class="bitfield">0</entry>
|
|
<entry class="bitfield">00</entry>
|
|
<entry class="symbol">S8</entry>
|
|
</row>
|
|
<row>
|
|
<entry class="bitfield">0</entry>
|
|
<entry class="bitfield">01</entry>
|
|
<entry class="symbol">S16</entry>
|
|
</row>
|
|
<row>
|
|
<entry class="bitfield">0</entry>
|
|
<entry class="bitfield">10</entry>
|
|
<entry class="symbol">S32</entry>
|
|
</row>
|
|
<row>
|
|
<entry class="bitfield">0</entry>
|
|
<entry class="bitfield">11</entry>
|
|
<entry class="symbol">RESERVED</entry>
|
|
</row>
|
|
<row>
|
|
<entry class="bitfield">1</entry>
|
|
<entry class="bitfield">00</entry>
|
|
<entry class="symbol">U8</entry>
|
|
</row>
|
|
<row>
|
|
<entry class="bitfield">1</entry>
|
|
<entry class="bitfield">01</entry>
|
|
<entry class="symbol">U16</entry>
|
|
</row>
|
|
<row>
|
|
<entry class="bitfield">1</entry>
|
|
<entry class="bitfield">10</entry>
|
|
<entry class="symbol">U32</entry>
|
|
</row>
|
|
<row>
|
|
<entry class="bitfield">1</entry>
|
|
<entry class="bitfield">11</entry>
|
|
<entry class="symbol">RESERVED</entry>
|
|
</row>
|
|
</tbody>
|
|
</tgroup>
|
|
</table>
|
|
</definition>
|
|
</account>
|
|
<account iclass="simd_2r_misc" symbol="<dt>" iclass_long="Advanced SIMD two registers misc">
|
|
<encodings>
|
|
<encoding encname="VPADAL_T1_D" />
|
|
<encoding encname="VPADAL_T1_Q" />
|
|
<encoding encname="VPADDL_T1_D" />
|
|
<encoding encname="VPADDL_T1_Q" />
|
|
</encodings>
|
|
<orig>Is the data type for the elements of the vectors, encoded in "op:size", where 000->S8, 001->S16, 010->S32, 100->U8, 101->U16, 110->U32, otherwise UNDEFINED</orig>
|
|
<definition encodedin="op:size">
|
|
<intro>Is the data type for the elements of the vectors, </intro>
|
|
<table class="valuetable">
|
|
<tgroup cols="3">
|
|
<thead>
|
|
<row>
|
|
<entry class="bitfield" bitwidth="1">op</entry>
|
|
<entry class="bitfield" bitwidth="2">size</entry>
|
|
<entry class="symbol"><dt></entry>
|
|
</row>
|
|
</thead>
|
|
<tbody>
|
|
<row>
|
|
<entry class="bitfield">0</entry>
|
|
<entry class="bitfield">00</entry>
|
|
<entry class="symbol">S8</entry>
|
|
</row>
|
|
<row>
|
|
<entry class="bitfield">0</entry>
|
|
<entry class="bitfield">01</entry>
|
|
<entry class="symbol">S16</entry>
|
|
</row>
|
|
<row>
|
|
<entry class="bitfield">0</entry>
|
|
<entry class="bitfield">10</entry>
|
|
<entry class="symbol">S32</entry>
|
|
</row>
|
|
<row>
|
|
<entry class="bitfield">0</entry>
|
|
<entry class="bitfield">11</entry>
|
|
<entry class="symbol">RESERVED</entry>
|
|
</row>
|
|
<row>
|
|
<entry class="bitfield">1</entry>
|
|
<entry class="bitfield">00</entry>
|
|
<entry class="symbol">U8</entry>
|
|
</row>
|
|
<row>
|
|
<entry class="bitfield">1</entry>
|
|
<entry class="bitfield">01</entry>
|
|
<entry class="symbol">U16</entry>
|
|
</row>
|
|
<row>
|
|
<entry class="bitfield">1</entry>
|
|
<entry class="bitfield">10</entry>
|
|
<entry class="symbol">U32</entry>
|
|
</row>
|
|
<row>
|
|
<entry class="bitfield">1</entry>
|
|
<entry class="bitfield">11</entry>
|
|
<entry class="symbol">RESERVED</entry>
|
|
</row>
|
|
</tbody>
|
|
</tgroup>
|
|
</table>
|
|
</definition>
|
|
</account>
|
|
<account iclass="simd2reg_misc" symbol="<dt>" iclass_long="Advanced SIMD two registers misc">
|
|
<encodings>
|
|
<encoding encname="VTRN_A1_D" />
|
|
<encoding encname="VTRN_A1_Q" />
|
|
<encoding encname="VUZP_A1_Q" />
|
|
<encoding encname="VZIP_A1_Q" />
|
|
</encodings>
|
|
<orig>Is the data type for the elements of the vectors, encoded in "size", where 00->8, 01->16, 10->32, otherwise UNDEFINED</orig>
|
|
<definition encodedin="size">
|
|
<intro>Is the data type for the elements of the vectors, </intro>
|
|
<table class="valuetable">
|
|
<tgroup cols="2">
|
|
<thead>
|
|
<row>
|
|
<entry class="bitfield" bitwidth="2">size</entry>
|
|
<entry class="symbol"><dt></entry>
|
|
</row>
|
|
</thead>
|
|
<tbody>
|
|
<row>
|
|
<entry class="bitfield">00</entry>
|
|
<entry class="symbol">8</entry>
|
|
</row>
|
|
<row>
|
|
<entry class="bitfield">01</entry>
|
|
<entry class="symbol">16</entry>
|
|
</row>
|
|
<row>
|
|
<entry class="bitfield">10</entry>
|
|
<entry class="symbol">32</entry>
|
|
</row>
|
|
<row>
|
|
<entry class="bitfield">11</entry>
|
|
<entry class="symbol">RESERVED</entry>
|
|
</row>
|
|
</tbody>
|
|
</tgroup>
|
|
</table>
|
|
</definition>
|
|
</account>
|
|
<account iclass="simd_2r_misc" symbol="<dt>" iclass_long="Advanced SIMD two registers misc">
|
|
<encodings>
|
|
<encoding encname="VTRN_T1_D" />
|
|
<encoding encname="VTRN_T1_Q" />
|
|
<encoding encname="VUZP_T1_Q" />
|
|
<encoding encname="VZIP_T1_Q" />
|
|
</encodings>
|
|
<orig>Is the data type for the elements of the vectors, encoded in "size", where 00->8, 01->16, 10->32, otherwise UNDEFINED</orig>
|
|
<definition encodedin="size">
|
|
<intro>Is the data type for the elements of the vectors, </intro>
|
|
<table class="valuetable">
|
|
<tgroup cols="2">
|
|
<thead>
|
|
<row>
|
|
<entry class="bitfield" bitwidth="2">size</entry>
|
|
<entry class="symbol"><dt></entry>
|
|
</row>
|
|
</thead>
|
|
<tbody>
|
|
<row>
|
|
<entry class="bitfield">00</entry>
|
|
<entry class="symbol">8</entry>
|
|
</row>
|
|
<row>
|
|
<entry class="bitfield">01</entry>
|
|
<entry class="symbol">16</entry>
|
|
</row>
|
|
<row>
|
|
<entry class="bitfield">10</entry>
|
|
<entry class="symbol">32</entry>
|
|
</row>
|
|
<row>
|
|
<entry class="bitfield">11</entry>
|
|
<entry class="symbol">RESERVED</entry>
|
|
</row>
|
|
</tbody>
|
|
</tgroup>
|
|
</table>
|
|
</definition>
|
|
</account>
|
|
<account iclass="simd2reg_misc" symbol="<dt>" iclass_long="Advanced SIMD two registers misc">
|
|
<encodings>
|
|
<encoding encname="VUZP_A1_D" />
|
|
<encoding encname="VZIP_A1_D" />
|
|
</encodings>
|
|
<orig>Is the data type for the elements of the vectors, encoded in "size", where 00->8, 01->16, otherwise UNDEFINED</orig>
|
|
<definition encodedin="size">
|
|
<intro>Is the data type for the elements of the vectors, </intro>
|
|
<table class="valuetable">
|
|
<tgroup cols="2">
|
|
<thead>
|
|
<row>
|
|
<entry class="bitfield" bitwidth="2">size</entry>
|
|
<entry class="symbol"><dt></entry>
|
|
</row>
|
|
</thead>
|
|
<tbody>
|
|
<row>
|
|
<entry class="bitfield">00</entry>
|
|
<entry class="symbol">8</entry>
|
|
</row>
|
|
<row>
|
|
<entry class="bitfield">01</entry>
|
|
<entry class="symbol">16</entry>
|
|
</row>
|
|
<row>
|
|
<entry class="bitfield">1x</entry>
|
|
<entry class="symbol">RESERVED</entry>
|
|
</row>
|
|
</tbody>
|
|
</tgroup>
|
|
</table>
|
|
</definition>
|
|
</account>
|
|
<account iclass="simd_2r_misc" symbol="<dt>" iclass_long="Advanced SIMD two registers misc">
|
|
<encodings>
|
|
<encoding encname="VUZP_T1_D" />
|
|
<encoding encname="VZIP_T1_D" />
|
|
</encodings>
|
|
<orig>Is the data type for the elements of the vectors, encoded in "size", where 00->8, 01->16, otherwise UNDEFINED</orig>
|
|
<definition encodedin="size">
|
|
<intro>Is the data type for the elements of the vectors, </intro>
|
|
<table class="valuetable">
|
|
<tgroup cols="2">
|
|
<thead>
|
|
<row>
|
|
<entry class="bitfield" bitwidth="2">size</entry>
|
|
<entry class="symbol"><dt></entry>
|
|
</row>
|
|
</thead>
|
|
<tbody>
|
|
<row>
|
|
<entry class="bitfield">00</entry>
|
|
<entry class="symbol">8</entry>
|
|
</row>
|
|
<row>
|
|
<entry class="bitfield">01</entry>
|
|
<entry class="symbol">16</entry>
|
|
</row>
|
|
<row>
|
|
<entry class="bitfield">1x</entry>
|
|
<entry class="symbol">RESERVED</entry>
|
|
</row>
|
|
</tbody>
|
|
</tgroup>
|
|
</table>
|
|
</definition>
|
|
</account>
|
|
<account iclass="simd2reg_misc" symbol="<dt>" iclass_long="Advanced SIMD two registers misc">
|
|
<encodings>
|
|
<encoding encname="VQABS_A1_D" />
|
|
<encoding encname="VQABS_A1_Q" />
|
|
<encoding encname="VQNEG_A1_D" />
|
|
<encoding encname="VQNEG_A1_Q" />
|
|
</encodings>
|
|
<orig>Is the data type for the elements of the vectors, encoded in "size", where 00->S8, 01->S16, 10->S32, otherwise UNDEFINED</orig>
|
|
<definition encodedin="size">
|
|
<intro>Is the data type for the elements of the vectors, </intro>
|
|
<table class="valuetable">
|
|
<tgroup cols="2">
|
|
<thead>
|
|
<row>
|
|
<entry class="bitfield" bitwidth="2">size</entry>
|
|
<entry class="symbol"><dt></entry>
|
|
</row>
|
|
</thead>
|
|
<tbody>
|
|
<row>
|
|
<entry class="bitfield">00</entry>
|
|
<entry class="symbol">S8</entry>
|
|
</row>
|
|
<row>
|
|
<entry class="bitfield">01</entry>
|
|
<entry class="symbol">S16</entry>
|
|
</row>
|
|
<row>
|
|
<entry class="bitfield">10</entry>
|
|
<entry class="symbol">S32</entry>
|
|
</row>
|
|
<row>
|
|
<entry class="bitfield">11</entry>
|
|
<entry class="symbol">RESERVED</entry>
|
|
</row>
|
|
</tbody>
|
|
</tgroup>
|
|
</table>
|
|
</definition>
|
|
</account>
|
|
<account iclass="simd_2r_misc" symbol="<dt>" iclass_long="Advanced SIMD two registers misc">
|
|
<encodings>
|
|
<encoding encname="VQABS_T1_D" />
|
|
<encoding encname="VQABS_T1_Q" />
|
|
<encoding encname="VQNEG_T1_D" />
|
|
<encoding encname="VQNEG_T1_Q" />
|
|
</encodings>
|
|
<orig>Is the data type for the elements of the vectors, encoded in "size", where 00->S8, 01->S16, 10->S32, otherwise UNDEFINED</orig>
|
|
<definition encodedin="size">
|
|
<intro>Is the data type for the elements of the vectors, </intro>
|
|
<table class="valuetable">
|
|
<tgroup cols="2">
|
|
<thead>
|
|
<row>
|
|
<entry class="bitfield" bitwidth="2">size</entry>
|
|
<entry class="symbol"><dt></entry>
|
|
</row>
|
|
</thead>
|
|
<tbody>
|
|
<row>
|
|
<entry class="bitfield">00</entry>
|
|
<entry class="symbol">S8</entry>
|
|
</row>
|
|
<row>
|
|
<entry class="bitfield">01</entry>
|
|
<entry class="symbol">S16</entry>
|
|
</row>
|
|
<row>
|
|
<entry class="bitfield">10</entry>
|
|
<entry class="symbol">S32</entry>
|
|
</row>
|
|
<row>
|
|
<entry class="bitfield">11</entry>
|
|
<entry class="symbol">RESERVED</entry>
|
|
</row>
|
|
</tbody>
|
|
</tgroup>
|
|
</table>
|
|
</definition>
|
|
</account>
|
|
<account iclass="simd2reg_misc" symbol="<dt>" iclass_long="Advanced SIMD two registers misc">
|
|
<encodings>
|
|
<encoding encname="VRINTA_asimd_A1_D" />
|
|
<encoding encname="VRINTA_asimd_A1_Q" />
|
|
<encoding encname="VRINTM_asimd_A1_D" />
|
|
<encoding encname="VRINTM_asimd_A1_Q" />
|
|
<encoding encname="VRINTN_asimd_A1_D" />
|
|
<encoding encname="VRINTN_asimd_A1_Q" />
|
|
<encoding encname="VRINTP_asimd_A1_D" />
|
|
<encoding encname="VRINTP_asimd_A1_Q" />
|
|
<encoding encname="VRINTX_asimd_A1_D" />
|
|
<encoding encname="VRINTX_asimd_A1_Q" />
|
|
<encoding encname="VRINTZ_asimd_A1_D" />
|
|
<encoding encname="VRINTZ_asimd_A1_Q" />
|
|
</encodings>
|
|
<orig>Is the data type for the elements of the vectors, encoded in "size", where 01->F16, 10->F32</orig>
|
|
<definition encodedin="size">
|
|
<intro>Is the data type for the elements of the vectors, </intro>
|
|
<table class="valuetable">
|
|
<tgroup cols="2">
|
|
<thead>
|
|
<row>
|
|
<entry class="bitfield" bitwidth="2">size</entry>
|
|
<entry class="symbol"><dt></entry>
|
|
</row>
|
|
</thead>
|
|
<tbody>
|
|
<row>
|
|
<entry class="bitfield">01</entry>
|
|
<entry class="symbol">F16</entry>
|
|
</row>
|
|
<row>
|
|
<entry class="bitfield">10</entry>
|
|
<entry class="symbol">F32</entry>
|
|
</row>
|
|
</tbody>
|
|
</tgroup>
|
|
</table>
|
|
</definition>
|
|
</account>
|
|
<account iclass="simd_2r_misc" symbol="<dt>" iclass_long="Advanced SIMD two registers misc">
|
|
<encodings>
|
|
<encoding encname="VRINTA_asimd_T1_D" />
|
|
<encoding encname="VRINTA_asimd_T1_Q" />
|
|
<encoding encname="VRINTM_asimd_T1_D" />
|
|
<encoding encname="VRINTM_asimd_T1_Q" />
|
|
<encoding encname="VRINTN_asimd_T1_D" />
|
|
<encoding encname="VRINTN_asimd_T1_Q" />
|
|
<encoding encname="VRINTP_asimd_T1_D" />
|
|
<encoding encname="VRINTP_asimd_T1_Q" />
|
|
<encoding encname="VRINTX_asimd_T1_D" />
|
|
<encoding encname="VRINTX_asimd_T1_Q" />
|
|
<encoding encname="VRINTZ_asimd_T1_D" />
|
|
<encoding encname="VRINTZ_asimd_T1_Q" />
|
|
</encodings>
|
|
<orig>Is the data type for the elements of the vectors, encoded in "size", where 01->F16, 10->F32</orig>
|
|
<definition encodedin="size">
|
|
<intro>Is the data type for the elements of the vectors, </intro>
|
|
<table class="valuetable">
|
|
<tgroup cols="2">
|
|
<thead>
|
|
<row>
|
|
<entry class="bitfield" bitwidth="2">size</entry>
|
|
<entry class="symbol"><dt></entry>
|
|
</row>
|
|
</thead>
|
|
<tbody>
|
|
<row>
|
|
<entry class="bitfield">01</entry>
|
|
<entry class="symbol">F16</entry>
|
|
</row>
|
|
<row>
|
|
<entry class="bitfield">10</entry>
|
|
<entry class="symbol">F32</entry>
|
|
</row>
|
|
</tbody>
|
|
</tgroup>
|
|
</table>
|
|
</definition>
|
|
</account>
|
|
<account iclass="simd2reg_misc" symbol="<dt>" iclass_long="Advanced SIMD two registers misc">
|
|
<encodings>
|
|
<encoding encname="AESD_A1" />
|
|
<encoding encname="AESE_A1" />
|
|
<encoding encname="AESIMC_A1" />
|
|
<encoding encname="AESMC_A1" />
|
|
</encodings>
|
|
<orig>Is the data type, encoded in "size", where 00->8, otherwise UNDEFINED.</orig>
|
|
<definition encodedin="size">
|
|
<intro>Is the data type, </intro>
|
|
<table class="valuetable">
|
|
<tgroup cols="2">
|
|
<thead>
|
|
<row>
|
|
<entry class="bitfield" bitwidth="2">size</entry>
|
|
<entry class="symbol"><dt></entry>
|
|
</row>
|
|
</thead>
|
|
<tbody>
|
|
<row>
|
|
<entry class="bitfield">00</entry>
|
|
<entry class="symbol">8</entry>
|
|
</row>
|
|
<row>
|
|
<entry class="bitfield">01</entry>
|
|
<entry class="symbol">RESERVED</entry>
|
|
</row>
|
|
<row>
|
|
<entry class="bitfield">1x</entry>
|
|
<entry class="symbol">RESERVED</entry>
|
|
</row>
|
|
</tbody>
|
|
</tgroup>
|
|
</table>
|
|
</definition>
|
|
</account>
|
|
<account iclass="simd_2r_misc" symbol="<dt>" iclass_long="Advanced SIMD two registers misc">
|
|
<encodings>
|
|
<encoding encname="AESD_T1" />
|
|
<encoding encname="AESE_T1" />
|
|
<encoding encname="AESIMC_T1" />
|
|
<encoding encname="AESMC_T1" />
|
|
</encodings>
|
|
<orig>Is the data type, encoded in "size", where 00->8, otherwise UNDEFINED.</orig>
|
|
<definition encodedin="size">
|
|
<intro>Is the data type, </intro>
|
|
<table class="valuetable">
|
|
<tgroup cols="2">
|
|
<thead>
|
|
<row>
|
|
<entry class="bitfield" bitwidth="2">size</entry>
|
|
<entry class="symbol"><dt></entry>
|
|
</row>
|
|
</thead>
|
|
<tbody>
|
|
<row>
|
|
<entry class="bitfield">00</entry>
|
|
<entry class="symbol">8</entry>
|
|
</row>
|
|
<row>
|
|
<entry class="bitfield">01</entry>
|
|
<entry class="symbol">RESERVED</entry>
|
|
</row>
|
|
<row>
|
|
<entry class="bitfield">1x</entry>
|
|
<entry class="symbol">RESERVED</entry>
|
|
</row>
|
|
</tbody>
|
|
</tgroup>
|
|
</table>
|
|
</definition>
|
|
</account>
|
|
<account iclass="cps" symbol="<endian_specifier>" iclass_long="Change Process State">
|
|
<encodings>
|
|
<encoding encname="SETEND_A1" />
|
|
</encodings>
|
|
<orig>Is the endianness to be selected, and the value to be set in PSTATE.E, encoded in "E", where 0->LE, 1->BE</orig>
|
|
<definition encodedin="E">
|
|
<intro>Is the endianness to be selected, and the value to be set in PSTATE.E, </intro>
|
|
<table class="valuetable">
|
|
<tgroup cols="2">
|
|
<thead>
|
|
<row>
|
|
<entry class="bitfield" bitwidth="1">E</entry>
|
|
<entry class="symbol"><endian_specifier></entry>
|
|
</row>
|
|
</thead>
|
|
<tbody>
|
|
<row>
|
|
<entry class="bitfield">0</entry>
|
|
<entry class="symbol">LE</entry>
|
|
</row>
|
|
<row>
|
|
<entry class="bitfield">1</entry>
|
|
<entry class="symbol">BE</entry>
|
|
</row>
|
|
</tbody>
|
|
</tgroup>
|
|
</table>
|
|
</definition>
|
|
</account>
|
|
<account iclass="cps16" symbol="<endian_specifier>" iclass_long="Change Processor State">
|
|
<encodings>
|
|
<encoding encname="SETEND_T1" />
|
|
</encodings>
|
|
<orig>Is the endianness to be selected, and the value to be set in PSTATE.E, encoded in "E", where 0->LE, 1->BE</orig>
|
|
<definition encodedin="E">
|
|
<intro>Is the endianness to be selected, and the value to be set in PSTATE.E, </intro>
|
|
<table class="valuetable">
|
|
<tgroup cols="2">
|
|
<thead>
|
|
<row>
|
|
<entry class="bitfield" bitwidth="1">E</entry>
|
|
<entry class="symbol"><endian_specifier></entry>
|
|
</row>
|
|
</thead>
|
|
<tbody>
|
|
<row>
|
|
<entry class="bitfield">0</entry>
|
|
<entry class="symbol">LE</entry>
|
|
</row>
|
|
<row>
|
|
<entry class="bitfield">1</entry>
|
|
<entry class="symbol">BE</entry>
|
|
</row>
|
|
</tbody>
|
|
</tgroup>
|
|
</table>
|
|
</definition>
|
|
</account>
|
|
<account iclass="dpint_shiftr" symbol="<shift>" iclass_long="Data-processing (shifted register)">
|
|
<encodings>
|
|
<encoding encname="ADCS_r_T2" />
|
|
<encoding encname="ADC_r_T2" />
|
|
<encoding encname="ADDS_SP_r_T3" />
|
|
<encoding encname="ADDS_r_T3" />
|
|
<encoding encname="ADD_SP_r_T3" />
|
|
<encoding encname="ADD_r_T3" />
|
|
<encoding encname="ANDS_r_T2" />
|
|
<encoding encname="AND_r_T2" />
|
|
<encoding encname="BICS_r_T2" />
|
|
<encoding encname="BIC_r_T2" />
|
|
<encoding encname="CMN_r_T2" />
|
|
<encoding encname="CMP_r_T3" />
|
|
<encoding encname="EORS_r_T2" />
|
|
<encoding encname="EOR_r_T2" />
|
|
<encoding encname="ORNS_r_T1" />
|
|
<encoding encname="ORN_r_T1" />
|
|
<encoding encname="ORRS_r_T2" />
|
|
<encoding encname="ORR_r_T2" />
|
|
<encoding encname="RSBS_r_T1" />
|
|
<encoding encname="RSB_r_T1" />
|
|
<encoding encname="SBCS_r_T2" />
|
|
<encoding encname="SBC_r_T2" />
|
|
<encoding encname="SUBS_SP_r_T1" />
|
|
<encoding encname="SUBS_r_T2" />
|
|
<encoding encname="SUB_SP_r_T1" />
|
|
<encoding encname="SUB_r_T2" />
|
|
<encoding encname="TEQ_r_T1" />
|
|
<encoding encname="TST_r_T2" />
|
|
</encodings>
|
|
<orig>Is the type of shift to be applied to the second source register, encoded in "stype", where 00->LSL, 01->LSR, 10->ASR, 11->ROR.</orig>
|
|
<definition encodedin="stype">
|
|
<intro>Is the type of shift to be applied to the second source register, </intro>
|
|
<table class="valuetable">
|
|
<tgroup cols="2">
|
|
<thead>
|
|
<row>
|
|
<entry class="bitfield" bitwidth="2">stype</entry>
|
|
<entry class="symbol"><shift></entry>
|
|
</row>
|
|
</thead>
|
|
<tbody>
|
|
<row>
|
|
<entry class="bitfield">00</entry>
|
|
<entry class="symbol">LSL</entry>
|
|
</row>
|
|
<row>
|
|
<entry class="bitfield">01</entry>
|
|
<entry class="symbol">LSR</entry>
|
|
</row>
|
|
<row>
|
|
<entry class="bitfield">10</entry>
|
|
<entry class="symbol">ASR</entry>
|
|
</row>
|
|
<row>
|
|
<entry class="bitfield">11</entry>
|
|
<entry class="symbol">ROR</entry>
|
|
</row>
|
|
</tbody>
|
|
</tgroup>
|
|
</table>
|
|
</definition>
|
|
</account>
|
|
<account iclass="dpint_shiftr" symbol="<shift>" iclass_long="Data-processing (shifted register)">
|
|
<encodings>
|
|
<encoding encname="MOVS_r_T3" />
|
|
<encoding encname="MOV_r_T3" />
|
|
<encoding encname="MVNS_r_T2" />
|
|
<encoding encname="MVN_r_T2" />
|
|
</encodings>
|
|
<orig>Is the type of shift to be applied to the source register, encoded in "stype", where 00->LSL, 01->LSR, 10->ASR, 11->ROR.</orig>
|
|
<definition encodedin="stype">
|
|
<intro>Is the type of shift to be applied to the source register, </intro>
|
|
<table class="valuetable">
|
|
<tgroup cols="2">
|
|
<thead>
|
|
<row>
|
|
<entry class="bitfield" bitwidth="2">stype</entry>
|
|
<entry class="symbol"><shift></entry>
|
|
</row>
|
|
</thead>
|
|
<tbody>
|
|
<row>
|
|
<entry class="bitfield">00</entry>
|
|
<entry class="symbol">LSL</entry>
|
|
</row>
|
|
<row>
|
|
<entry class="bitfield">01</entry>
|
|
<entry class="symbol">LSR</entry>
|
|
</row>
|
|
<row>
|
|
<entry class="bitfield">10</entry>
|
|
<entry class="symbol">ASR</entry>
|
|
</row>
|
|
<row>
|
|
<entry class="bitfield">11</entry>
|
|
<entry class="symbol">ROR</entry>
|
|
</row>
|
|
</tbody>
|
|
</tgroup>
|
|
</table>
|
|
</definition>
|
|
</account>
|
|
<account iclass="extend" symbol="<amount>" iclass_long="Extend and Add">
|
|
<encodings>
|
|
<encoding encname="SXTAB16_A1" />
|
|
<encoding encname="SXTAB_A1" />
|
|
<encoding encname="SXTAH_A1" />
|
|
<encoding encname="SXTB16_A1" />
|
|
<encoding encname="SXTB_A1" />
|
|
<encoding encname="SXTH_A1" />
|
|
<encoding encname="UXTAB16_A1" />
|
|
<encoding encname="UXTAB_A1" />
|
|
<encoding encname="UXTAH_A1" />
|
|
<encoding encname="UXTB16_A1" />
|
|
<encoding encname="UXTB_A1" />
|
|
<encoding encname="UXTH_A1" />
|
|
</encodings>
|
|
<orig>Is the rotate amount, encoded in "rotate", where 00->(omitted), 01->8, 10->16, 11->24</orig>
|
|
<definition encodedin="rotate">
|
|
<intro>Is the rotate amount, </intro>
|
|
<table class="valuetable">
|
|
<tgroup cols="2">
|
|
<thead>
|
|
<row>
|
|
<entry class="bitfield" bitwidth="2">rotate</entry>
|
|
<entry class="symbol"><amount></entry>
|
|
</row>
|
|
</thead>
|
|
<tbody>
|
|
<row>
|
|
<entry class="bitfield">00</entry>
|
|
<entry class="symbol">(omitted)</entry>
|
|
</row>
|
|
<row>
|
|
<entry class="bitfield">01</entry>
|
|
<entry class="symbol">8</entry>
|
|
</row>
|
|
<row>
|
|
<entry class="bitfield">10</entry>
|
|
<entry class="symbol">16</entry>
|
|
</row>
|
|
<row>
|
|
<entry class="bitfield">11</entry>
|
|
<entry class="symbol">24</entry>
|
|
</row>
|
|
</tbody>
|
|
</tgroup>
|
|
</table>
|
|
</definition>
|
|
</account>
|
|
<account iclass="fpdp2reg" symbol="<dt>" iclass_long="Floating-point data-processing (two registers)">
|
|
<encodings>
|
|
<encoding encname="VCVT_toxv_A1_D" />
|
|
<encoding encname="VCVT_toxv_A1_H" />
|
|
<encoding encname="VCVT_toxv_A1_S" />
|
|
<encoding encname="VCVT_xv_A1_D" />
|
|
<encoding encname="VCVT_xv_A1_H" />
|
|
<encoding encname="VCVT_xv_A1_S" />
|
|
</encodings>
|
|
<orig>Is the data type for the fixed-point number, encoded in "U:sx", where 00->S16, 10->U16, 01->S32, 11->U32</orig>
|
|
<definition encodedin="U:sx">
|
|
<intro>Is the data type for the fixed-point number, </intro>
|
|
<table class="valuetable">
|
|
<tgroup cols="3">
|
|
<thead>
|
|
<row>
|
|
<entry class="bitfield" bitwidth="1">U</entry>
|
|
<entry class="bitfield" bitwidth="1">sx</entry>
|
|
<entry class="symbol"><dt></entry>
|
|
</row>
|
|
</thead>
|
|
<tbody>
|
|
<row>
|
|
<entry class="bitfield">0</entry>
|
|
<entry class="bitfield">0</entry>
|
|
<entry class="symbol">S16</entry>
|
|
</row>
|
|
<row>
|
|
<entry class="bitfield">0</entry>
|
|
<entry class="bitfield">1</entry>
|
|
<entry class="symbol">S32</entry>
|
|
</row>
|
|
<row>
|
|
<entry class="bitfield">1</entry>
|
|
<entry class="bitfield">0</entry>
|
|
<entry class="symbol">U16</entry>
|
|
</row>
|
|
<row>
|
|
<entry class="bitfield">1</entry>
|
|
<entry class="bitfield">1</entry>
|
|
<entry class="symbol">U32</entry>
|
|
</row>
|
|
</tbody>
|
|
</tgroup>
|
|
</table>
|
|
</definition>
|
|
</account>
|
|
<account iclass="fp_2r" symbol="<dt>" iclass_long="Floating-point data-processing (two registers)">
|
|
<encodings>
|
|
<encoding encname="VCVT_toxv_T1_D" />
|
|
<encoding encname="VCVT_toxv_T1_H" />
|
|
<encoding encname="VCVT_toxv_T1_S" />
|
|
<encoding encname="VCVT_xv_T1_D" />
|
|
<encoding encname="VCVT_xv_T1_H" />
|
|
<encoding encname="VCVT_xv_T1_S" />
|
|
</encodings>
|
|
<orig>Is the data type for the fixed-point number, encoded in "U:sx", where 00->S16, 10->U16, 01->S32, 11->U32</orig>
|
|
<definition encodedin="U:sx">
|
|
<intro>Is the data type for the fixed-point number, </intro>
|
|
<table class="valuetable">
|
|
<tgroup cols="3">
|
|
<thead>
|
|
<row>
|
|
<entry class="bitfield" bitwidth="1">U</entry>
|
|
<entry class="bitfield" bitwidth="1">sx</entry>
|
|
<entry class="symbol"><dt></entry>
|
|
</row>
|
|
</thead>
|
|
<tbody>
|
|
<row>
|
|
<entry class="bitfield">0</entry>
|
|
<entry class="bitfield">0</entry>
|
|
<entry class="symbol">S16</entry>
|
|
</row>
|
|
<row>
|
|
<entry class="bitfield">0</entry>
|
|
<entry class="bitfield">1</entry>
|
|
<entry class="symbol">S32</entry>
|
|
</row>
|
|
<row>
|
|
<entry class="bitfield">1</entry>
|
|
<entry class="bitfield">0</entry>
|
|
<entry class="symbol">U16</entry>
|
|
</row>
|
|
<row>
|
|
<entry class="bitfield">1</entry>
|
|
<entry class="bitfield">1</entry>
|
|
<entry class="symbol">U32</entry>
|
|
</row>
|
|
</tbody>
|
|
</tgroup>
|
|
</table>
|
|
</definition>
|
|
</account>
|
|
<account iclass="fpdp2reg" symbol="<dt>" iclass_long="Floating-point data-processing (two registers)">
|
|
<encodings>
|
|
<encoding encname="VCVT_vi_A1_D" />
|
|
<encoding encname="VCVT_vi_A1_H" />
|
|
<encoding encname="VCVT_vi_A1_S" />
|
|
</encodings>
|
|
<orig>Is the data type for the operand, encoded in "op", where 0->U32, 1->S32</orig>
|
|
<definition encodedin="op">
|
|
<intro>Is the data type for the operand, </intro>
|
|
<table class="valuetable">
|
|
<tgroup cols="2">
|
|
<thead>
|
|
<row>
|
|
<entry class="bitfield" bitwidth="1">op</entry>
|
|
<entry class="symbol"><dt></entry>
|
|
</row>
|
|
</thead>
|
|
<tbody>
|
|
<row>
|
|
<entry class="bitfield">0</entry>
|
|
<entry class="symbol">U32</entry>
|
|
</row>
|
|
<row>
|
|
<entry class="bitfield">1</entry>
|
|
<entry class="symbol">S32</entry>
|
|
</row>
|
|
</tbody>
|
|
</tgroup>
|
|
</table>
|
|
</definition>
|
|
</account>
|
|
<account iclass="fp_2r" symbol="<dt>" iclass_long="Floating-point data-processing (two registers)">
|
|
<encodings>
|
|
<encoding encname="VCVT_vi_T1_D" />
|
|
<encoding encname="VCVT_vi_T1_H" />
|
|
<encoding encname="VCVT_vi_T1_S" />
|
|
</encodings>
|
|
<orig>Is the data type for the operand, encoded in "op", where 0->U32, 1->S32</orig>
|
|
<definition encodedin="op">
|
|
<intro>Is the data type for the operand, </intro>
|
|
<table class="valuetable">
|
|
<tgroup cols="2">
|
|
<thead>
|
|
<row>
|
|
<entry class="bitfield" bitwidth="1">op</entry>
|
|
<entry class="symbol"><dt></entry>
|
|
</row>
|
|
</thead>
|
|
<tbody>
|
|
<row>
|
|
<entry class="bitfield">0</entry>
|
|
<entry class="symbol">U32</entry>
|
|
</row>
|
|
<row>
|
|
<entry class="bitfield">1</entry>
|
|
<entry class="symbol">S32</entry>
|
|
</row>
|
|
</tbody>
|
|
</tgroup>
|
|
</table>
|
|
</definition>
|
|
</account>
|
|
<account iclass="fpcvtrnd" symbol="<dt>" iclass_long="Floating-point directed convert to integer">
|
|
<encodings>
|
|
<encoding encname="VCVTA_vfp_A1_D" />
|
|
<encoding encname="VCVTA_vfp_A1_H" />
|
|
<encoding encname="VCVTA_vfp_A1_S" />
|
|
<encoding encname="VCVTM_vfp_A1_D" />
|
|
<encoding encname="VCVTM_vfp_A1_H" />
|
|
<encoding encname="VCVTM_vfp_A1_S" />
|
|
<encoding encname="VCVTN_vfp_A1_D" />
|
|
<encoding encname="VCVTN_vfp_A1_H" />
|
|
<encoding encname="VCVTN_vfp_A1_S" />
|
|
<encoding encname="VCVTP_vfp_A1_D" />
|
|
<encoding encname="VCVTP_vfp_A1_H" />
|
|
<encoding encname="VCVTP_vfp_A1_S" />
|
|
</encodings>
|
|
<orig>Is the data type for the elements of the destination, encoded in "op" where 0->U32, 1->S32</orig>
|
|
<definition encodedin="op">
|
|
<intro>Is the data type for the elements of the destination, </intro>
|
|
<table class="valuetable">
|
|
<tgroup cols="2">
|
|
<thead>
|
|
<row>
|
|
<entry class="bitfield" bitwidth="1">op</entry>
|
|
<entry class="symbol"><dt></entry>
|
|
</row>
|
|
</thead>
|
|
<tbody>
|
|
<row>
|
|
<entry class="bitfield">0</entry>
|
|
<entry class="symbol">U32</entry>
|
|
</row>
|
|
<row>
|
|
<entry class="bitfield">1</entry>
|
|
<entry class="symbol">S32</entry>
|
|
</row>
|
|
</tbody>
|
|
</tgroup>
|
|
</table>
|
|
</definition>
|
|
</account>
|
|
<account iclass="fp_toint" symbol="<dt>" iclass_long="Floating-point directed convert to integer">
|
|
<encodings>
|
|
<encoding encname="VCVTA_vfp_T1_D" />
|
|
<encoding encname="VCVTA_vfp_T1_H" />
|
|
<encoding encname="VCVTA_vfp_T1_S" />
|
|
<encoding encname="VCVTM_vfp_T1_D" />
|
|
<encoding encname="VCVTM_vfp_T1_H" />
|
|
<encoding encname="VCVTM_vfp_T1_S" />
|
|
<encoding encname="VCVTN_vfp_T1_D" />
|
|
<encoding encname="VCVTN_vfp_T1_H" />
|
|
<encoding encname="VCVTN_vfp_T1_S" />
|
|
<encoding encname="VCVTP_vfp_T1_D" />
|
|
<encoding encname="VCVTP_vfp_T1_H" />
|
|
<encoding encname="VCVTP_vfp_T1_S" />
|
|
</encodings>
|
|
<orig>Is the data type for the elements of the destination, encoded in "op" where 0->U32, 1->S32</orig>
|
|
<definition encodedin="op">
|
|
<intro>Is the data type for the elements of the destination, </intro>
|
|
<table class="valuetable">
|
|
<tgroup cols="2">
|
|
<thead>
|
|
<row>
|
|
<entry class="bitfield" bitwidth="1">op</entry>
|
|
<entry class="symbol"><dt></entry>
|
|
</row>
|
|
</thead>
|
|
<tbody>
|
|
<row>
|
|
<entry class="bitfield">0</entry>
|
|
<entry class="symbol">U32</entry>
|
|
</row>
|
|
<row>
|
|
<entry class="bitfield">1</entry>
|
|
<entry class="symbol">S32</entry>
|
|
</row>
|
|
</tbody>
|
|
</tgroup>
|
|
</table>
|
|
</definition>
|
|
</account>
|
|
<account iclass="movfpsr" symbol="<spec_reg>" iclass_long="Floating-point move special register">
|
|
<encodings>
|
|
<encoding encname="VMSR_A1_AS" />
|
|
</encodings>
|
|
<orig>Is the destination Advanced SIMD and floating-point System register, encoded in "reg", where 0000->FPSID, 0001->FPSCR, 1000->FPEXC, otherwise UNPREDICTABLE</orig>
|
|
<definition encodedin="reg">
|
|
<intro>Is the destination Advanced SIMD and floating-point System register, </intro>
|
|
<table class="valuetable">
|
|
<tgroup cols="2">
|
|
<thead>
|
|
<row>
|
|
<entry class="bitfield" bitwidth="4">reg</entry>
|
|
<entry class="symbol"><spec_reg></entry>
|
|
</row>
|
|
</thead>
|
|
<tbody>
|
|
<row>
|
|
<entry class="bitfield">0000</entry>
|
|
<entry class="symbol">FPSID</entry>
|
|
</row>
|
|
<row>
|
|
<entry class="bitfield">0001</entry>
|
|
<entry class="symbol">FPSCR</entry>
|
|
</row>
|
|
<row>
|
|
<entry class="bitfield">001x</entry>
|
|
<entry class="symbol">UNPREDICTABLE</entry>
|
|
</row>
|
|
<row>
|
|
<entry class="bitfield">01xx</entry>
|
|
<entry class="symbol">UNPREDICTABLE</entry>
|
|
</row>
|
|
<row>
|
|
<entry class="bitfield">1000</entry>
|
|
<entry class="symbol">FPEXC</entry>
|
|
</row>
|
|
<row>
|
|
<entry class="bitfield">1001</entry>
|
|
<entry class="symbol">UNPREDICTABLE</entry>
|
|
</row>
|
|
<row>
|
|
<entry class="bitfield">101x</entry>
|
|
<entry class="symbol">UNPREDICTABLE</entry>
|
|
</row>
|
|
<row>
|
|
<entry class="bitfield">11xx</entry>
|
|
<entry class="symbol">UNPREDICTABLE</entry>
|
|
</row>
|
|
</tbody>
|
|
</tgroup>
|
|
</table>
|
|
</definition>
|
|
</account>
|
|
<account iclass="fp_msr" symbol="<spec_reg>" iclass_long="Floating-point move special register">
|
|
<encodings>
|
|
<encoding encname="VMSR_T1_AS" />
|
|
</encodings>
|
|
<orig>Is the destination Advanced SIMD and floating-point System register, encoded in "reg", where 0000->FPSID, 0001->FPSCR, 1000->FPEXC, otherwise UNPREDICTABLE</orig>
|
|
<definition encodedin="reg">
|
|
<intro>Is the destination Advanced SIMD and floating-point System register, </intro>
|
|
<table class="valuetable">
|
|
<tgroup cols="2">
|
|
<thead>
|
|
<row>
|
|
<entry class="bitfield" bitwidth="4">reg</entry>
|
|
<entry class="symbol"><spec_reg></entry>
|
|
</row>
|
|
</thead>
|
|
<tbody>
|
|
<row>
|
|
<entry class="bitfield">0000</entry>
|
|
<entry class="symbol">FPSID</entry>
|
|
</row>
|
|
<row>
|
|
<entry class="bitfield">0001</entry>
|
|
<entry class="symbol">FPSCR</entry>
|
|
</row>
|
|
<row>
|
|
<entry class="bitfield">001x</entry>
|
|
<entry class="symbol">UNPREDICTABLE</entry>
|
|
</row>
|
|
<row>
|
|
<entry class="bitfield">01xx</entry>
|
|
<entry class="symbol">UNPREDICTABLE</entry>
|
|
</row>
|
|
<row>
|
|
<entry class="bitfield">1000</entry>
|
|
<entry class="symbol">FPEXC</entry>
|
|
</row>
|
|
<row>
|
|
<entry class="bitfield">1001</entry>
|
|
<entry class="symbol">UNPREDICTABLE</entry>
|
|
</row>
|
|
<row>
|
|
<entry class="bitfield">101x</entry>
|
|
<entry class="symbol">UNPREDICTABLE</entry>
|
|
</row>
|
|
<row>
|
|
<entry class="bitfield">11xx</entry>
|
|
<entry class="symbol">UNPREDICTABLE</entry>
|
|
</row>
|
|
</tbody>
|
|
</tgroup>
|
|
</table>
|
|
</definition>
|
|
</account>
|
|
<account iclass="movfpsr" symbol="<spec_reg>" iclass_long="Floating-point move special register">
|
|
<encodings>
|
|
<encoding encname="VMRS_A1_AS" />
|
|
</encodings>
|
|
<orig>Is the source Advanced SIMD and floating-point System register, encoded in "reg", where 0000->FPSID, 0001->FPSCR, 0101->MVFR2, 0110->MVFR1, 0111->MVFR0, 1000->FPEXC, otherwise UNPREDICTABLE</orig>
|
|
<definition encodedin="reg">
|
|
<intro>Is the source Advanced SIMD and floating-point System register, </intro>
|
|
<table class="valuetable">
|
|
<tgroup cols="2">
|
|
<thead>
|
|
<row>
|
|
<entry class="bitfield" bitwidth="4">reg</entry>
|
|
<entry class="symbol"><spec_reg></entry>
|
|
</row>
|
|
</thead>
|
|
<tbody>
|
|
<row>
|
|
<entry class="bitfield">0000</entry>
|
|
<entry class="symbol">FPSID</entry>
|
|
</row>
|
|
<row>
|
|
<entry class="bitfield">0001</entry>
|
|
<entry class="symbol">FPSCR</entry>
|
|
</row>
|
|
<row>
|
|
<entry class="bitfield">001x</entry>
|
|
<entry class="symbol">UNPREDICTABLE</entry>
|
|
</row>
|
|
<row>
|
|
<entry class="bitfield">0100</entry>
|
|
<entry class="symbol">UNPREDICTABLE</entry>
|
|
</row>
|
|
<row>
|
|
<entry class="bitfield">0101</entry>
|
|
<entry class="symbol">MVFR2</entry>
|
|
</row>
|
|
<row>
|
|
<entry class="bitfield">0110</entry>
|
|
<entry class="symbol">MVFR1</entry>
|
|
</row>
|
|
<row>
|
|
<entry class="bitfield">0111</entry>
|
|
<entry class="symbol">MVFR0</entry>
|
|
</row>
|
|
<row>
|
|
<entry class="bitfield">1000</entry>
|
|
<entry class="symbol">FPEXC</entry>
|
|
</row>
|
|
<row>
|
|
<entry class="bitfield">1001</entry>
|
|
<entry class="symbol">UNPREDICTABLE</entry>
|
|
</row>
|
|
<row>
|
|
<entry class="bitfield">101x</entry>
|
|
<entry class="symbol">UNPREDICTABLE</entry>
|
|
</row>
|
|
<row>
|
|
<entry class="bitfield">11xx</entry>
|
|
<entry class="symbol">UNPREDICTABLE</entry>
|
|
</row>
|
|
</tbody>
|
|
</tgroup>
|
|
</table>
|
|
</definition>
|
|
</account>
|
|
<account iclass="fp_msr" symbol="<spec_reg>" iclass_long="Floating-point move special register">
|
|
<encodings>
|
|
<encoding encname="VMRS_T1_AS" />
|
|
</encodings>
|
|
<orig>Is the source Advanced SIMD and floating-point System register, encoded in "reg", where 0000->FPSID, 0001->FPSCR, 0101->MVFR2, 0110->MVFR1, 0111->MVFR0, 1000->FPEXC, otherwise UNPREDICTABLE</orig>
|
|
<definition encodedin="reg">
|
|
<intro>Is the source Advanced SIMD and floating-point System register, </intro>
|
|
<table class="valuetable">
|
|
<tgroup cols="2">
|
|
<thead>
|
|
<row>
|
|
<entry class="bitfield" bitwidth="4">reg</entry>
|
|
<entry class="symbol"><spec_reg></entry>
|
|
</row>
|
|
</thead>
|
|
<tbody>
|
|
<row>
|
|
<entry class="bitfield">0000</entry>
|
|
<entry class="symbol">FPSID</entry>
|
|
</row>
|
|
<row>
|
|
<entry class="bitfield">0001</entry>
|
|
<entry class="symbol">FPSCR</entry>
|
|
</row>
|
|
<row>
|
|
<entry class="bitfield">001x</entry>
|
|
<entry class="symbol">UNPREDICTABLE</entry>
|
|
</row>
|
|
<row>
|
|
<entry class="bitfield">0100</entry>
|
|
<entry class="symbol">UNPREDICTABLE</entry>
|
|
</row>
|
|
<row>
|
|
<entry class="bitfield">0101</entry>
|
|
<entry class="symbol">MVFR2</entry>
|
|
</row>
|
|
<row>
|
|
<entry class="bitfield">0110</entry>
|
|
<entry class="symbol">MVFR1</entry>
|
|
</row>
|
|
<row>
|
|
<entry class="bitfield">0111</entry>
|
|
<entry class="symbol">MVFR0</entry>
|
|
</row>
|
|
<row>
|
|
<entry class="bitfield">1000</entry>
|
|
<entry class="symbol">FPEXC</entry>
|
|
</row>
|
|
<row>
|
|
<entry class="bitfield">1001</entry>
|
|
<entry class="symbol">UNPREDICTABLE</entry>
|
|
</row>
|
|
<row>
|
|
<entry class="bitfield">101x</entry>
|
|
<entry class="symbol">UNPREDICTABLE</entry>
|
|
</row>
|
|
<row>
|
|
<entry class="bitfield">11xx</entry>
|
|
<entry class="symbol">UNPREDICTABLE</entry>
|
|
</row>
|
|
</tbody>
|
|
</tgroup>
|
|
</table>
|
|
</definition>
|
|
</account>
|
|
<account iclass="intdp3reg_immsh" symbol="<shift>" iclass_long="Integer Data Processing (three register, immediate shift)">
|
|
<encodings>
|
|
<encoding encname="ADCS_r_A1" />
|
|
<encoding encname="ADC_r_A1" />
|
|
<encoding encname="ADDS_SP_r_A1" />
|
|
<encoding encname="ADDS_r_A1" />
|
|
<encoding encname="ADD_SP_r_A1" />
|
|
<encoding encname="ADD_r_A1" />
|
|
<encoding encname="ANDS_r_A1" />
|
|
<encoding encname="AND_r_A1" />
|
|
<encoding encname="EORS_r_A1" />
|
|
<encoding encname="EOR_r_A1" />
|
|
<encoding encname="RSBS_r_A1" />
|
|
<encoding encname="RSB_r_A1" />
|
|
<encoding encname="RSCS_r_A1" />
|
|
<encoding encname="RSC_r_A1" />
|
|
<encoding encname="SBCS_r_A1" />
|
|
<encoding encname="SBC_r_A1" />
|
|
<encoding encname="SUBS_SP_r_A1" />
|
|
<encoding encname="SUBS_r_A1" />
|
|
<encoding encname="SUB_SP_r_A1" />
|
|
<encoding encname="SUB_r_A1" />
|
|
</encodings>
|
|
<orig>Is the type of shift to be applied to the second source register, encoded in "stype", where 00->LSL, 01->LSR, 10->ASR, 11->ROR.</orig>
|
|
<definition encodedin="stype">
|
|
<intro>Is the type of shift to be applied to the second source register, </intro>
|
|
<table class="valuetable">
|
|
<tgroup cols="2">
|
|
<thead>
|
|
<row>
|
|
<entry class="bitfield" bitwidth="2">stype</entry>
|
|
<entry class="symbol"><shift></entry>
|
|
</row>
|
|
</thead>
|
|
<tbody>
|
|
<row>
|
|
<entry class="bitfield">00</entry>
|
|
<entry class="symbol">LSL</entry>
|
|
</row>
|
|
<row>
|
|
<entry class="bitfield">01</entry>
|
|
<entry class="symbol">LSR</entry>
|
|
</row>
|
|
<row>
|
|
<entry class="bitfield">10</entry>
|
|
<entry class="symbol">ASR</entry>
|
|
</row>
|
|
<row>
|
|
<entry class="bitfield">11</entry>
|
|
<entry class="symbol">ROR</entry>
|
|
</row>
|
|
</tbody>
|
|
</tgroup>
|
|
</table>
|
|
</definition>
|
|
</account>
|
|
<account iclass="intdp3reg_regsh" symbol="<shift>" iclass_long="Integer Data Processing (three register, register shift)">
|
|
<encodings>
|
|
<encoding encname="ADCS_rr_A1" />
|
|
<encoding encname="ADC_rr_A1" />
|
|
<encoding encname="ADDS_rr_A1" />
|
|
<encoding encname="ADD_rr_A1" />
|
|
<encoding encname="ANDS_rr_A1" />
|
|
<encoding encname="AND_rr_A1" />
|
|
<encoding encname="EORS_rr_A1" />
|
|
<encoding encname="EOR_rr_A1" />
|
|
<encoding encname="RSBS_rr_A1" />
|
|
<encoding encname="RSB_rr_A1" />
|
|
<encoding encname="RSCS_rr_A1" />
|
|
<encoding encname="RSC_rr_A1" />
|
|
<encoding encname="SBCS_rr_A1" />
|
|
<encoding encname="SBC_rr_A1" />
|
|
<encoding encname="SUBS_rr_A1" />
|
|
<encoding encname="SUB_rr_A1" />
|
|
</encodings>
|
|
<orig>Is the type of shift to be applied to the second source register, encoded in "stype", where 00->LSL, 01->LSR, 10->ASR, 11->ROR.</orig>
|
|
<definition encodedin="stype">
|
|
<intro>Is the type of shift to be applied to the second source register, </intro>
|
|
<table class="valuetable">
|
|
<tgroup cols="2">
|
|
<thead>
|
|
<row>
|
|
<entry class="bitfield" bitwidth="2">stype</entry>
|
|
<entry class="symbol"><shift></entry>
|
|
</row>
|
|
</thead>
|
|
<tbody>
|
|
<row>
|
|
<entry class="bitfield">00</entry>
|
|
<entry class="symbol">LSL</entry>
|
|
</row>
|
|
<row>
|
|
<entry class="bitfield">01</entry>
|
|
<entry class="symbol">LSR</entry>
|
|
</row>
|
|
<row>
|
|
<entry class="bitfield">10</entry>
|
|
<entry class="symbol">ASR</entry>
|
|
</row>
|
|
<row>
|
|
<entry class="bitfield">11</entry>
|
|
<entry class="symbol">ROR</entry>
|
|
</row>
|
|
</tbody>
|
|
</tgroup>
|
|
</table>
|
|
</definition>
|
|
</account>
|
|
<account iclass="intdp2reg_immsh" symbol="<shift>" iclass_long="Integer Test and Compare (two register, immediate shift)">
|
|
<encodings>
|
|
<encoding encname="CMN_r_A1" />
|
|
<encoding encname="CMP_r_A1" />
|
|
<encoding encname="TEQ_r_A1" />
|
|
<encoding encname="TST_r_A1" />
|
|
</encodings>
|
|
<orig>Is the type of shift to be applied to the second source register, encoded in "stype", where 00->LSL, 01->LSR, 10->ASR, 11->ROR.</orig>
|
|
<definition encodedin="stype">
|
|
<intro>Is the type of shift to be applied to the second source register, </intro>
|
|
<table class="valuetable">
|
|
<tgroup cols="2">
|
|
<thead>
|
|
<row>
|
|
<entry class="bitfield" bitwidth="2">stype</entry>
|
|
<entry class="symbol"><shift></entry>
|
|
</row>
|
|
</thead>
|
|
<tbody>
|
|
<row>
|
|
<entry class="bitfield">00</entry>
|
|
<entry class="symbol">LSL</entry>
|
|
</row>
|
|
<row>
|
|
<entry class="bitfield">01</entry>
|
|
<entry class="symbol">LSR</entry>
|
|
</row>
|
|
<row>
|
|
<entry class="bitfield">10</entry>
|
|
<entry class="symbol">ASR</entry>
|
|
</row>
|
|
<row>
|
|
<entry class="bitfield">11</entry>
|
|
<entry class="symbol">ROR</entry>
|
|
</row>
|
|
</tbody>
|
|
</tgroup>
|
|
</table>
|
|
</definition>
|
|
</account>
|
|
<account iclass="intdp2reg_regsh" symbol="<type>" iclass_long="Integer Test and Compare (two register, register shift)">
|
|
<encodings>
|
|
<encoding encname="CMN_rr_A1" />
|
|
<encoding encname="CMP_rr_A1" />
|
|
<encoding encname="TEQ_rr_A1" />
|
|
<encoding encname="TST_rr_A1" />
|
|
</encodings>
|
|
<orig>Is the type of shift to be applied to the second source register, encoded in "stype", where 00->LSL, 01->LSR, 10->ASR, 11->ROR.</orig>
|
|
<definition encodedin="stype">
|
|
<intro>Is the type of shift to be applied to the second source register, </intro>
|
|
<table class="valuetable">
|
|
<tgroup cols="2">
|
|
<thead>
|
|
<row>
|
|
<entry class="bitfield" bitwidth="2">stype</entry>
|
|
<entry class="symbol"><type></entry>
|
|
</row>
|
|
</thead>
|
|
<tbody>
|
|
<row>
|
|
<entry class="bitfield">00</entry>
|
|
<entry class="symbol">LSL</entry>
|
|
</row>
|
|
<row>
|
|
<entry class="bitfield">01</entry>
|
|
<entry class="symbol">LSR</entry>
|
|
</row>
|
|
<row>
|
|
<entry class="bitfield">10</entry>
|
|
<entry class="symbol">ASR</entry>
|
|
</row>
|
|
<row>
|
|
<entry class="bitfield">11</entry>
|
|
<entry class="symbol">ROR</entry>
|
|
</row>
|
|
</tbody>
|
|
</tgroup>
|
|
</table>
|
|
</definition>
|
|
</account>
|
|
<account iclass="lddlit" symbol="+/-" iclass_long="Load dual (literal)">
|
|
<encodings>
|
|
<encoding encname="LDRD_l_T1" />
|
|
</encodings>
|
|
<orig>Specifies the offset is added to or subtracted from the base register, defaulting to + if omitted and encoded in the "U" field, where 0->-, 1->+.</orig>
|
|
<definition encodedin="U">
|
|
<intro>Specifies the offset is added to or subtracted from the base register, defaulting to + if omitted and </intro>
|
|
<table class="valuetable">
|
|
<tgroup cols="2">
|
|
<thead>
|
|
<row>
|
|
<entry class="bitfield" bitwidth="1">U</entry>
|
|
<entry class="symbol">+/-</entry>
|
|
</row>
|
|
</thead>
|
|
<tbody>
|
|
<row>
|
|
<entry class="bitfield">0</entry>
|
|
<entry class="symbol">-</entry>
|
|
</row>
|
|
<row>
|
|
<entry class="bitfield">1</entry>
|
|
<entry class="symbol">+</entry>
|
|
</row>
|
|
</tbody>
|
|
</tgroup>
|
|
</table>
|
|
</definition>
|
|
</account>
|
|
<account iclass="ldlit_signed" symbol="+/-" iclass_long="Load, signed (literal)">
|
|
<encodings>
|
|
<encoding encname="LDRSB_l_T1" />
|
|
<encoding encname="LDRSH_l_T1" />
|
|
<encoding encname="PLI_i_T3" />
|
|
</encodings>
|
|
<orig>Specifies the offset is added to or subtracted from the base register, defaulting to + if omitted and encoded in the "U" field, where 0->-, 1->+.</orig>
|
|
<definition encodedin="U">
|
|
<intro>Specifies the offset is added to or subtracted from the base register, defaulting to + if omitted and </intro>
|
|
<table class="valuetable">
|
|
<tgroup cols="2">
|
|
<thead>
|
|
<row>
|
|
<entry class="bitfield" bitwidth="1">U</entry>
|
|
<entry class="symbol">+/-</entry>
|
|
</row>
|
|
</thead>
|
|
<tbody>
|
|
<row>
|
|
<entry class="bitfield">0</entry>
|
|
<entry class="symbol">-</entry>
|
|
</row>
|
|
<row>
|
|
<entry class="bitfield">1</entry>
|
|
<entry class="symbol">+</entry>
|
|
</row>
|
|
</tbody>
|
|
</tgroup>
|
|
</table>
|
|
</definition>
|
|
</account>
|
|
<account iclass="ldlit_unsigned" symbol="+/-" iclass_long="Load, unsigned (literal)">
|
|
<encodings>
|
|
<encoding encname="LDRB_l_T1" />
|
|
<encoding encname="LDRH_l_T1" />
|
|
<encoding encname="LDR_l_T2" />
|
|
<encoding encname="PLD_l_T1" />
|
|
</encodings>
|
|
<orig>Specifies the offset is added to or subtracted from the base register, defaulting to + if omitted and encoded in the "U" field, where 0->-, 1->+.</orig>
|
|
<definition encodedin="U">
|
|
<intro>Specifies the offset is added to or subtracted from the base register, defaulting to + if omitted and </intro>
|
|
<table class="valuetable">
|
|
<tgroup cols="2">
|
|
<thead>
|
|
<row>
|
|
<entry class="bitfield" bitwidth="1">U</entry>
|
|
<entry class="symbol">+/-</entry>
|
|
</row>
|
|
</thead>
|
|
<tbody>
|
|
<row>
|
|
<entry class="bitfield">0</entry>
|
|
<entry class="symbol">-</entry>
|
|
</row>
|
|
<row>
|
|
<entry class="bitfield">1</entry>
|
|
<entry class="symbol">+</entry>
|
|
</row>
|
|
</tbody>
|
|
</tgroup>
|
|
</table>
|
|
</definition>
|
|
</account>
|
|
<account iclass="ldstximm" symbol="+/-" iclass_long="Load/Store Dual, Half, Signed Byte (immediate, literal)">
|
|
<encodings>
|
|
<encoding encname="LDRD_i_A1_off" />
|
|
<encoding encname="LDRD_i_A1_post" />
|
|
<encoding encname="LDRD_i_A1_pre" />
|
|
<encoding encname="LDRD_l_A1" />
|
|
<encoding encname="LDRHT_A1" />
|
|
<encoding encname="LDRH_i_A1_off" />
|
|
<encoding encname="LDRH_i_A1_post" />
|
|
<encoding encname="LDRH_i_A1_pre" />
|
|
<encoding encname="LDRH_l_A1" />
|
|
<encoding encname="LDRSBT_A1" />
|
|
<encoding encname="LDRSB_i_A1_off" />
|
|
<encoding encname="LDRSB_i_A1_post" />
|
|
<encoding encname="LDRSB_i_A1_pre" />
|
|
<encoding encname="LDRSB_l_A1" />
|
|
<encoding encname="LDRSHT_A1" />
|
|
<encoding encname="LDRSH_i_A1_off" />
|
|
<encoding encname="LDRSH_i_A1_post" />
|
|
<encoding encname="LDRSH_i_A1_pre" />
|
|
<encoding encname="LDRSH_l_A1" />
|
|
<encoding encname="STRD_i_A1_off" />
|
|
<encoding encname="STRD_i_A1_post" />
|
|
<encoding encname="STRD_i_A1_pre" />
|
|
<encoding encname="STRHT_A1" />
|
|
<encoding encname="STRH_i_A1_off" />
|
|
<encoding encname="STRH_i_A1_post" />
|
|
<encoding encname="STRH_i_A1_pre" />
|
|
</encodings>
|
|
<orig>Specifies the offset is added to or subtracted from the base register, defaulting to + if omitted and encoded in the "U" field, where 0->-, 1->+.</orig>
|
|
<definition encodedin="U">
|
|
<intro>Specifies the offset is added to or subtracted from the base register, defaulting to + if omitted and </intro>
|
|
<table class="valuetable">
|
|
<tgroup cols="2">
|
|
<thead>
|
|
<row>
|
|
<entry class="bitfield" bitwidth="1">U</entry>
|
|
<entry class="symbol">+/-</entry>
|
|
</row>
|
|
</thead>
|
|
<tbody>
|
|
<row>
|
|
<entry class="bitfield">0</entry>
|
|
<entry class="symbol">-</entry>
|
|
</row>
|
|
<row>
|
|
<entry class="bitfield">1</entry>
|
|
<entry class="symbol">+</entry>
|
|
</row>
|
|
</tbody>
|
|
</tgroup>
|
|
</table>
|
|
</definition>
|
|
</account>
|
|
<account iclass="ldstxreg" symbol="+/-" iclass_long="Load/Store Dual, Half, Signed Byte (register)">
|
|
<encodings>
|
|
<encoding encname="LDRD_r_A1_off" />
|
|
<encoding encname="LDRD_r_A1_post" />
|
|
<encoding encname="LDRD_r_A1_pre" />
|
|
<encoding encname="LDRHT_A2" />
|
|
<encoding encname="LDRH_r_A1_off" />
|
|
<encoding encname="LDRH_r_A1_post" />
|
|
<encoding encname="LDRH_r_A1_pre" />
|
|
<encoding encname="LDRSBT_A2" />
|
|
<encoding encname="LDRSB_r_A1_off" />
|
|
<encoding encname="LDRSB_r_A1_post" />
|
|
<encoding encname="LDRSB_r_A1_pre" />
|
|
<encoding encname="LDRSHT_A2" />
|
|
<encoding encname="LDRSH_r_A1_off" />
|
|
<encoding encname="LDRSH_r_A1_post" />
|
|
<encoding encname="LDRSH_r_A1_pre" />
|
|
<encoding encname="STRD_r_A1_off" />
|
|
<encoding encname="STRD_r_A1_post" />
|
|
<encoding encname="STRD_r_A1_pre" />
|
|
<encoding encname="STRHT_A2" />
|
|
<encoding encname="STRH_r_A1_off" />
|
|
<encoding encname="STRH_r_A1_post" />
|
|
<encoding encname="STRH_r_A1_pre" />
|
|
</encodings>
|
|
<orig>Specifies the index register is added to or subtracted from the base register, defaulting to + if omitted and encoded in the "U" field, where 0->-, 1->+.</orig>
|
|
<definition encodedin="U">
|
|
<intro>Specifies the index register is added to or subtracted from the base register, defaulting to + if omitted and </intro>
|
|
<table class="valuetable">
|
|
<tgroup cols="2">
|
|
<thead>
|
|
<row>
|
|
<entry class="bitfield" bitwidth="1">U</entry>
|
|
<entry class="symbol">+/-</entry>
|
|
</row>
|
|
</thead>
|
|
<tbody>
|
|
<row>
|
|
<entry class="bitfield">0</entry>
|
|
<entry class="symbol">-</entry>
|
|
</row>
|
|
<row>
|
|
<entry class="bitfield">1</entry>
|
|
<entry class="symbol">+</entry>
|
|
</row>
|
|
</tbody>
|
|
</tgroup>
|
|
</table>
|
|
</definition>
|
|
</account>
|
|
<account iclass="ldstimm" symbol="+/-" iclass_long="Load/Store Word, Unsigned Byte (immediate, literal)">
|
|
<encodings>
|
|
<encoding encname="LDRBT_A1" />
|
|
<encoding encname="LDRB_i_A1_off" />
|
|
<encoding encname="LDRB_i_A1_post" />
|
|
<encoding encname="LDRB_i_A1_pre" />
|
|
<encoding encname="LDRB_l_A1" />
|
|
<encoding encname="LDRT_A1" />
|
|
<encoding encname="LDR_i_A1_off" />
|
|
<encoding encname="LDR_i_A1_post" />
|
|
<encoding encname="LDR_i_A1_pre" />
|
|
<encoding encname="LDR_l_A1" />
|
|
<encoding encname="STRBT_A1" />
|
|
<encoding encname="STRB_i_A1_off" />
|
|
<encoding encname="STRB_i_A1_post" />
|
|
<encoding encname="STRB_i_A1_pre" />
|
|
<encoding encname="STRT_A1" />
|
|
<encoding encname="STR_i_A1_off" />
|
|
<encoding encname="STR_i_A1_post" />
|
|
<encoding encname="STR_i_A1_pre" />
|
|
</encodings>
|
|
<orig>Specifies the offset is added to or subtracted from the base register, defaulting to + if omitted and encoded in the "U" field, where 0->-, 1->+.</orig>
|
|
<definition encodedin="U">
|
|
<intro>Specifies the offset is added to or subtracted from the base register, defaulting to + if omitted and </intro>
|
|
<table class="valuetable">
|
|
<tgroup cols="2">
|
|
<thead>
|
|
<row>
|
|
<entry class="bitfield" bitwidth="1">U</entry>
|
|
<entry class="symbol">+/-</entry>
|
|
</row>
|
|
</thead>
|
|
<tbody>
|
|
<row>
|
|
<entry class="bitfield">0</entry>
|
|
<entry class="symbol">-</entry>
|
|
</row>
|
|
<row>
|
|
<entry class="bitfield">1</entry>
|
|
<entry class="symbol">+</entry>
|
|
</row>
|
|
</tbody>
|
|
</tgroup>
|
|
</table>
|
|
</definition>
|
|
</account>
|
|
<account iclass="ldstreg" symbol="+/-" iclass_long="Load/Store Word, Unsigned Byte (register)">
|
|
<encodings>
|
|
<encoding encname="LDRBT_A2" />
|
|
<encoding encname="LDRB_r_A1_off" />
|
|
<encoding encname="LDRB_r_A1_post" />
|
|
<encoding encname="LDRB_r_A1_pre" />
|
|
<encoding encname="LDRT_A2" />
|
|
<encoding encname="LDR_r_A1_off" />
|
|
<encoding encname="LDR_r_A1_post" />
|
|
<encoding encname="LDR_r_A1_pre" />
|
|
<encoding encname="STRBT_A2" />
|
|
<encoding encname="STRB_r_A1_off" />
|
|
<encoding encname="STRB_r_A1_post" />
|
|
<encoding encname="STRB_r_A1_pre" />
|
|
<encoding encname="STRT_A2" />
|
|
<encoding encname="STR_r_A1_off" />
|
|
<encoding encname="STR_r_A1_post" />
|
|
<encoding encname="STR_r_A1_pre" />
|
|
</encodings>
|
|
<orig>Specifies the index register is added to or subtracted from the base register, defaulting to + if omitted and encoded in the "U" field, where 0->-, 1->+.</orig>
|
|
<definition encodedin="U">
|
|
<intro>Specifies the index register is added to or subtracted from the base register, defaulting to + if omitted and </intro>
|
|
<table class="valuetable">
|
|
<tgroup cols="2">
|
|
<thead>
|
|
<row>
|
|
<entry class="bitfield" bitwidth="1">U</entry>
|
|
<entry class="symbol">+/-</entry>
|
|
</row>
|
|
</thead>
|
|
<tbody>
|
|
<row>
|
|
<entry class="bitfield">0</entry>
|
|
<entry class="symbol">-</entry>
|
|
</row>
|
|
<row>
|
|
<entry class="bitfield">1</entry>
|
|
<entry class="symbol">+</entry>
|
|
</row>
|
|
</tbody>
|
|
</tgroup>
|
|
</table>
|
|
</definition>
|
|
</account>
|
|
<account iclass="ldstd_imm" symbol="+/-" iclass_long="Load/store dual (immediate)">
|
|
<encodings>
|
|
<encoding encname="LDRD_i_T1_off" />
|
|
<encoding encname="STRD_i_T1_off" />
|
|
</encodings>
|
|
<orig>Specifies the offset is added to or subtracted from the base register, defaulting to + if omitted and encoded in the "U" field, where 0->-, 1->+.</orig>
|
|
<definition encodedin="U">
|
|
<intro>Specifies the offset is added to or subtracted from the base register, defaulting to + if omitted and </intro>
|
|
<table class="valuetable">
|
|
<tgroup cols="2">
|
|
<thead>
|
|
<row>
|
|
<entry class="bitfield" bitwidth="1">U</entry>
|
|
<entry class="symbol">+/-</entry>
|
|
</row>
|
|
</thead>
|
|
<tbody>
|
|
<row>
|
|
<entry class="bitfield">0</entry>
|
|
<entry class="symbol">-</entry>
|
|
</row>
|
|
<row>
|
|
<entry class="bitfield">1</entry>
|
|
<entry class="symbol">+</entry>
|
|
</row>
|
|
</tbody>
|
|
</tgroup>
|
|
</table>
|
|
</definition>
|
|
</account>
|
|
<account iclass="ldstd_post" symbol="+/-" iclass_long="Load/store dual (immediate, post-indexed)">
|
|
<encodings>
|
|
<encoding encname="LDRD_i_T1_post" />
|
|
<encoding encname="STRD_i_T1_post" />
|
|
</encodings>
|
|
<orig>Specifies the offset is added to or subtracted from the base register, defaulting to + if omitted and encoded in the "U" field, where 0->-, 1->+.</orig>
|
|
<definition encodedin="U">
|
|
<intro>Specifies the offset is added to or subtracted from the base register, defaulting to + if omitted and </intro>
|
|
<table class="valuetable">
|
|
<tgroup cols="2">
|
|
<thead>
|
|
<row>
|
|
<entry class="bitfield" bitwidth="1">U</entry>
|
|
<entry class="symbol">+/-</entry>
|
|
</row>
|
|
</thead>
|
|
<tbody>
|
|
<row>
|
|
<entry class="bitfield">0</entry>
|
|
<entry class="symbol">-</entry>
|
|
</row>
|
|
<row>
|
|
<entry class="bitfield">1</entry>
|
|
<entry class="symbol">+</entry>
|
|
</row>
|
|
</tbody>
|
|
</tgroup>
|
|
</table>
|
|
</definition>
|
|
</account>
|
|
<account iclass="ldstd_pre" symbol="+/-" iclass_long="Load/store dual (immediate, pre-indexed)">
|
|
<encodings>
|
|
<encoding encname="LDRD_i_T1_pre" />
|
|
<encoding encname="STRD_i_T1_pre" />
|
|
</encodings>
|
|
<orig>Specifies the offset is added to or subtracted from the base register, defaulting to + if omitted and encoded in the "U" field, where 0->-, 1->+.</orig>
|
|
<definition encodedin="U">
|
|
<intro>Specifies the offset is added to or subtracted from the base register, defaulting to + if omitted and </intro>
|
|
<table class="valuetable">
|
|
<tgroup cols="2">
|
|
<thead>
|
|
<row>
|
|
<entry class="bitfield" bitwidth="1">U</entry>
|
|
<entry class="symbol">+/-</entry>
|
|
</row>
|
|
</thead>
|
|
<tbody>
|
|
<row>
|
|
<entry class="bitfield">0</entry>
|
|
<entry class="symbol">-</entry>
|
|
</row>
|
|
<row>
|
|
<entry class="bitfield">1</entry>
|
|
<entry class="symbol">+</entry>
|
|
</row>
|
|
</tbody>
|
|
</tgroup>
|
|
</table>
|
|
</definition>
|
|
</account>
|
|
<account iclass="ldst_signed_post" symbol="+/-" iclass_long="Load/store, signed (immediate, post-indexed)">
|
|
<encodings>
|
|
<encoding encname="LDRSB_i_T2_post" />
|
|
<encoding encname="LDRSH_i_T2_post" />
|
|
</encodings>
|
|
<orig>Specifies the offset is added to or subtracted from the base register, defaulting to + if omitted and encoded in the "U" field, where 0->-, 1->+.</orig>
|
|
<definition encodedin="U">
|
|
<intro>Specifies the offset is added to or subtracted from the base register, defaulting to + if omitted and </intro>
|
|
<table class="valuetable">
|
|
<tgroup cols="2">
|
|
<thead>
|
|
<row>
|
|
<entry class="bitfield" bitwidth="1">U</entry>
|
|
<entry class="symbol">+/-</entry>
|
|
</row>
|
|
</thead>
|
|
<tbody>
|
|
<row>
|
|
<entry class="bitfield">0</entry>
|
|
<entry class="symbol">-</entry>
|
|
</row>
|
|
<row>
|
|
<entry class="bitfield">1</entry>
|
|
<entry class="symbol">+</entry>
|
|
</row>
|
|
</tbody>
|
|
</tgroup>
|
|
</table>
|
|
</definition>
|
|
</account>
|
|
<account iclass="ldst_signed_pre" symbol="+/-" iclass_long="Load/store, signed (immediate, pre-indexed)">
|
|
<encodings>
|
|
<encoding encname="LDRSB_i_T2_pre" />
|
|
<encoding encname="LDRSH_i_T2_pre" />
|
|
</encodings>
|
|
<orig>Specifies the offset is added to or subtracted from the base register, defaulting to + if omitted and encoded in the "U" field, where 0->-, 1->+.</orig>
|
|
<definition encodedin="U">
|
|
<intro>Specifies the offset is added to or subtracted from the base register, defaulting to + if omitted and </intro>
|
|
<table class="valuetable">
|
|
<tgroup cols="2">
|
|
<thead>
|
|
<row>
|
|
<entry class="bitfield" bitwidth="1">U</entry>
|
|
<entry class="symbol">+/-</entry>
|
|
</row>
|
|
</thead>
|
|
<tbody>
|
|
<row>
|
|
<entry class="bitfield">0</entry>
|
|
<entry class="symbol">-</entry>
|
|
</row>
|
|
<row>
|
|
<entry class="bitfield">1</entry>
|
|
<entry class="symbol">+</entry>
|
|
</row>
|
|
</tbody>
|
|
</tgroup>
|
|
</table>
|
|
</definition>
|
|
</account>
|
|
<account iclass="ldst_unsigned_post" symbol="+/-" iclass_long="Load/store, unsigned (immediate, post-indexed)">
|
|
<encodings>
|
|
<encoding encname="LDRB_i_T3_post" />
|
|
<encoding encname="LDRH_i_T3_post" />
|
|
<encoding encname="LDR_i_T4_post" />
|
|
<encoding encname="STRB_i_T3_post" />
|
|
<encoding encname="STRH_i_T3_post" />
|
|
<encoding encname="STR_i_T4_post" />
|
|
</encodings>
|
|
<orig>Specifies the offset is added to or subtracted from the base register, defaulting to + if omitted and encoded in the "U" field, where 0->-, 1->+.</orig>
|
|
<definition encodedin="U">
|
|
<intro>Specifies the offset is added to or subtracted from the base register, defaulting to + if omitted and </intro>
|
|
<table class="valuetable">
|
|
<tgroup cols="2">
|
|
<thead>
|
|
<row>
|
|
<entry class="bitfield" bitwidth="1">U</entry>
|
|
<entry class="symbol">+/-</entry>
|
|
</row>
|
|
</thead>
|
|
<tbody>
|
|
<row>
|
|
<entry class="bitfield">0</entry>
|
|
<entry class="symbol">-</entry>
|
|
</row>
|
|
<row>
|
|
<entry class="bitfield">1</entry>
|
|
<entry class="symbol">+</entry>
|
|
</row>
|
|
</tbody>
|
|
</tgroup>
|
|
</table>
|
|
</definition>
|
|
</account>
|
|
<account iclass="ldst_unsigned_pre" symbol="+/-" iclass_long="Load/store, unsigned (immediate, pre-indexed)">
|
|
<encodings>
|
|
<encoding encname="LDRB_i_T3_pre" />
|
|
<encoding encname="LDRH_i_T3_pre" />
|
|
<encoding encname="LDR_i_T4_pre" />
|
|
<encoding encname="STRB_i_T3_pre" />
|
|
<encoding encname="STRH_i_T3_pre" />
|
|
<encoding encname="STR_i_T4_pre" />
|
|
</encodings>
|
|
<orig>Specifies the offset is added to or subtracted from the base register, defaulting to + if omitted and encoded in the "U" field, where 0->-, 1->+.</orig>
|
|
<definition encodedin="U">
|
|
<intro>Specifies the offset is added to or subtracted from the base register, defaulting to + if omitted and </intro>
|
|
<table class="valuetable">
|
|
<tgroup cols="2">
|
|
<thead>
|
|
<row>
|
|
<entry class="bitfield" bitwidth="1">U</entry>
|
|
<entry class="symbol">+/-</entry>
|
|
</row>
|
|
</thead>
|
|
<tbody>
|
|
<row>
|
|
<entry class="bitfield">0</entry>
|
|
<entry class="symbol">-</entry>
|
|
</row>
|
|
<row>
|
|
<entry class="bitfield">1</entry>
|
|
<entry class="symbol">+</entry>
|
|
</row>
|
|
</tbody>
|
|
</tgroup>
|
|
</table>
|
|
</definition>
|
|
</account>
|
|
<account iclass="logic3reg_immsh" symbol="<shift>" iclass_long="Logical Arithmetic (three register, immediate shift)">
|
|
<encodings>
|
|
<encoding encname="BICS_r_A1" />
|
|
<encoding encname="BIC_r_A1" />
|
|
<encoding encname="ORRS_r_A1" />
|
|
<encoding encname="ORR_r_A1" />
|
|
</encodings>
|
|
<orig>Is the type of shift to be applied to the second source register, encoded in "stype", where 00->LSL, 01->LSR, 10->ASR, 11->ROR.</orig>
|
|
<definition encodedin="stype">
|
|
<intro>Is the type of shift to be applied to the second source register, </intro>
|
|
<table class="valuetable">
|
|
<tgroup cols="2">
|
|
<thead>
|
|
<row>
|
|
<entry class="bitfield" bitwidth="2">stype</entry>
|
|
<entry class="symbol"><shift></entry>
|
|
</row>
|
|
</thead>
|
|
<tbody>
|
|
<row>
|
|
<entry class="bitfield">00</entry>
|
|
<entry class="symbol">LSL</entry>
|
|
</row>
|
|
<row>
|
|
<entry class="bitfield">01</entry>
|
|
<entry class="symbol">LSR</entry>
|
|
</row>
|
|
<row>
|
|
<entry class="bitfield">10</entry>
|
|
<entry class="symbol">ASR</entry>
|
|
</row>
|
|
<row>
|
|
<entry class="bitfield">11</entry>
|
|
<entry class="symbol">ROR</entry>
|
|
</row>
|
|
</tbody>
|
|
</tgroup>
|
|
</table>
|
|
</definition>
|
|
</account>
|
|
<account iclass="logic3reg_immsh" symbol="<shift>" iclass_long="Logical Arithmetic (three register, immediate shift)">
|
|
<encodings>
|
|
<encoding encname="MOVS_r_A1" />
|
|
<encoding encname="MOV_r_A1" />
|
|
<encoding encname="MVNS_r_A1" />
|
|
<encoding encname="MVN_r_A1" />
|
|
</encodings>
|
|
<orig>Is the type of shift to be applied to the source register, encoded in "stype", where 00->LSL, 01->LSR, 10->ASR, 11->ROR.</orig>
|
|
<definition encodedin="stype">
|
|
<intro>Is the type of shift to be applied to the source register, </intro>
|
|
<table class="valuetable">
|
|
<tgroup cols="2">
|
|
<thead>
|
|
<row>
|
|
<entry class="bitfield" bitwidth="2">stype</entry>
|
|
<entry class="symbol"><shift></entry>
|
|
</row>
|
|
</thead>
|
|
<tbody>
|
|
<row>
|
|
<entry class="bitfield">00</entry>
|
|
<entry class="symbol">LSL</entry>
|
|
</row>
|
|
<row>
|
|
<entry class="bitfield">01</entry>
|
|
<entry class="symbol">LSR</entry>
|
|
</row>
|
|
<row>
|
|
<entry class="bitfield">10</entry>
|
|
<entry class="symbol">ASR</entry>
|
|
</row>
|
|
<row>
|
|
<entry class="bitfield">11</entry>
|
|
<entry class="symbol">ROR</entry>
|
|
</row>
|
|
</tbody>
|
|
</tgroup>
|
|
</table>
|
|
</definition>
|
|
</account>
|
|
<account iclass="logic3reg_regsh" symbol="<shift>" iclass_long="Logical Arithmetic (three register, register shift)">
|
|
<encodings>
|
|
<encoding encname="BICS_rr_A1" />
|
|
<encoding encname="BIC_rr_A1" />
|
|
<encoding encname="MOVS_rr_A1" />
|
|
<encoding encname="MOV_rr_A1" />
|
|
<encoding encname="MVNS_rr_A1" />
|
|
<encoding encname="MVN_rr_A1" />
|
|
<encoding encname="ORRS_rr_A1" />
|
|
<encoding encname="ORR_rr_A1" />
|
|
</encodings>
|
|
<orig>Is the type of shift to be applied to the second source register, encoded in "stype", where 00->LSL, 01->LSR, 10->ASR, 11->ROR.</orig>
|
|
<definition encodedin="stype">
|
|
<intro>Is the type of shift to be applied to the second source register, </intro>
|
|
<table class="valuetable">
|
|
<tgroup cols="2">
|
|
<thead>
|
|
<row>
|
|
<entry class="bitfield" bitwidth="2">stype</entry>
|
|
<entry class="symbol"><shift></entry>
|
|
</row>
|
|
</thead>
|
|
<tbody>
|
|
<row>
|
|
<entry class="bitfield">00</entry>
|
|
<entry class="symbol">LSL</entry>
|
|
</row>
|
|
<row>
|
|
<entry class="bitfield">01</entry>
|
|
<entry class="symbol">LSR</entry>
|
|
</row>
|
|
<row>
|
|
<entry class="bitfield">10</entry>
|
|
<entry class="symbol">ASR</entry>
|
|
</row>
|
|
<row>
|
|
<entry class="bitfield">11</entry>
|
|
<entry class="symbol">ROR</entry>
|
|
</row>
|
|
</tbody>
|
|
</tgroup>
|
|
</table>
|
|
</definition>
|
|
</account>
|
|
<account iclass="mrs_bank" symbol="<banked_reg>" iclass_long="MRS (banked)">
|
|
<encodings>
|
|
<encoding encname="MRS_br_T1_AS" />
|
|
</encodings>
|
|
<orig>Is the name of the banked register to be transferred to or from, encoded in the "R:M:M1" field, where 000000->R8_usr, 000001->R9_usr, 000010->R10_usr, 000011->R11_usr, 000100->R12_usr, 000101->SP_usr, 000110->LR_usr, 001000->R8_fiq, 001001->R9_fiq, 001010->R10_fiq, 001011->R11_fiq, 001100->R12_fiq, 001101->SP_fiq, 001110->LR_fiq, 010000->LR_irq, 010001->SP_irq, 010010->LR_svc, 010011->SP_svc, 010100->LR_abt, 010101->SP_abt, 010110->LR_und, 010111->SP_und, 011100->LR_mon, 011101->SP_mon, 011110->ELR_hyp, 011111->SP_hyp, 101110->SPSR_fiq, 110000->SPSR_irq, 110010->SPSR_svc, 110100->SPSR_abt, 110110->SPSR_und, 111100->SPSR_mon, 111110->SPSR_hyp, otherwise UNPREDICTABLE</orig>
|
|
<definition encodedin="R:M:M1">
|
|
<intro>Is the name of the banked register to be transferred to or from, </intro>
|
|
<table class="valuetable">
|
|
<tgroup cols="4">
|
|
<thead>
|
|
<row>
|
|
<entry class="bitfield" bitwidth="1">R</entry>
|
|
<entry class="bitfield" bitwidth="1">M</entry>
|
|
<entry class="bitfield" bitwidth="4">M1</entry>
|
|
<entry class="symbol"><banked_reg></entry>
|
|
</row>
|
|
</thead>
|
|
<tbody>
|
|
<row>
|
|
<entry class="bitfield">0</entry>
|
|
<entry class="bitfield">0</entry>
|
|
<entry class="bitfield">0000</entry>
|
|
<entry class="symbol">R8_usr</entry>
|
|
</row>
|
|
<row>
|
|
<entry class="bitfield">0</entry>
|
|
<entry class="bitfield">0</entry>
|
|
<entry class="bitfield">0001</entry>
|
|
<entry class="symbol">R9_usr</entry>
|
|
</row>
|
|
<row>
|
|
<entry class="bitfield">0</entry>
|
|
<entry class="bitfield">0</entry>
|
|
<entry class="bitfield">0010</entry>
|
|
<entry class="symbol">R10_usr</entry>
|
|
</row>
|
|
<row>
|
|
<entry class="bitfield">0</entry>
|
|
<entry class="bitfield">0</entry>
|
|
<entry class="bitfield">0011</entry>
|
|
<entry class="symbol">R11_usr</entry>
|
|
</row>
|
|
<row>
|
|
<entry class="bitfield">0</entry>
|
|
<entry class="bitfield">0</entry>
|
|
<entry class="bitfield">0100</entry>
|
|
<entry class="symbol">R12_usr</entry>
|
|
</row>
|
|
<row>
|
|
<entry class="bitfield">0</entry>
|
|
<entry class="bitfield">0</entry>
|
|
<entry class="bitfield">0101</entry>
|
|
<entry class="symbol">SP_usr</entry>
|
|
</row>
|
|
<row>
|
|
<entry class="bitfield">0</entry>
|
|
<entry class="bitfield">0</entry>
|
|
<entry class="bitfield">0110</entry>
|
|
<entry class="symbol">LR_usr</entry>
|
|
</row>
|
|
<row>
|
|
<entry class="bitfield">0</entry>
|
|
<entry class="bitfield">0</entry>
|
|
<entry class="bitfield">0111</entry>
|
|
<entry class="symbol">UNPREDICTABLE</entry>
|
|
</row>
|
|
<row>
|
|
<entry class="bitfield">0</entry>
|
|
<entry class="bitfield">0</entry>
|
|
<entry class="bitfield">1000</entry>
|
|
<entry class="symbol">R8_fiq</entry>
|
|
</row>
|
|
<row>
|
|
<entry class="bitfield">0</entry>
|
|
<entry class="bitfield">0</entry>
|
|
<entry class="bitfield">1001</entry>
|
|
<entry class="symbol">R9_fiq</entry>
|
|
</row>
|
|
<row>
|
|
<entry class="bitfield">0</entry>
|
|
<entry class="bitfield">0</entry>
|
|
<entry class="bitfield">1010</entry>
|
|
<entry class="symbol">R10_fiq</entry>
|
|
</row>
|
|
<row>
|
|
<entry class="bitfield">0</entry>
|
|
<entry class="bitfield">0</entry>
|
|
<entry class="bitfield">1011</entry>
|
|
<entry class="symbol">R11_fiq</entry>
|
|
</row>
|
|
<row>
|
|
<entry class="bitfield">0</entry>
|
|
<entry class="bitfield">0</entry>
|
|
<entry class="bitfield">1100</entry>
|
|
<entry class="symbol">R12_fiq</entry>
|
|
</row>
|
|
<row>
|
|
<entry class="bitfield">0</entry>
|
|
<entry class="bitfield">0</entry>
|
|
<entry class="bitfield">1101</entry>
|
|
<entry class="symbol">SP_fiq</entry>
|
|
</row>
|
|
<row>
|
|
<entry class="bitfield">0</entry>
|
|
<entry class="bitfield">0</entry>
|
|
<entry class="bitfield">1110</entry>
|
|
<entry class="symbol">LR_fiq</entry>
|
|
</row>
|
|
<row>
|
|
<entry class="bitfield">0</entry>
|
|
<entry class="bitfield">0</entry>
|
|
<entry class="bitfield">1111</entry>
|
|
<entry class="symbol">UNPREDICTABLE</entry>
|
|
</row>
|
|
<row>
|
|
<entry class="bitfield">0</entry>
|
|
<entry class="bitfield">1</entry>
|
|
<entry class="bitfield">0000</entry>
|
|
<entry class="symbol">LR_irq</entry>
|
|
</row>
|
|
<row>
|
|
<entry class="bitfield">0</entry>
|
|
<entry class="bitfield">1</entry>
|
|
<entry class="bitfield">0001</entry>
|
|
<entry class="symbol">SP_irq</entry>
|
|
</row>
|
|
<row>
|
|
<entry class="bitfield">0</entry>
|
|
<entry class="bitfield">1</entry>
|
|
<entry class="bitfield">0010</entry>
|
|
<entry class="symbol">LR_svc</entry>
|
|
</row>
|
|
<row>
|
|
<entry class="bitfield">0</entry>
|
|
<entry class="bitfield">1</entry>
|
|
<entry class="bitfield">0011</entry>
|
|
<entry class="symbol">SP_svc</entry>
|
|
</row>
|
|
<row>
|
|
<entry class="bitfield">0</entry>
|
|
<entry class="bitfield">1</entry>
|
|
<entry class="bitfield">0100</entry>
|
|
<entry class="symbol">LR_abt</entry>
|
|
</row>
|
|
<row>
|
|
<entry class="bitfield">0</entry>
|
|
<entry class="bitfield">1</entry>
|
|
<entry class="bitfield">0101</entry>
|
|
<entry class="symbol">SP_abt</entry>
|
|
</row>
|
|
<row>
|
|
<entry class="bitfield">0</entry>
|
|
<entry class="bitfield">1</entry>
|
|
<entry class="bitfield">0110</entry>
|
|
<entry class="symbol">LR_und</entry>
|
|
</row>
|
|
<row>
|
|
<entry class="bitfield">0</entry>
|
|
<entry class="bitfield">1</entry>
|
|
<entry class="bitfield">0111</entry>
|
|
<entry class="symbol">SP_und</entry>
|
|
</row>
|
|
<row>
|
|
<entry class="bitfield">0</entry>
|
|
<entry class="bitfield">1</entry>
|
|
<entry class="bitfield">10xx</entry>
|
|
<entry class="symbol">UNPREDICTABLE</entry>
|
|
</row>
|
|
<row>
|
|
<entry class="bitfield">0</entry>
|
|
<entry class="bitfield">1</entry>
|
|
<entry class="bitfield">1100</entry>
|
|
<entry class="symbol">LR_mon</entry>
|
|
</row>
|
|
<row>
|
|
<entry class="bitfield">0</entry>
|
|
<entry class="bitfield">1</entry>
|
|
<entry class="bitfield">1101</entry>
|
|
<entry class="symbol">SP_mon</entry>
|
|
</row>
|
|
<row>
|
|
<entry class="bitfield">0</entry>
|
|
<entry class="bitfield">1</entry>
|
|
<entry class="bitfield">1110</entry>
|
|
<entry class="symbol">ELR_hyp</entry>
|
|
</row>
|
|
<row>
|
|
<entry class="bitfield">0</entry>
|
|
<entry class="bitfield">1</entry>
|
|
<entry class="bitfield">1111</entry>
|
|
<entry class="symbol">SP_hyp</entry>
|
|
</row>
|
|
<row>
|
|
<entry class="bitfield">1</entry>
|
|
<entry class="bitfield">0</entry>
|
|
<entry class="bitfield">0xxx</entry>
|
|
<entry class="symbol">UNPREDICTABLE</entry>
|
|
</row>
|
|
<row>
|
|
<entry class="bitfield">1</entry>
|
|
<entry class="bitfield">0</entry>
|
|
<entry class="bitfield">10xx</entry>
|
|
<entry class="symbol">UNPREDICTABLE</entry>
|
|
</row>
|
|
<row>
|
|
<entry class="bitfield">1</entry>
|
|
<entry class="bitfield">0</entry>
|
|
<entry class="bitfield">110x</entry>
|
|
<entry class="symbol">UNPREDICTABLE</entry>
|
|
</row>
|
|
<row>
|
|
<entry class="bitfield">1</entry>
|
|
<entry class="bitfield">0</entry>
|
|
<entry class="bitfield">1110</entry>
|
|
<entry class="symbol">SPSR_fiq</entry>
|
|
</row>
|
|
<row>
|
|
<entry class="bitfield">1</entry>
|
|
<entry class="bitfield">0</entry>
|
|
<entry class="bitfield">1111</entry>
|
|
<entry class="symbol">UNPREDICTABLE</entry>
|
|
</row>
|
|
<row>
|
|
<entry class="bitfield">1</entry>
|
|
<entry class="bitfield">1</entry>
|
|
<entry class="bitfield">0000</entry>
|
|
<entry class="symbol">SPSR_irq</entry>
|
|
</row>
|
|
<row>
|
|
<entry class="bitfield">1</entry>
|
|
<entry class="bitfield">1</entry>
|
|
<entry class="bitfield">0001</entry>
|
|
<entry class="symbol">UNPREDICTABLE</entry>
|
|
</row>
|
|
<row>
|
|
<entry class="bitfield">1</entry>
|
|
<entry class="bitfield">1</entry>
|
|
<entry class="bitfield">0010</entry>
|
|
<entry class="symbol">SPSR_svc</entry>
|
|
</row>
|
|
<row>
|
|
<entry class="bitfield">1</entry>
|
|
<entry class="bitfield">1</entry>
|
|
<entry class="bitfield">0011</entry>
|
|
<entry class="symbol">UNPREDICTABLE</entry>
|
|
</row>
|
|
<row>
|
|
<entry class="bitfield">1</entry>
|
|
<entry class="bitfield">1</entry>
|
|
<entry class="bitfield">0100</entry>
|
|
<entry class="symbol">SPSR_abt</entry>
|
|
</row>
|
|
<row>
|
|
<entry class="bitfield">1</entry>
|
|
<entry class="bitfield">1</entry>
|
|
<entry class="bitfield">0101</entry>
|
|
<entry class="symbol">UNPREDICTABLE</entry>
|
|
</row>
|
|
<row>
|
|
<entry class="bitfield">1</entry>
|
|
<entry class="bitfield">1</entry>
|
|
<entry class="bitfield">0110</entry>
|
|
<entry class="symbol">SPSR_und</entry>
|
|
</row>
|
|
<row>
|
|
<entry class="bitfield">1</entry>
|
|
<entry class="bitfield">1</entry>
|
|
<entry class="bitfield">0111</entry>
|
|
<entry class="symbol">UNPREDICTABLE</entry>
|
|
</row>
|
|
<row>
|
|
<entry class="bitfield">1</entry>
|
|
<entry class="bitfield">1</entry>
|
|
<entry class="bitfield">10xx</entry>
|
|
<entry class="symbol">UNPREDICTABLE</entry>
|
|
</row>
|
|
<row>
|
|
<entry class="bitfield">1</entry>
|
|
<entry class="bitfield">1</entry>
|
|
<entry class="bitfield">1100</entry>
|
|
<entry class="symbol">SPSR_mon</entry>
|
|
</row>
|
|
<row>
|
|
<entry class="bitfield">1</entry>
|
|
<entry class="bitfield">1</entry>
|
|
<entry class="bitfield">1101</entry>
|
|
<entry class="symbol">UNPREDICTABLE</entry>
|
|
</row>
|
|
<row>
|
|
<entry class="bitfield">1</entry>
|
|
<entry class="bitfield">1</entry>
|
|
<entry class="bitfield">1110</entry>
|
|
<entry class="symbol">SPSR_hyp</entry>
|
|
</row>
|
|
<row>
|
|
<entry class="bitfield">1</entry>
|
|
<entry class="bitfield">1</entry>
|
|
<entry class="bitfield">1111</entry>
|
|
<entry class="symbol">UNPREDICTABLE</entry>
|
|
</row>
|
|
</tbody>
|
|
</tgroup>
|
|
</table>
|
|
</definition>
|
|
</account>
|
|
<account iclass="mrs_spec" symbol="<spec_reg>" iclass_long="MRS (special)">
|
|
<encodings>
|
|
<encoding encname="MRS_T1_AS" />
|
|
</encodings>
|
|
<orig>Is the special register to be accessed, encoded in "R", where 0->CPSR|APSR, 1->SPSR.</orig>
|
|
<definition encodedin="R">
|
|
<intro>Is the special register to be accessed, </intro>
|
|
<table class="valuetable">
|
|
<tgroup cols="2">
|
|
<thead>
|
|
<row>
|
|
<entry class="bitfield" bitwidth="1">R</entry>
|
|
<entry class="symbol"><spec_reg></entry>
|
|
</row>
|
|
</thead>
|
|
<tbody>
|
|
<row>
|
|
<entry class="bitfield">0</entry>
|
|
<entry class="symbol">CPSR|APSR</entry>
|
|
</row>
|
|
<row>
|
|
<entry class="bitfield">1</entry>
|
|
<entry class="symbol">SPSR</entry>
|
|
</row>
|
|
</tbody>
|
|
</tgroup>
|
|
</table>
|
|
</definition>
|
|
</account>
|
|
<account iclass="msr_bank" symbol="<banked_reg>" iclass_long="MSR (banked)">
|
|
<encodings>
|
|
<encoding encname="MSR_br_T1_AS" />
|
|
</encodings>
|
|
<orig>Is the name of the banked register to be transferred to or from, encoded in the "R:M:M1" field, where 000000->R8_usr, 000001->R9_usr, 000010->R10_usr, 000011->R11_usr, 000100->R12_usr, 000101->SP_usr, 000110->LR_usr, 001000->R8_fiq, 001001->R9_fiq, 001010->R10_fiq, 001011->R11_fiq, 001100->R12_fiq, 001101->SP_fiq, 001110->LR_fiq, 010000->LR_irq, 010001->SP_irq, 010010->LR_svc, 010011->SP_svc, 010100->LR_abt, 010101->SP_abt, 010110->LR_und, 010111->SP_und, 011100->LR_mon, 011101->SP_mon, 011110->ELR_hyp, 011111->SP_hyp, 101110->SPSR_fiq, 110000->SPSR_irq, 110010->SPSR_svc, 110100->SPSR_abt, 110110->SPSR_und, 111100->SPSR_mon, 111110->SPSR_hyp, otherwise UNPREDICTABLE</orig>
|
|
<definition encodedin="R:M:M1">
|
|
<intro>Is the name of the banked register to be transferred to or from, </intro>
|
|
<table class="valuetable">
|
|
<tgroup cols="4">
|
|
<thead>
|
|
<row>
|
|
<entry class="bitfield" bitwidth="1">R</entry>
|
|
<entry class="bitfield" bitwidth="1">M</entry>
|
|
<entry class="bitfield" bitwidth="4">M1</entry>
|
|
<entry class="symbol"><banked_reg></entry>
|
|
</row>
|
|
</thead>
|
|
<tbody>
|
|
<row>
|
|
<entry class="bitfield">0</entry>
|
|
<entry class="bitfield">0</entry>
|
|
<entry class="bitfield">0000</entry>
|
|
<entry class="symbol">R8_usr</entry>
|
|
</row>
|
|
<row>
|
|
<entry class="bitfield">0</entry>
|
|
<entry class="bitfield">0</entry>
|
|
<entry class="bitfield">0001</entry>
|
|
<entry class="symbol">R9_usr</entry>
|
|
</row>
|
|
<row>
|
|
<entry class="bitfield">0</entry>
|
|
<entry class="bitfield">0</entry>
|
|
<entry class="bitfield">0010</entry>
|
|
<entry class="symbol">R10_usr</entry>
|
|
</row>
|
|
<row>
|
|
<entry class="bitfield">0</entry>
|
|
<entry class="bitfield">0</entry>
|
|
<entry class="bitfield">0011</entry>
|
|
<entry class="symbol">R11_usr</entry>
|
|
</row>
|
|
<row>
|
|
<entry class="bitfield">0</entry>
|
|
<entry class="bitfield">0</entry>
|
|
<entry class="bitfield">0100</entry>
|
|
<entry class="symbol">R12_usr</entry>
|
|
</row>
|
|
<row>
|
|
<entry class="bitfield">0</entry>
|
|
<entry class="bitfield">0</entry>
|
|
<entry class="bitfield">0101</entry>
|
|
<entry class="symbol">SP_usr</entry>
|
|
</row>
|
|
<row>
|
|
<entry class="bitfield">0</entry>
|
|
<entry class="bitfield">0</entry>
|
|
<entry class="bitfield">0110</entry>
|
|
<entry class="symbol">LR_usr</entry>
|
|
</row>
|
|
<row>
|
|
<entry class="bitfield">0</entry>
|
|
<entry class="bitfield">0</entry>
|
|
<entry class="bitfield">0111</entry>
|
|
<entry class="symbol">UNPREDICTABLE</entry>
|
|
</row>
|
|
<row>
|
|
<entry class="bitfield">0</entry>
|
|
<entry class="bitfield">0</entry>
|
|
<entry class="bitfield">1000</entry>
|
|
<entry class="symbol">R8_fiq</entry>
|
|
</row>
|
|
<row>
|
|
<entry class="bitfield">0</entry>
|
|
<entry class="bitfield">0</entry>
|
|
<entry class="bitfield">1001</entry>
|
|
<entry class="symbol">R9_fiq</entry>
|
|
</row>
|
|
<row>
|
|
<entry class="bitfield">0</entry>
|
|
<entry class="bitfield">0</entry>
|
|
<entry class="bitfield">1010</entry>
|
|
<entry class="symbol">R10_fiq</entry>
|
|
</row>
|
|
<row>
|
|
<entry class="bitfield">0</entry>
|
|
<entry class="bitfield">0</entry>
|
|
<entry class="bitfield">1011</entry>
|
|
<entry class="symbol">R11_fiq</entry>
|
|
</row>
|
|
<row>
|
|
<entry class="bitfield">0</entry>
|
|
<entry class="bitfield">0</entry>
|
|
<entry class="bitfield">1100</entry>
|
|
<entry class="symbol">R12_fiq</entry>
|
|
</row>
|
|
<row>
|
|
<entry class="bitfield">0</entry>
|
|
<entry class="bitfield">0</entry>
|
|
<entry class="bitfield">1101</entry>
|
|
<entry class="symbol">SP_fiq</entry>
|
|
</row>
|
|
<row>
|
|
<entry class="bitfield">0</entry>
|
|
<entry class="bitfield">0</entry>
|
|
<entry class="bitfield">1110</entry>
|
|
<entry class="symbol">LR_fiq</entry>
|
|
</row>
|
|
<row>
|
|
<entry class="bitfield">0</entry>
|
|
<entry class="bitfield">0</entry>
|
|
<entry class="bitfield">1111</entry>
|
|
<entry class="symbol">UNPREDICTABLE</entry>
|
|
</row>
|
|
<row>
|
|
<entry class="bitfield">0</entry>
|
|
<entry class="bitfield">1</entry>
|
|
<entry class="bitfield">0000</entry>
|
|
<entry class="symbol">LR_irq</entry>
|
|
</row>
|
|
<row>
|
|
<entry class="bitfield">0</entry>
|
|
<entry class="bitfield">1</entry>
|
|
<entry class="bitfield">0001</entry>
|
|
<entry class="symbol">SP_irq</entry>
|
|
</row>
|
|
<row>
|
|
<entry class="bitfield">0</entry>
|
|
<entry class="bitfield">1</entry>
|
|
<entry class="bitfield">0010</entry>
|
|
<entry class="symbol">LR_svc</entry>
|
|
</row>
|
|
<row>
|
|
<entry class="bitfield">0</entry>
|
|
<entry class="bitfield">1</entry>
|
|
<entry class="bitfield">0011</entry>
|
|
<entry class="symbol">SP_svc</entry>
|
|
</row>
|
|
<row>
|
|
<entry class="bitfield">0</entry>
|
|
<entry class="bitfield">1</entry>
|
|
<entry class="bitfield">0100</entry>
|
|
<entry class="symbol">LR_abt</entry>
|
|
</row>
|
|
<row>
|
|
<entry class="bitfield">0</entry>
|
|
<entry class="bitfield">1</entry>
|
|
<entry class="bitfield">0101</entry>
|
|
<entry class="symbol">SP_abt</entry>
|
|
</row>
|
|
<row>
|
|
<entry class="bitfield">0</entry>
|
|
<entry class="bitfield">1</entry>
|
|
<entry class="bitfield">0110</entry>
|
|
<entry class="symbol">LR_und</entry>
|
|
</row>
|
|
<row>
|
|
<entry class="bitfield">0</entry>
|
|
<entry class="bitfield">1</entry>
|
|
<entry class="bitfield">0111</entry>
|
|
<entry class="symbol">SP_und</entry>
|
|
</row>
|
|
<row>
|
|
<entry class="bitfield">0</entry>
|
|
<entry class="bitfield">1</entry>
|
|
<entry class="bitfield">10xx</entry>
|
|
<entry class="symbol">UNPREDICTABLE</entry>
|
|
</row>
|
|
<row>
|
|
<entry class="bitfield">0</entry>
|
|
<entry class="bitfield">1</entry>
|
|
<entry class="bitfield">1100</entry>
|
|
<entry class="symbol">LR_mon</entry>
|
|
</row>
|
|
<row>
|
|
<entry class="bitfield">0</entry>
|
|
<entry class="bitfield">1</entry>
|
|
<entry class="bitfield">1101</entry>
|
|
<entry class="symbol">SP_mon</entry>
|
|
</row>
|
|
<row>
|
|
<entry class="bitfield">0</entry>
|
|
<entry class="bitfield">1</entry>
|
|
<entry class="bitfield">1110</entry>
|
|
<entry class="symbol">ELR_hyp</entry>
|
|
</row>
|
|
<row>
|
|
<entry class="bitfield">0</entry>
|
|
<entry class="bitfield">1</entry>
|
|
<entry class="bitfield">1111</entry>
|
|
<entry class="symbol">SP_hyp</entry>
|
|
</row>
|
|
<row>
|
|
<entry class="bitfield">1</entry>
|
|
<entry class="bitfield">0</entry>
|
|
<entry class="bitfield">0xxx</entry>
|
|
<entry class="symbol">UNPREDICTABLE</entry>
|
|
</row>
|
|
<row>
|
|
<entry class="bitfield">1</entry>
|
|
<entry class="bitfield">0</entry>
|
|
<entry class="bitfield">10xx</entry>
|
|
<entry class="symbol">UNPREDICTABLE</entry>
|
|
</row>
|
|
<row>
|
|
<entry class="bitfield">1</entry>
|
|
<entry class="bitfield">0</entry>
|
|
<entry class="bitfield">110x</entry>
|
|
<entry class="symbol">UNPREDICTABLE</entry>
|
|
</row>
|
|
<row>
|
|
<entry class="bitfield">1</entry>
|
|
<entry class="bitfield">0</entry>
|
|
<entry class="bitfield">1110</entry>
|
|
<entry class="symbol">SPSR_fiq</entry>
|
|
</row>
|
|
<row>
|
|
<entry class="bitfield">1</entry>
|
|
<entry class="bitfield">0</entry>
|
|
<entry class="bitfield">1111</entry>
|
|
<entry class="symbol">UNPREDICTABLE</entry>
|
|
</row>
|
|
<row>
|
|
<entry class="bitfield">1</entry>
|
|
<entry class="bitfield">1</entry>
|
|
<entry class="bitfield">0000</entry>
|
|
<entry class="symbol">SPSR_irq</entry>
|
|
</row>
|
|
<row>
|
|
<entry class="bitfield">1</entry>
|
|
<entry class="bitfield">1</entry>
|
|
<entry class="bitfield">0001</entry>
|
|
<entry class="symbol">UNPREDICTABLE</entry>
|
|
</row>
|
|
<row>
|
|
<entry class="bitfield">1</entry>
|
|
<entry class="bitfield">1</entry>
|
|
<entry class="bitfield">0010</entry>
|
|
<entry class="symbol">SPSR_svc</entry>
|
|
</row>
|
|
<row>
|
|
<entry class="bitfield">1</entry>
|
|
<entry class="bitfield">1</entry>
|
|
<entry class="bitfield">0011</entry>
|
|
<entry class="symbol">UNPREDICTABLE</entry>
|
|
</row>
|
|
<row>
|
|
<entry class="bitfield">1</entry>
|
|
<entry class="bitfield">1</entry>
|
|
<entry class="bitfield">0100</entry>
|
|
<entry class="symbol">SPSR_abt</entry>
|
|
</row>
|
|
<row>
|
|
<entry class="bitfield">1</entry>
|
|
<entry class="bitfield">1</entry>
|
|
<entry class="bitfield">0101</entry>
|
|
<entry class="symbol">UNPREDICTABLE</entry>
|
|
</row>
|
|
<row>
|
|
<entry class="bitfield">1</entry>
|
|
<entry class="bitfield">1</entry>
|
|
<entry class="bitfield">0110</entry>
|
|
<entry class="symbol">SPSR_und</entry>
|
|
</row>
|
|
<row>
|
|
<entry class="bitfield">1</entry>
|
|
<entry class="bitfield">1</entry>
|
|
<entry class="bitfield">0111</entry>
|
|
<entry class="symbol">UNPREDICTABLE</entry>
|
|
</row>
|
|
<row>
|
|
<entry class="bitfield">1</entry>
|
|
<entry class="bitfield">1</entry>
|
|
<entry class="bitfield">10xx</entry>
|
|
<entry class="symbol">UNPREDICTABLE</entry>
|
|
</row>
|
|
<row>
|
|
<entry class="bitfield">1</entry>
|
|
<entry class="bitfield">1</entry>
|
|
<entry class="bitfield">1100</entry>
|
|
<entry class="symbol">SPSR_mon</entry>
|
|
</row>
|
|
<row>
|
|
<entry class="bitfield">1</entry>
|
|
<entry class="bitfield">1</entry>
|
|
<entry class="bitfield">1101</entry>
|
|
<entry class="symbol">UNPREDICTABLE</entry>
|
|
</row>
|
|
<row>
|
|
<entry class="bitfield">1</entry>
|
|
<entry class="bitfield">1</entry>
|
|
<entry class="bitfield">1110</entry>
|
|
<entry class="symbol">SPSR_hyp</entry>
|
|
</row>
|
|
<row>
|
|
<entry class="bitfield">1</entry>
|
|
<entry class="bitfield">1</entry>
|
|
<entry class="bitfield">1111</entry>
|
|
<entry class="symbol">UNPREDICTABLE</entry>
|
|
</row>
|
|
</tbody>
|
|
</tgroup>
|
|
</table>
|
|
</definition>
|
|
</account>
|
|
<account iclass="movsr_reg" symbol="<banked_reg>" iclass_long="Move special register (register)">
|
|
<encodings>
|
|
<encoding encname="MRS_br_A1_AS" />
|
|
<encoding encname="MSR_br_A1_AS" />
|
|
</encodings>
|
|
<orig>Is the name of the banked register to be transferred to or from, encoded in the "R:M:M1" field, where 000000->R8_usr, 000001->R9_usr, 000010->R10_usr, 000011->R11_usr, 000100->R12_usr, 000101->SP_usr, 000110->LR_usr, 001000->R8_fiq, 001001->R9_fiq, 001010->R10_fiq, 001011->R11_fiq, 001100->R12_fiq, 001101->SP_fiq, 001110->LR_fiq, 010000->LR_irq, 010001->SP_irq, 010010->LR_svc, 010011->SP_svc, 010100->LR_abt, 010101->SP_abt, 010110->LR_und, 010111->SP_und, 011100->LR_mon, 011101->SP_mon, 011110->ELR_hyp, 011111->SP_hyp, 101110->SPSR_fiq, 110000->SPSR_irq, 110010->SPSR_svc, 110100->SPSR_abt, 110110->SPSR_und, 111100->SPSR_mon, 111110->SPSR_hyp, otherwise UNPREDICTABLE</orig>
|
|
<definition encodedin="R:M:M1">
|
|
<intro>Is the name of the banked register to be transferred to or from, </intro>
|
|
<table class="valuetable">
|
|
<tgroup cols="4">
|
|
<thead>
|
|
<row>
|
|
<entry class="bitfield" bitwidth="1">R</entry>
|
|
<entry class="bitfield" bitwidth="1">M</entry>
|
|
<entry class="bitfield" bitwidth="4">M1</entry>
|
|
<entry class="symbol"><banked_reg></entry>
|
|
</row>
|
|
</thead>
|
|
<tbody>
|
|
<row>
|
|
<entry class="bitfield">0</entry>
|
|
<entry class="bitfield">0</entry>
|
|
<entry class="bitfield">0000</entry>
|
|
<entry class="symbol">R8_usr</entry>
|
|
</row>
|
|
<row>
|
|
<entry class="bitfield">0</entry>
|
|
<entry class="bitfield">0</entry>
|
|
<entry class="bitfield">0001</entry>
|
|
<entry class="symbol">R9_usr</entry>
|
|
</row>
|
|
<row>
|
|
<entry class="bitfield">0</entry>
|
|
<entry class="bitfield">0</entry>
|
|
<entry class="bitfield">0010</entry>
|
|
<entry class="symbol">R10_usr</entry>
|
|
</row>
|
|
<row>
|
|
<entry class="bitfield">0</entry>
|
|
<entry class="bitfield">0</entry>
|
|
<entry class="bitfield">0011</entry>
|
|
<entry class="symbol">R11_usr</entry>
|
|
</row>
|
|
<row>
|
|
<entry class="bitfield">0</entry>
|
|
<entry class="bitfield">0</entry>
|
|
<entry class="bitfield">0100</entry>
|
|
<entry class="symbol">R12_usr</entry>
|
|
</row>
|
|
<row>
|
|
<entry class="bitfield">0</entry>
|
|
<entry class="bitfield">0</entry>
|
|
<entry class="bitfield">0101</entry>
|
|
<entry class="symbol">SP_usr</entry>
|
|
</row>
|
|
<row>
|
|
<entry class="bitfield">0</entry>
|
|
<entry class="bitfield">0</entry>
|
|
<entry class="bitfield">0110</entry>
|
|
<entry class="symbol">LR_usr</entry>
|
|
</row>
|
|
<row>
|
|
<entry class="bitfield">0</entry>
|
|
<entry class="bitfield">0</entry>
|
|
<entry class="bitfield">0111</entry>
|
|
<entry class="symbol">UNPREDICTABLE</entry>
|
|
</row>
|
|
<row>
|
|
<entry class="bitfield">0</entry>
|
|
<entry class="bitfield">0</entry>
|
|
<entry class="bitfield">1000</entry>
|
|
<entry class="symbol">R8_fiq</entry>
|
|
</row>
|
|
<row>
|
|
<entry class="bitfield">0</entry>
|
|
<entry class="bitfield">0</entry>
|
|
<entry class="bitfield">1001</entry>
|
|
<entry class="symbol">R9_fiq</entry>
|
|
</row>
|
|
<row>
|
|
<entry class="bitfield">0</entry>
|
|
<entry class="bitfield">0</entry>
|
|
<entry class="bitfield">1010</entry>
|
|
<entry class="symbol">R10_fiq</entry>
|
|
</row>
|
|
<row>
|
|
<entry class="bitfield">0</entry>
|
|
<entry class="bitfield">0</entry>
|
|
<entry class="bitfield">1011</entry>
|
|
<entry class="symbol">R11_fiq</entry>
|
|
</row>
|
|
<row>
|
|
<entry class="bitfield">0</entry>
|
|
<entry class="bitfield">0</entry>
|
|
<entry class="bitfield">1100</entry>
|
|
<entry class="symbol">R12_fiq</entry>
|
|
</row>
|
|
<row>
|
|
<entry class="bitfield">0</entry>
|
|
<entry class="bitfield">0</entry>
|
|
<entry class="bitfield">1101</entry>
|
|
<entry class="symbol">SP_fiq</entry>
|
|
</row>
|
|
<row>
|
|
<entry class="bitfield">0</entry>
|
|
<entry class="bitfield">0</entry>
|
|
<entry class="bitfield">1110</entry>
|
|
<entry class="symbol">LR_fiq</entry>
|
|
</row>
|
|
<row>
|
|
<entry class="bitfield">0</entry>
|
|
<entry class="bitfield">0</entry>
|
|
<entry class="bitfield">1111</entry>
|
|
<entry class="symbol">UNPREDICTABLE</entry>
|
|
</row>
|
|
<row>
|
|
<entry class="bitfield">0</entry>
|
|
<entry class="bitfield">1</entry>
|
|
<entry class="bitfield">0000</entry>
|
|
<entry class="symbol">LR_irq</entry>
|
|
</row>
|
|
<row>
|
|
<entry class="bitfield">0</entry>
|
|
<entry class="bitfield">1</entry>
|
|
<entry class="bitfield">0001</entry>
|
|
<entry class="symbol">SP_irq</entry>
|
|
</row>
|
|
<row>
|
|
<entry class="bitfield">0</entry>
|
|
<entry class="bitfield">1</entry>
|
|
<entry class="bitfield">0010</entry>
|
|
<entry class="symbol">LR_svc</entry>
|
|
</row>
|
|
<row>
|
|
<entry class="bitfield">0</entry>
|
|
<entry class="bitfield">1</entry>
|
|
<entry class="bitfield">0011</entry>
|
|
<entry class="symbol">SP_svc</entry>
|
|
</row>
|
|
<row>
|
|
<entry class="bitfield">0</entry>
|
|
<entry class="bitfield">1</entry>
|
|
<entry class="bitfield">0100</entry>
|
|
<entry class="symbol">LR_abt</entry>
|
|
</row>
|
|
<row>
|
|
<entry class="bitfield">0</entry>
|
|
<entry class="bitfield">1</entry>
|
|
<entry class="bitfield">0101</entry>
|
|
<entry class="symbol">SP_abt</entry>
|
|
</row>
|
|
<row>
|
|
<entry class="bitfield">0</entry>
|
|
<entry class="bitfield">1</entry>
|
|
<entry class="bitfield">0110</entry>
|
|
<entry class="symbol">LR_und</entry>
|
|
</row>
|
|
<row>
|
|
<entry class="bitfield">0</entry>
|
|
<entry class="bitfield">1</entry>
|
|
<entry class="bitfield">0111</entry>
|
|
<entry class="symbol">SP_und</entry>
|
|
</row>
|
|
<row>
|
|
<entry class="bitfield">0</entry>
|
|
<entry class="bitfield">1</entry>
|
|
<entry class="bitfield">10xx</entry>
|
|
<entry class="symbol">UNPREDICTABLE</entry>
|
|
</row>
|
|
<row>
|
|
<entry class="bitfield">0</entry>
|
|
<entry class="bitfield">1</entry>
|
|
<entry class="bitfield">1100</entry>
|
|
<entry class="symbol">LR_mon</entry>
|
|
</row>
|
|
<row>
|
|
<entry class="bitfield">0</entry>
|
|
<entry class="bitfield">1</entry>
|
|
<entry class="bitfield">1101</entry>
|
|
<entry class="symbol">SP_mon</entry>
|
|
</row>
|
|
<row>
|
|
<entry class="bitfield">0</entry>
|
|
<entry class="bitfield">1</entry>
|
|
<entry class="bitfield">1110</entry>
|
|
<entry class="symbol">ELR_hyp</entry>
|
|
</row>
|
|
<row>
|
|
<entry class="bitfield">0</entry>
|
|
<entry class="bitfield">1</entry>
|
|
<entry class="bitfield">1111</entry>
|
|
<entry class="symbol">SP_hyp</entry>
|
|
</row>
|
|
<row>
|
|
<entry class="bitfield">1</entry>
|
|
<entry class="bitfield">0</entry>
|
|
<entry class="bitfield">0xxx</entry>
|
|
<entry class="symbol">UNPREDICTABLE</entry>
|
|
</row>
|
|
<row>
|
|
<entry class="bitfield">1</entry>
|
|
<entry class="bitfield">0</entry>
|
|
<entry class="bitfield">10xx</entry>
|
|
<entry class="symbol">UNPREDICTABLE</entry>
|
|
</row>
|
|
<row>
|
|
<entry class="bitfield">1</entry>
|
|
<entry class="bitfield">0</entry>
|
|
<entry class="bitfield">110x</entry>
|
|
<entry class="symbol">UNPREDICTABLE</entry>
|
|
</row>
|
|
<row>
|
|
<entry class="bitfield">1</entry>
|
|
<entry class="bitfield">0</entry>
|
|
<entry class="bitfield">1110</entry>
|
|
<entry class="symbol">SPSR_fiq</entry>
|
|
</row>
|
|
<row>
|
|
<entry class="bitfield">1</entry>
|
|
<entry class="bitfield">0</entry>
|
|
<entry class="bitfield">1111</entry>
|
|
<entry class="symbol">UNPREDICTABLE</entry>
|
|
</row>
|
|
<row>
|
|
<entry class="bitfield">1</entry>
|
|
<entry class="bitfield">1</entry>
|
|
<entry class="bitfield">0000</entry>
|
|
<entry class="symbol">SPSR_irq</entry>
|
|
</row>
|
|
<row>
|
|
<entry class="bitfield">1</entry>
|
|
<entry class="bitfield">1</entry>
|
|
<entry class="bitfield">0001</entry>
|
|
<entry class="symbol">UNPREDICTABLE</entry>
|
|
</row>
|
|
<row>
|
|
<entry class="bitfield">1</entry>
|
|
<entry class="bitfield">1</entry>
|
|
<entry class="bitfield">0010</entry>
|
|
<entry class="symbol">SPSR_svc</entry>
|
|
</row>
|
|
<row>
|
|
<entry class="bitfield">1</entry>
|
|
<entry class="bitfield">1</entry>
|
|
<entry class="bitfield">0011</entry>
|
|
<entry class="symbol">UNPREDICTABLE</entry>
|
|
</row>
|
|
<row>
|
|
<entry class="bitfield">1</entry>
|
|
<entry class="bitfield">1</entry>
|
|
<entry class="bitfield">0100</entry>
|
|
<entry class="symbol">SPSR_abt</entry>
|
|
</row>
|
|
<row>
|
|
<entry class="bitfield">1</entry>
|
|
<entry class="bitfield">1</entry>
|
|
<entry class="bitfield">0101</entry>
|
|
<entry class="symbol">UNPREDICTABLE</entry>
|
|
</row>
|
|
<row>
|
|
<entry class="bitfield">1</entry>
|
|
<entry class="bitfield">1</entry>
|
|
<entry class="bitfield">0110</entry>
|
|
<entry class="symbol">SPSR_und</entry>
|
|
</row>
|
|
<row>
|
|
<entry class="bitfield">1</entry>
|
|
<entry class="bitfield">1</entry>
|
|
<entry class="bitfield">0111</entry>
|
|
<entry class="symbol">UNPREDICTABLE</entry>
|
|
</row>
|
|
<row>
|
|
<entry class="bitfield">1</entry>
|
|
<entry class="bitfield">1</entry>
|
|
<entry class="bitfield">10xx</entry>
|
|
<entry class="symbol">UNPREDICTABLE</entry>
|
|
</row>
|
|
<row>
|
|
<entry class="bitfield">1</entry>
|
|
<entry class="bitfield">1</entry>
|
|
<entry class="bitfield">1100</entry>
|
|
<entry class="symbol">SPSR_mon</entry>
|
|
</row>
|
|
<row>
|
|
<entry class="bitfield">1</entry>
|
|
<entry class="bitfield">1</entry>
|
|
<entry class="bitfield">1101</entry>
|
|
<entry class="symbol">UNPREDICTABLE</entry>
|
|
</row>
|
|
<row>
|
|
<entry class="bitfield">1</entry>
|
|
<entry class="bitfield">1</entry>
|
|
<entry class="bitfield">1110</entry>
|
|
<entry class="symbol">SPSR_hyp</entry>
|
|
</row>
|
|
<row>
|
|
<entry class="bitfield">1</entry>
|
|
<entry class="bitfield">1</entry>
|
|
<entry class="bitfield">1111</entry>
|
|
<entry class="symbol">UNPREDICTABLE</entry>
|
|
</row>
|
|
</tbody>
|
|
</tgroup>
|
|
</table>
|
|
</definition>
|
|
</account>
|
|
<account iclass="movsr_reg" symbol="<spec_reg>" iclass_long="Move special register (register)">
|
|
<encodings>
|
|
<encoding encname="MRS_A1_AS" />
|
|
</encodings>
|
|
<orig>Is the special register to be accessed, encoded in "R", where 0->CPSR|APSR, 1->SPSR.</orig>
|
|
<definition encodedin="R">
|
|
<intro>Is the special register to be accessed, </intro>
|
|
<table class="valuetable">
|
|
<tgroup cols="2">
|
|
<thead>
|
|
<row>
|
|
<entry class="bitfield" bitwidth="1">R</entry>
|
|
<entry class="symbol"><spec_reg></entry>
|
|
</row>
|
|
</thead>
|
|
<tbody>
|
|
<row>
|
|
<entry class="bitfield">0</entry>
|
|
<entry class="symbol">CPSR|APSR</entry>
|
|
</row>
|
|
<row>
|
|
<entry class="bitfield">1</entry>
|
|
<entry class="symbol">SPSR</entry>
|
|
</row>
|
|
</tbody>
|
|
</tgroup>
|
|
</table>
|
|
</definition>
|
|
</account>
|
|
<account iclass="preload_imm" symbol="+/-" iclass_long="Preload (immediate)">
|
|
<encodings>
|
|
<encoding encname="PLDW_i_A1" />
|
|
<encoding encname="PLD_i_A1" />
|
|
<encoding encname="PLD_l_A1" />
|
|
<encoding encname="PLI_i_A1" />
|
|
</encodings>
|
|
<orig>Specifies the offset is added to or subtracted from the base register, defaulting to + if omitted and encoded in the "U" field, where 0->-, 1->+.</orig>
|
|
<definition encodedin="U">
|
|
<intro>Specifies the offset is added to or subtracted from the base register, defaulting to + if omitted and </intro>
|
|
<table class="valuetable">
|
|
<tgroup cols="2">
|
|
<thead>
|
|
<row>
|
|
<entry class="bitfield" bitwidth="1">U</entry>
|
|
<entry class="symbol">+/-</entry>
|
|
</row>
|
|
</thead>
|
|
<tbody>
|
|
<row>
|
|
<entry class="bitfield">0</entry>
|
|
<entry class="symbol">-</entry>
|
|
</row>
|
|
<row>
|
|
<entry class="bitfield">1</entry>
|
|
<entry class="symbol">+</entry>
|
|
</row>
|
|
</tbody>
|
|
</tgroup>
|
|
</table>
|
|
</definition>
|
|
</account>
|
|
<account iclass="preload_reg" symbol="<shift>" iclass_long="Preload (register)">
|
|
<encodings>
|
|
<encoding encname="PLDW_r_A1" />
|
|
<encoding encname="PLD_r_A1" />
|
|
<encoding encname="PLI_r_A1" />
|
|
</encodings>
|
|
<orig>Is the type of shift to be applied to the index register, encoded in "stype", where 00->LSL, 01->LSR, 10->ASR, 11->ROR.</orig>
|
|
<definition encodedin="stype">
|
|
<intro>Is the type of shift to be applied to the index register, </intro>
|
|
<table class="valuetable">
|
|
<tgroup cols="2">
|
|
<thead>
|
|
<row>
|
|
<entry class="bitfield" bitwidth="2">stype</entry>
|
|
<entry class="symbol"><shift></entry>
|
|
</row>
|
|
</thead>
|
|
<tbody>
|
|
<row>
|
|
<entry class="bitfield">00</entry>
|
|
<entry class="symbol">LSL</entry>
|
|
</row>
|
|
<row>
|
|
<entry class="bitfield">01</entry>
|
|
<entry class="symbol">LSR</entry>
|
|
</row>
|
|
<row>
|
|
<entry class="bitfield">10</entry>
|
|
<entry class="symbol">ASR</entry>
|
|
</row>
|
|
<row>
|
|
<entry class="bitfield">11</entry>
|
|
<entry class="symbol">ROR</entry>
|
|
</row>
|
|
</tbody>
|
|
</tgroup>
|
|
</table>
|
|
</definition>
|
|
</account>
|
|
<account iclass="preload_reg" symbol="+/-" iclass_long="Preload (register)">
|
|
<encodings>
|
|
<encoding encname="PLDW_r_A1" />
|
|
<encoding encname="PLDW_r_A1_RRX" />
|
|
<encoding encname="PLD_r_A1" />
|
|
<encoding encname="PLD_r_A1_RRX" />
|
|
<encoding encname="PLI_r_A1" />
|
|
<encoding encname="PLI_r_A1_RRX" />
|
|
</encodings>
|
|
<orig>Specifies the index register is added to or subtracted from the base register, defaulting to + if omitted and encoded in the "U" field, where 0->-, 1->+.</orig>
|
|
<definition encodedin="U">
|
|
<intro>Specifies the index register is added to or subtracted from the base register, defaulting to + if omitted and </intro>
|
|
<table class="valuetable">
|
|
<tgroup cols="2">
|
|
<thead>
|
|
<row>
|
|
<entry class="bitfield" bitwidth="1">U</entry>
|
|
<entry class="symbol">+/-</entry>
|
|
</row>
|
|
</thead>
|
|
<tbody>
|
|
<row>
|
|
<entry class="bitfield">0</entry>
|
|
<entry class="symbol">-</entry>
|
|
</row>
|
|
<row>
|
|
<entry class="bitfield">1</entry>
|
|
<entry class="symbol">+</entry>
|
|
</row>
|
|
</tbody>
|
|
</tgroup>
|
|
</table>
|
|
</definition>
|
|
</account>
|
|
<account iclass="extendr" symbol="<amount>" iclass_long="Register extends">
|
|
<encodings>
|
|
<encoding encname="SXTAB16_T1" />
|
|
<encoding encname="SXTAB_T1" />
|
|
<encoding encname="SXTAH_T1" />
|
|
<encoding encname="SXTB16_T1" />
|
|
<encoding encname="SXTB_T2" />
|
|
<encoding encname="SXTH_T2" />
|
|
<encoding encname="UXTAB16_T1" />
|
|
<encoding encname="UXTAB_T1" />
|
|
<encoding encname="UXTAH_T1" />
|
|
<encoding encname="UXTB16_T1" />
|
|
<encoding encname="UXTB_T2" />
|
|
<encoding encname="UXTH_T2" />
|
|
</encodings>
|
|
<orig>Is the rotate amount, encoded in "rotate", where 00->(omitted), 01->8, 10->16, 11->24</orig>
|
|
<definition encodedin="rotate">
|
|
<intro>Is the rotate amount, </intro>
|
|
<table class="valuetable">
|
|
<tgroup cols="2">
|
|
<thead>
|
|
<row>
|
|
<entry class="bitfield" bitwidth="2">rotate</entry>
|
|
<entry class="symbol"><amount></entry>
|
|
</row>
|
|
</thead>
|
|
<tbody>
|
|
<row>
|
|
<entry class="bitfield">00</entry>
|
|
<entry class="symbol">(omitted)</entry>
|
|
</row>
|
|
<row>
|
|
<entry class="bitfield">01</entry>
|
|
<entry class="symbol">8</entry>
|
|
</row>
|
|
<row>
|
|
<entry class="bitfield">10</entry>
|
|
<entry class="symbol">16</entry>
|
|
</row>
|
|
<row>
|
|
<entry class="bitfield">11</entry>
|
|
<entry class="symbol">24</entry>
|
|
</row>
|
|
</tbody>
|
|
</tgroup>
|
|
</table>
|
|
</definition>
|
|
</account>
|
|
<account iclass="shiftr" symbol="<shift>" iclass_long="Register shifts">
|
|
<encodings>
|
|
<encoding encname="MOVS_rr_T2" />
|
|
<encoding encname="MOV_rr_T2" />
|
|
</encodings>
|
|
<orig>Is the type of shift to be applied to the second source register, encoded in "stype", where 00->LSL, 01->LSR, 10->ASR, 11->ROR.</orig>
|
|
<definition encodedin="stype">
|
|
<intro>Is the type of shift to be applied to the second source register, </intro>
|
|
<table class="valuetable">
|
|
<tgroup cols="2">
|
|
<thead>
|
|
<row>
|
|
<entry class="bitfield" bitwidth="2">stype</entry>
|
|
<entry class="symbol"><shift></entry>
|
|
</row>
|
|
</thead>
|
|
<tbody>
|
|
<row>
|
|
<entry class="bitfield">00</entry>
|
|
<entry class="symbol">LSL</entry>
|
|
</row>
|
|
<row>
|
|
<entry class="bitfield">01</entry>
|
|
<entry class="symbol">LSR</entry>
|
|
</row>
|
|
<row>
|
|
<entry class="bitfield">10</entry>
|
|
<entry class="symbol">ASR</entry>
|
|
</row>
|
|
<row>
|
|
<entry class="bitfield">11</entry>
|
|
<entry class="symbol">ROR</entry>
|
|
</row>
|
|
</tbody>
|
|
</tgroup>
|
|
</table>
|
|
</definition>
|
|
</account>
|
|
<account iclass="shift16_imm" symbol="<shift>" iclass_long="Shift (immediate)">
|
|
<encodings>
|
|
<encoding encname="MOV_r_T2" />
|
|
</encodings>
|
|
<orig>Is the type of shift to be applied to the source register, encoded in "op", where 00->LSL, 01->LSR, 10->ASR.</orig>
|
|
<definition encodedin="op">
|
|
<intro>Is the type of shift to be applied to the source register, </intro>
|
|
<table class="valuetable">
|
|
<tgroup cols="2">
|
|
<thead>
|
|
<row>
|
|
<entry class="bitfield" bitwidth="2">op</entry>
|
|
<entry class="symbol"><shift></entry>
|
|
</row>
|
|
</thead>
|
|
<tbody>
|
|
<row>
|
|
<entry class="bitfield">00</entry>
|
|
<entry class="symbol">LSL</entry>
|
|
</row>
|
|
<row>
|
|
<entry class="bitfield">01</entry>
|
|
<entry class="symbol">LSR</entry>
|
|
</row>
|
|
<row>
|
|
<entry class="bitfield">10</entry>
|
|
<entry class="symbol">ASR</entry>
|
|
</row>
|
|
</tbody>
|
|
</tgroup>
|
|
</table>
|
|
</definition>
|
|
</account>
|
|
<account iclass="movcpgp32" symbol="<coproc>" iclass_long="System register 32-bit move">
|
|
<encodings>
|
|
<encoding encname="MCR_A1" />
|
|
<encoding encname="MRC_A1" />
|
|
</encodings>
|
|
<orig>Is the System register encoding space, encoded in "coproc<0>", where 0->p14, 1->p15.</orig>
|
|
<definition encodedin="coproc<0>">
|
|
<intro>Is the System register encoding space, </intro>
|
|
<table class="valuetable">
|
|
<tgroup cols="2">
|
|
<thead>
|
|
<row>
|
|
<entry class="bitfield" bitwidth="1">coproc<0></entry>
|
|
<entry class="symbol"><coproc></entry>
|
|
</row>
|
|
</thead>
|
|
<tbody>
|
|
<row>
|
|
<entry class="bitfield">0</entry>
|
|
<entry class="symbol">p14</entry>
|
|
</row>
|
|
<row>
|
|
<entry class="bitfield">1</entry>
|
|
<entry class="symbol">p15</entry>
|
|
</row>
|
|
</tbody>
|
|
</tgroup>
|
|
</table>
|
|
</definition>
|
|
</account>
|
|
<account iclass="cp_mov32" symbol="<coproc>" iclass_long="System register 32-bit move">
|
|
<encodings>
|
|
<encoding encname="MCR_T1" />
|
|
<encoding encname="MRC_T1" />
|
|
</encodings>
|
|
<orig>Is the System register encoding space, encoded in "coproc<0>", where 0->p14, 1->p15.</orig>
|
|
<definition encodedin="coproc<0>">
|
|
<intro>Is the System register encoding space, </intro>
|
|
<table class="valuetable">
|
|
<tgroup cols="2">
|
|
<thead>
|
|
<row>
|
|
<entry class="bitfield" bitwidth="1">coproc<0></entry>
|
|
<entry class="symbol"><coproc></entry>
|
|
</row>
|
|
</thead>
|
|
<tbody>
|
|
<row>
|
|
<entry class="bitfield">0</entry>
|
|
<entry class="symbol">p14</entry>
|
|
</row>
|
|
<row>
|
|
<entry class="bitfield">1</entry>
|
|
<entry class="symbol">p15</entry>
|
|
</row>
|
|
</tbody>
|
|
</tgroup>
|
|
</table>
|
|
</definition>
|
|
</account>
|
|
<account iclass="movcpgp64" symbol="<coproc>" iclass_long="System register 64-bit move">
|
|
<encodings>
|
|
<encoding encname="MCRR_A1" />
|
|
<encoding encname="MRRC_A1" />
|
|
</encodings>
|
|
<orig>Is the System register encoding space, encoded in "coproc<0>", where 0->p14, 1->p15.</orig>
|
|
<definition encodedin="coproc<0>">
|
|
<intro>Is the System register encoding space, </intro>
|
|
<table class="valuetable">
|
|
<tgroup cols="2">
|
|
<thead>
|
|
<row>
|
|
<entry class="bitfield" bitwidth="1">coproc<0></entry>
|
|
<entry class="symbol"><coproc></entry>
|
|
</row>
|
|
</thead>
|
|
<tbody>
|
|
<row>
|
|
<entry class="bitfield">0</entry>
|
|
<entry class="symbol">p14</entry>
|
|
</row>
|
|
<row>
|
|
<entry class="bitfield">1</entry>
|
|
<entry class="symbol">p15</entry>
|
|
</row>
|
|
</tbody>
|
|
</tgroup>
|
|
</table>
|
|
</definition>
|
|
</account>
|
|
<account iclass="cp_mov64" symbol="<coproc>" iclass_long="System register 64-bit move">
|
|
<encodings>
|
|
<encoding encname="MCRR_T1" />
|
|
<encoding encname="MRRC_T1" />
|
|
</encodings>
|
|
<orig>Is the System register encoding space, encoded in "coproc<0>", where 0->p14, 1->p15.</orig>
|
|
<definition encodedin="coproc<0>">
|
|
<intro>Is the System register encoding space, </intro>
|
|
<table class="valuetable">
|
|
<tgroup cols="2">
|
|
<thead>
|
|
<row>
|
|
<entry class="bitfield" bitwidth="1">coproc<0></entry>
|
|
<entry class="symbol"><coproc></entry>
|
|
</row>
|
|
</thead>
|
|
<tbody>
|
|
<row>
|
|
<entry class="bitfield">0</entry>
|
|
<entry class="symbol">p14</entry>
|
|
</row>
|
|
<row>
|
|
<entry class="bitfield">1</entry>
|
|
<entry class="symbol">p15</entry>
|
|
</row>
|
|
</tbody>
|
|
</tgroup>
|
|
</table>
|
|
</definition>
|
|
</account>
|
|
<account iclass="cp_ldst" symbol="+/-" iclass_long="System register Load/Store">
|
|
<encodings>
|
|
<encoding encname="LDC_i_T1_off" />
|
|
<encoding encname="LDC_i_T1_post" />
|
|
<encoding encname="LDC_i_T1_pre" />
|
|
<encoding encname="LDC_l_T1" />
|
|
<encoding encname="STC_T1_off" />
|
|
<encoding encname="STC_T1_post" />
|
|
<encoding encname="STC_T1_pre" />
|
|
</encodings>
|
|
<orig>Specifies the offset is added to or subtracted from the base register, defaulting to + if omitted and encoded in the "U" field, where 0->-, 1->+.</orig>
|
|
<definition encodedin="U">
|
|
<intro>Specifies the offset is added to or subtracted from the base register, defaulting to + if omitted and </intro>
|
|
<table class="valuetable">
|
|
<tgroup cols="2">
|
|
<thead>
|
|
<row>
|
|
<entry class="bitfield" bitwidth="1">U</entry>
|
|
<entry class="symbol">+/-</entry>
|
|
</row>
|
|
</thead>
|
|
<tbody>
|
|
<row>
|
|
<entry class="bitfield">0</entry>
|
|
<entry class="symbol">-</entry>
|
|
</row>
|
|
<row>
|
|
<entry class="bitfield">1</entry>
|
|
<entry class="symbol">+</entry>
|
|
</row>
|
|
</tbody>
|
|
</tgroup>
|
|
</table>
|
|
</definition>
|
|
</account>
|
|
<account iclass="ldstcp" symbol="+/-" iclass_long="System register load/store">
|
|
<encodings>
|
|
<encoding encname="LDC_i_A1_off" />
|
|
<encoding encname="LDC_i_A1_post" />
|
|
<encoding encname="LDC_i_A1_pre" />
|
|
<encoding encname="LDC_l_A1" />
|
|
<encoding encname="STC_A1_off" />
|
|
<encoding encname="STC_A1_post" />
|
|
<encoding encname="STC_A1_pre" />
|
|
</encodings>
|
|
<orig>Specifies the offset is added to or subtracted from the base register, defaulting to + if omitted and encoded in the "U" field, where 0->-, 1->+.</orig>
|
|
<definition encodedin="U">
|
|
<intro>Specifies the offset is added to or subtracted from the base register, defaulting to + if omitted and </intro>
|
|
<table class="valuetable">
|
|
<tgroup cols="2">
|
|
<thead>
|
|
<row>
|
|
<entry class="bitfield" bitwidth="1">U</entry>
|
|
<entry class="symbol">+/-</entry>
|
|
</row>
|
|
</thead>
|
|
<tbody>
|
|
<row>
|
|
<entry class="bitfield">0</entry>
|
|
<entry class="symbol">-</entry>
|
|
</row>
|
|
<row>
|
|
<entry class="bitfield">1</entry>
|
|
<entry class="symbol">+</entry>
|
|
</row>
|
|
</tbody>
|
|
</tgroup>
|
|
</table>
|
|
</definition>
|
|
</account>
|
|
</accounts>
|