338 lines
19 KiB
XML
338 lines
19 KiB
XML
<?xml version="1.0" encoding="utf-8"?>
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<?xml-stylesheet type="text/xsl" encoding="UTF-8" href="iform.xsl" version="1.0"?>
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<!DOCTYPE instructionsection PUBLIC "-//ARM//DTD instructionsection //EN" "iform-p.dtd">
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<!-- Copyright (c) 2010-2022 Arm Limited or its affiliates. All rights reserved. -->
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<!-- This document is Non-Confidential. This document may only be used and distributed in accordance with the terms of the agreement entered into by Arm and the party that Arm delivered this document to. -->
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<instructionsection id="CRC32" title="CRC32 -- AArch32" type="instruction">
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<docvars>
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<docvar key="instr-class" value="general" />
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</docvars>
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<heading>CRC32</heading>
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<desc>
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<brief>
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<para>CRC32</para>
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</brief>
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<authored>
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<para><instruction>CRC32</instruction> performs a cyclic redundancy check (CRC) calculation on a value held in a general-purpose register. It takes an input CRC value in the first source operand, performs a CRC on the input value in the second source operand, and returns the output CRC value. The second source operand can be 8, 16, or 32 bits. To align with common usage, the bit order of the values is reversed as part of the operation, and the polynomial <hexnumber>0x04C11DB7</hexnumber> is used for the CRC calculation.</para>
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<para>In an Armv8.0 implementation, this is an <arm-defined-word>optional</arm-defined-word> instruction. From Armv8.1, it is mandatory for all implementations to implement this instruction.</para>
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<note>
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<para><xref linkend="AArch32.id_isar5">ID_ISAR5</xref>.CRC32 indicates whether this instruction is supported in the T32 and A32 instruction sets.</para>
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</note>
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</authored>
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<encodingnotes>
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<para>For more information about the <arm-defined-word>constrained unpredictable</arm-defined-word> behavior, see <xref linkend="CJAEGDJC">Architectural Constraints on UNPREDICTABLE behaviors</xref>.</para>
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</encodingnotes>
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</desc>
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<operationalnotes>
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<para>If CPSR.DIT is 1 and this instruction passes its condition execution check:</para>
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<list type="unordered">
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<listitem><content>The execution time of this instruction is independent of:<list type="unordered"><listitem><content>The values of the data supplied in any of its registers.</content></listitem><listitem><content>The values of the NZCV flags.</content></listitem></list></content></listitem>
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<listitem><content>The response of this instruction to asynchronous exceptions does not vary based on:<list type="unordered"><listitem><content>The values of the data supplied in any of its registers.</content></listitem><listitem><content>The values of the NZCV flags.</content></listitem></list></content></listitem>
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</list>
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</operationalnotes>
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<alias_list howmany="0"></alias_list>
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<classes>
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<classesintro count="2">
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<txt>It has encodings from the following instruction sets:</txt>
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<txt> A32 (</txt>
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<a href="#iclass_a1">A1</a>
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<txt>)</txt>
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<txt> and </txt>
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<txt> T32 (</txt>
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<a href="#iclass_t1">T1</a>
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<txt>)</txt>
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<txt>.</txt>
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</classesintro>
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<iclass name="A1" oneof="2" id="iclass_a1" no_encodings="3" isa="A32">
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<docvars>
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<docvar key="armarmheading" value="A1" />
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<docvar key="instr-class" value="general" />
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<docvar key="isa" value="A32" />
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</docvars>
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<iclassintro count="3"></iclassintro>
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<arch_variants>
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<arch_variant name="ARMv8.0" feature="FEAT_CRC32" />
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</arch_variants>
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<regdiagram form="32" psname="aarch32/instrs/CRC32/A1_A.txt" tworows="1">
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<box hibit="31" width="4" name="cond" usename="1" settings="4" constraint="!= 1111">
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<c colspan="4">!= 1111</c>
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</box>
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<box hibit="27" width="5" settings="5">
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<c>0</c>
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<c>0</c>
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<c>0</c>
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<c>1</c>
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<c>0</c>
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</box>
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<box hibit="22" width="2" name="sz" usename="1">
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<c colspan="2"></c>
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</box>
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<box hibit="20" settings="1">
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<c>0</c>
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</box>
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<box hibit="19" width="4" name="Rn" usename="1">
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<c colspan="4"></c>
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</box>
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<box hibit="15" width="4" name="Rd" usename="1">
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<c colspan="4"></c>
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</box>
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<box hibit="11" settings="1">
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<c>(0)</c>
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</box>
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<box hibit="10" settings="1">
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<c>(0)</c>
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</box>
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<box hibit="9" name="C" usename="1" settings="1">
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<c>0</c>
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</box>
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<box hibit="8" settings="1">
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<c>(0)</c>
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</box>
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<box hibit="7" width="4" settings="4">
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<c>0</c>
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<c>1</c>
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<c>0</c>
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<c>0</c>
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</box>
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<box hibit="3" width="4" name="Rm" usename="1">
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<c colspan="4"></c>
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</box>
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</regdiagram>
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<encoding name="CRC32B_A1" oneofinclass="3" oneof="6" label="CRC32B" bitdiffs="sz == 00">
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<docvars>
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<docvar key="armarmheading" value="A1" />
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<docvar key="instr-class" value="general" />
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<docvar key="isa" value="A32" />
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<docvar key="mnemonic" value="CRC32B" />
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</docvars>
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<box hibit="22" width="2" name="sz">
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<c>0</c>
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<c>0</c>
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</box>
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<asmtemplate><text>CRC32B</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}"><q></a><text>}</text><text> </text><a link="sa_rd" hover="General-purpose accumulator output register (field "Rd")"><Rd></a><text>, </text><a link="sa_rn" hover="General-purpose accumulator input register (field "Rn")"><Rn></a><text>, </text><a link="sa_rm" hover="General-purpose data source register (field "Rm")"><Rm></a></asmtemplate>
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</encoding>
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<encoding name="CRC32H_A1" oneofinclass="3" oneof="6" label="CRC32H" bitdiffs="sz == 01">
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<docvars>
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<docvar key="armarmheading" value="A1" />
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<docvar key="instr-class" value="general" />
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<docvar key="isa" value="A32" />
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<docvar key="mnemonic" value="CRC32H" />
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</docvars>
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<box hibit="22" width="2" name="sz">
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<c>0</c>
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<c>1</c>
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</box>
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<asmtemplate><text>CRC32H</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}"><q></a><text>}</text><text> </text><a link="sa_rd" hover="General-purpose accumulator output register (field "Rd")"><Rd></a><text>, </text><a link="sa_rn" hover="General-purpose accumulator input register (field "Rn")"><Rn></a><text>, </text><a link="sa_rm" hover="General-purpose data source register (field "Rm")"><Rm></a></asmtemplate>
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</encoding>
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<encoding name="CRC32W_A1" oneofinclass="3" oneof="6" label="CRC32W" bitdiffs="sz == 10">
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<docvars>
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<docvar key="armarmheading" value="A1" />
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<docvar key="instr-class" value="general" />
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<docvar key="isa" value="A32" />
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<docvar key="mnemonic" value="CRC32W" />
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</docvars>
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<box hibit="22" width="2" name="sz">
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<c>1</c>
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<c>0</c>
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</box>
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<asmtemplate><text>CRC32W</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}"><q></a><text>}</text><text> </text><a link="sa_rd" hover="General-purpose accumulator output register (field "Rd")"><Rd></a><text>, </text><a link="sa_rn" hover="General-purpose accumulator input register (field "Rn")"><Rn></a><text>, </text><a link="sa_rm" hover="General-purpose data source register (field "Rm")"><Rm></a></asmtemplate>
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</encoding>
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<ps_section howmany="1">
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<ps name="aarch32/instrs/CRC32/A1_A.txt" mylink="aarch32.instrs.CRC32.A1_A.txt" enclabels="" sections="1" secttype="noheading">
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<pstext mayhavelinks="1" section="Decode" rep_section="decode">if ! <a link="impl-shared.HaveCRCExt.0" file="shared_pseudocode.xml" hover="function: boolean HaveCRCExt()">HaveCRCExt</a>() then UNDEFINED;
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d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rd); n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rn); m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rm);
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size = 8 << <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(sz);
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crc32c = (C == '1');
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if d == 15 || n == 15 || m == 15 then UNPREDICTABLE;
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if size == 64 then UNPREDICTABLE;
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if cond != '1110' then UNPREDICTABLE;</pstext>
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</ps>
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</ps_section>
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<constrained_unpredictables encoding="A1" ps_block="Decode">
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<cu_case>
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<cu_cause>
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<pstext mayhavelinks="1">size == 64</pstext>
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</cu_cause>
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<cu_type constraint="Constraint_UNDEF" />
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<cu_type constraint="Constraint_NOP" />
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<cu_type constraint="Constraint_ADDITIONAL_DECODE">
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<cu_type_variable name="pseudocode" value="size = 32;" />
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</cu_type>
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</cu_case>
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<cu_case>
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<cu_cause>
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<pstext mayhavelinks="1">cond != '1110'</pstext>
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</cu_cause>
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<cu_type constraint="Constraint_UNDEF" />
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<cu_type constraint="Constraint_NOP" />
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<cu_type constraint="Constraint_UNCOND" />
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<cu_type constraint="Constraint_COND" />
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</cu_case>
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</constrained_unpredictables>
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</iclass>
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<iclass name="T1" oneof="2" id="iclass_t1" no_encodings="3" isa="T32">
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<docvars>
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<docvar key="armarmheading" value="T1" />
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<docvar key="instr-class" value="general" />
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<docvar key="isa" value="T32" />
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</docvars>
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<iclassintro count="3"></iclassintro>
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<arch_variants>
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<arch_variant name="ARMv8.0" feature="FEAT_CRC32" />
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</arch_variants>
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<regdiagram form="16x2" psname="aarch32/instrs/CRC32/T1_A.txt" tworows="1">
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<box hibit="31" width="9" settings="9">
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<c>1</c>
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<c>1</c>
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<c>1</c>
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<c>1</c>
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<c>1</c>
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<c>0</c>
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<c>1</c>
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<c>0</c>
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<c>1</c>
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</box>
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<box hibit="22" width="2" settings="2">
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<c>1</c>
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<c>0</c>
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</box>
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<box hibit="20" name="C" usename="1" settings="1">
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<c>0</c>
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</box>
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<box hibit="19" width="4" name="Rn" usename="1">
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<c colspan="4"></c>
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</box>
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<box hibit="15" width="4" settings="4">
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<c>1</c>
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<c>1</c>
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<c>1</c>
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<c>1</c>
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</box>
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<box hibit="11" width="4" name="Rd" usename="1">
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<c colspan="4"></c>
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</box>
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<box hibit="7" width="2" settings="2">
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<c>1</c>
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<c>0</c>
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</box>
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<box hibit="5" width="2" name="sz" usename="1">
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<c colspan="2"></c>
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</box>
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<box hibit="3" width="4" name="Rm" usename="1">
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<c colspan="4"></c>
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</box>
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</regdiagram>
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<encoding name="CRC32B_T1" oneofinclass="3" oneof="6" label="CRC32B" bitdiffs="sz == 00">
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<docvars>
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<docvar key="armarmheading" value="T1" />
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<docvar key="instr-class" value="general" />
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<docvar key="isa" value="T32" />
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<docvar key="mnemonic" value="CRC32B" />
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</docvars>
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<box hibit="5" width="2" name="sz">
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<c>0</c>
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<c>0</c>
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</box>
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<asmtemplate><text>CRC32B</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}"><q></a><text>}</text><text> </text><a link="sa_rd" hover="General-purpose accumulator output register (field "Rd")"><Rd></a><text>, </text><a link="sa_rn" hover="General-purpose accumulator input register (field "Rn")"><Rn></a><text>, </text><a link="sa_rm" hover="General-purpose data source register (field "Rm")"><Rm></a></asmtemplate>
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</encoding>
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<encoding name="CRC32H_T1" oneofinclass="3" oneof="6" label="CRC32H" bitdiffs="sz == 01">
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<docvars>
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<docvar key="armarmheading" value="T1" />
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<docvar key="instr-class" value="general" />
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<docvar key="isa" value="T32" />
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<docvar key="mnemonic" value="CRC32H" />
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</docvars>
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<box hibit="5" width="2" name="sz">
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<c>0</c>
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<c>1</c>
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</box>
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<asmtemplate><text>CRC32H</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}"><q></a><text>}</text><text> </text><a link="sa_rd" hover="General-purpose accumulator output register (field "Rd")"><Rd></a><text>, </text><a link="sa_rn" hover="General-purpose accumulator input register (field "Rn")"><Rn></a><text>, </text><a link="sa_rm" hover="General-purpose data source register (field "Rm")"><Rm></a></asmtemplate>
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</encoding>
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<encoding name="CRC32W_T1" oneofinclass="3" oneof="6" label="CRC32W" bitdiffs="sz == 10">
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<docvars>
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<docvar key="armarmheading" value="T1" />
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<docvar key="instr-class" value="general" />
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<docvar key="isa" value="T32" />
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<docvar key="mnemonic" value="CRC32W" />
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</docvars>
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<box hibit="5" width="2" name="sz">
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<c>1</c>
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<c>0</c>
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</box>
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<asmtemplate><text>CRC32W</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}"><q></a><text>}</text><text> </text><a link="sa_rd" hover="General-purpose accumulator output register (field "Rd")"><Rd></a><text>, </text><a link="sa_rn" hover="General-purpose accumulator input register (field "Rn")"><Rn></a><text>, </text><a link="sa_rm" hover="General-purpose data source register (field "Rm")"><Rm></a></asmtemplate>
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</encoding>
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<ps_section howmany="1">
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<ps name="aarch32/instrs/CRC32/T1_A.txt" mylink="aarch32.instrs.CRC32.T1_A.txt" enclabels="" sections="1" secttype="noheading">
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<pstext mayhavelinks="1" section="Decode" rep_section="decode">if <a link="impl-aarch32.InITBlock.0" file="shared_pseudocode.xml" hover="function: boolean InITBlock()">InITBlock</a>() then UNPREDICTABLE;
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if ! <a link="impl-shared.HaveCRCExt.0" file="shared_pseudocode.xml" hover="function: boolean HaveCRCExt()">HaveCRCExt</a>() then UNDEFINED;
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d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rd); n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rn); m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rm);
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size = 8 << <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(sz);
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crc32c = (C == '1');
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if d == 15 || n == 15 || m == 15 then UNPREDICTABLE;
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if size == 64 then UNPREDICTABLE;</pstext>
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</ps>
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</ps_section>
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<constrained_unpredictables encoding="T1" ps_block="Decode">
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<cu_case>
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<cu_cause>
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<pstext mayhavelinks="1">size == 64</pstext>
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</cu_cause>
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<cu_type constraint="Constraint_UNDEF" />
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<cu_type constraint="Constraint_NOP" />
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<cu_type constraint="Constraint_ADDITIONAL_DECODE">
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<cu_type_variable name="pseudocode" value="size = 32;" />
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</cu_type>
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</cu_case>
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</constrained_unpredictables>
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</iclass>
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</classes>
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<explanations scope="all">
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<explanation enclist="CRC32B_A1, CRC32B_T1" symboldefcount="1">
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<symbol link="sa_q"><q></symbol>
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<account encodedin="">
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<intro>
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<para>See <xref linkend="Babbefhf">Standard assembler syntax fields</xref>. A <instruction>CRC32</instruction> instruction must be unconditional.</para>
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</intro>
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</account>
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</explanation>
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<explanation enclist="CRC32B_A1, CRC32B_T1" symboldefcount="1">
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<symbol link="sa_rd"><Rd></symbol>
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<account encodedin="Rd">
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<intro>
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<para>Is the general-purpose accumulator output register, encoded in the "Rd" field.</para>
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</intro>
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</account>
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</explanation>
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<explanation enclist="CRC32B_A1, CRC32B_T1" symboldefcount="1">
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<symbol link="sa_rn"><Rn></symbol>
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<account encodedin="Rn">
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<intro>
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<para>Is the general-purpose accumulator input register, encoded in the "Rn" field.</para>
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</intro>
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</account>
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</explanation>
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<explanation enclist="CRC32B_A1, CRC32B_T1" symboldefcount="1">
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<symbol link="sa_rm"><Rm></symbol>
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<account encodedin="Rm">
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<intro>
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<para>Is the general-purpose data source register, encoded in the "Rm" field.</para>
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</intro>
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</account>
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</explanation>
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</explanations>
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<ps_section howmany="1">
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<ps name="aarch32/instrs/CRC32/Op_A.txt" mylink="execute" enclabels="" sections="1" secttype="Operation">
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<pstext mayhavelinks="1" section="Execute" rep_section="execute">if <a link="impl-aarch32.ConditionPassed.0" file="shared_pseudocode.xml" hover="function: boolean ConditionPassed()">ConditionPassed</a>() then
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EncodingSpecificOperations();
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acc = <a link="impl-aarch32.R.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) R[integer n]">R</a>[n]; // accumulator
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val = <a link="impl-aarch32.R.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) R[integer n]">R</a>[m]<size-1:0>; // input value
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poly = (if crc32c then 0x1EDC6F41 else 0x04C11DB7)<31:0>;
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tempacc = <a link="impl-shared.BitReverse.1" file="shared_pseudocode.xml" hover="function: bits(N) BitReverse(bits(N) data)">BitReverse</a>(acc):<a link="impl-shared.Zeros.1" file="shared_pseudocode.xml" hover="function: bits(N) Zeros(integer N)">Zeros</a>(size);
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tempval = <a link="impl-shared.BitReverse.1" file="shared_pseudocode.xml" hover="function: bits(N) BitReverse(bits(N) data)">BitReverse</a>(val):<a link="impl-shared.Zeros.1" file="shared_pseudocode.xml" hover="function: bits(N) Zeros(integer N)">Zeros</a>(32);
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// Poly32Mod2 on a bitstring does a polynomial Modulus over {0,1} operation
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<a link="impl-aarch32.R.write.1" file="shared_pseudocode.xml" hover="accessor: R[integer n] = bits(32) value">R</a>[d] = <a link="impl-shared.BitReverse.1" file="shared_pseudocode.xml" hover="function: bits(N) BitReverse(bits(N) data)">BitReverse</a>(<a link="impl-shared.Poly32Mod2.2" file="shared_pseudocode.xml" hover="function: bits(32) Poly32Mod2(bits(N) data_in, bits(32) poly)">Poly32Mod2</a>(tempacc EOR tempval, poly));</pstext>
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</ps>
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</ps_section>
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</instructionsection>
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