436 lines
22 KiB
XML
436 lines
22 KiB
XML
<?xml version="1.0" encoding="utf-8"?>
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<?xml-stylesheet type="text/xsl" encoding="UTF-8" href="iform.xsl" version="1.0"?>
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<!DOCTYPE instructionsection PUBLIC "-//ARM//DTD instructionsection //EN" "iform-p.dtd">
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<!-- Copyright (c) 2010-2022 Arm Limited or its affiliates. All rights reserved. -->
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<!-- This document is Non-Confidential. This document may only be used and distributed in accordance with the terms of the agreement entered into by Arm and the party that Arm delivered this document to. -->
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<instructionsection id="CMN_r" title="CMN (register) -- AArch32" type="instruction">
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<docvars>
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<docvar key="instr-class" value="general" />
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<docvar key="mnemonic" value="CMN" />
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</docvars>
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<heading>CMN (register)</heading>
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<desc>
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<brief>
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<para>Compare Negative (register)</para>
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</brief>
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<authored>
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<para>Compare Negative (register) adds a register value and an optionally-shifted register value. It updates the condition flags based on the result, and discards the result.</para>
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</authored>
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<encodingnotes>
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<para>For more information about the <arm-defined-word>constrained unpredictable</arm-defined-word> behavior, see <xref linkend="CJAEGDJC">Architectural Constraints on UNPREDICTABLE behaviors</xref>.</para>
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</encodingnotes>
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</desc>
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<operationalnotes>
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<para>If CPSR.DIT is 1, this instruction has passed its condition execution check, and does not use R15 as either its source or destination:</para>
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<list type="unordered">
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<listitem><content>The execution time of this instruction is independent of:<list type="unordered"><listitem><content>The values of the data supplied in any of its registers.</content></listitem><listitem><content>The values of the NZCV flags.</content></listitem></list></content></listitem>
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<listitem><content>The response of this instruction to asynchronous exceptions does not vary based on:<list type="unordered"><listitem><content>The values of the data supplied in any of its registers.</content></listitem><listitem><content>The values of the NZCV flags.</content></listitem></list></content></listitem>
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</list>
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</operationalnotes>
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<alias_list howmany="0"></alias_list>
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<classes>
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<classesintro count="3">
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<txt>It has encodings from the following instruction sets:</txt>
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<txt> A32 (</txt>
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<a href="#iclass_a1">A1</a>
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<txt>)</txt>
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<txt> and </txt>
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<txt> T32 (</txt>
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<a href="#iclass_t1">T1</a>
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<txt> and </txt>
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<a href="#iclass_t2">T2</a>
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<txt>)</txt>
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<txt>.</txt>
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</classesintro>
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<iclass name="A1" oneof="3" id="iclass_a1" no_encodings="2" isa="A32">
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<docvars>
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<docvar key="armarmheading" value="A1" />
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<docvar key="instr-class" value="general" />
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<docvar key="isa" value="A32" />
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<docvar key="mnemonic" value="CMN" />
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</docvars>
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<iclassintro count="2"></iclassintro>
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<regdiagram form="32" psname="aarch32/instrs/CMN_r/A1_A.txt" tworows="1">
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<box hibit="31" width="4" name="cond" usename="1" settings="4" constraint="!= 1111">
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<c colspan="4">!= 1111</c>
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</box>
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<box hibit="27" width="5" settings="5">
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<c>0</c>
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<c>0</c>
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<c>0</c>
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<c>1</c>
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<c>0</c>
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</box>
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<box hibit="22" width="2" name="opc" settings="2">
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<c>1</c>
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<c>1</c>
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</box>
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<box hibit="20" settings="1">
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<c>1</c>
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</box>
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<box hibit="19" width="4" name="Rn" usename="1">
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<c colspan="4"></c>
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</box>
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<box hibit="15" settings="1">
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<c>(0)</c>
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</box>
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<box hibit="14" settings="1">
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<c>(0)</c>
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</box>
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<box hibit="13" settings="1">
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<c>(0)</c>
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</box>
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<box hibit="12" settings="1">
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<c>(0)</c>
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</box>
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<box hibit="11" width="5" name="imm5" usename="1">
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<c colspan="5"></c>
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</box>
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<box hibit="6" width="2" name="stype" usename="1">
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<c colspan="2"></c>
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</box>
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<box hibit="4" settings="1">
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<c>0</c>
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</box>
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<box hibit="3" width="4" name="Rm" usename="1">
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<c colspan="4"></c>
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</box>
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</regdiagram>
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<encoding name="CMN_r_A1_RRX" oneofinclass="2" oneof="5" label="Rotate right with extend" bitdiffs="imm5 == 00000 && stype == 11">
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<docvars>
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<docvar key="armarmheading" value="A1" />
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<docvar key="instr-class" value="general" />
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<docvar key="isa" value="A32" />
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<docvar key="mnemonic" value="CMN" />
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<docvar key="mnemonic-shift-type" value="CMN-rrx" />
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<docvar key="shift-type" value="rrx" />
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</docvars>
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<box hibit="11" width="5" name="imm5">
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<c>0</c>
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<c>0</c>
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<c>0</c>
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<c>0</c>
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<c>0</c>
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</box>
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<box hibit="6" width="2" name="stype">
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<c>1</c>
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<c>1</c>
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</box>
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<asmtemplate><text>CMN</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}"><c></a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}"><q></a><text>}</text><text> </text><a link="sa_rn_1" hover="First general-purpose source register (field "Rn")"><Rn></a><text>, </text><a link="sa_rm_1" hover="Second general-purpose source register (field "Rm")"><Rm></a><text>, RRX</text></asmtemplate>
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</encoding>
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<encoding name="CMN_r_A1" oneofinclass="2" oneof="5" label="Shift or rotate by value" bitdiffs="!(imm5 == 00000 && stype == 11)">
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<docvars>
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<docvar key="armarmheading" value="A1" />
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<docvar key="instr-class" value="general" />
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<docvar key="isa" value="A32" />
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<docvar key="mnemonic" value="CMN" />
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<docvar key="mnemonic-shift-type" value="CMN-shift-no-rrx" />
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<docvar key="shift-type" value="shift-no-rrx" />
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</docvars>
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<box hibit="11" width="7" name="imm5:stype">
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<c>Z</c>
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<c>Z</c>
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<c>Z</c>
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<c>Z</c>
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<c>Z</c>
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<c>N</c>
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<c>N</c>
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</box>
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<asmtemplate><text>CMN</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}"><c></a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}"><q></a><text>}</text><text> </text><a link="sa_rn_1" hover="First general-purpose source register (field "Rn")"><Rn></a><text>, </text><a link="sa_rm_1" hover="Second general-purpose source register (field "Rm")"><Rm></a><text> </text><text>{</text><text>, </text><a link="sa_shift" hover="Type of shift applied to second source register (field "stype") [ASR,LSL,LSR,ROR]"><shift></a><text> #</text><a link="sa_amount_1" hover="Shift amount [1-31 (when <shift> = LSL or ROR) or 1 to 32 (when <shift> = LSR or ASR) (field "imm5")"><amount></a><text>}</text></asmtemplate>
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</encoding>
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<ps_section howmany="1">
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<ps name="aarch32/instrs/CMN_r/A1_A.txt" mylink="aarch32.instrs.CMN_r.A1_A.txt" enclabels="" sections="1" secttype="noheading">
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<pstext mayhavelinks="1" section="Decode" rep_section="decode">n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rn); m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rm);
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(shift_t, shift_n) = <a link="impl-aarch32.DecodeImmShift.2" file="shared_pseudocode.xml" hover="function: (SRType, integer) DecodeImmShift(bits(2) srtype, bits(5) imm5)">DecodeImmShift</a>(stype, imm5);</pstext>
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</ps>
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</ps_section>
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</iclass>
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<iclass name="T1" oneof="3" id="iclass_t1" no_encodings="1" isa="T32">
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<docvars>
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<docvar key="armarmheading" value="T1" />
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<docvar key="instr-class" value="general" />
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<docvar key="isa" value="T32" />
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<docvar key="mnemonic" value="CMN" />
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</docvars>
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<iclassintro count="1"></iclassintro>
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<regdiagram form="16" psname="aarch32/instrs/CMN_r/T1_A.txt">
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<box hibit="31" width="6" settings="6">
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<c>0</c>
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<c>1</c>
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<c>0</c>
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<c>0</c>
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<c>0</c>
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<c>0</c>
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</box>
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<box hibit="25" width="4" name="op" settings="4">
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<c>1</c>
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<c>0</c>
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<c>1</c>
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<c>1</c>
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</box>
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<box hibit="21" width="3" name="Rm" usename="1">
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<c colspan="3"></c>
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</box>
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<box hibit="18" width="3" name="Rn" usename="1">
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<c colspan="3"></c>
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</box>
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</regdiagram>
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<encoding name="CMN_r_T1" oneofinclass="1" oneof="5" label="T1">
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<docvars>
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<docvar key="armarmheading" value="T1" />
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<docvar key="instr-class" value="general" />
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<docvar key="isa" value="T32" />
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<docvar key="mnemonic" value="CMN" />
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</docvars>
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<asmtemplate><text>CMN</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}"><c></a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}"><q></a><text>}</text><text> </text><a link="sa_rn" hover="First general-purpose source register (field "Rn")"><Rn></a><text>, </text><a link="sa_rm" hover="Second general-purpose source register (field "Rm")"><Rm></a></asmtemplate>
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</encoding>
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<ps_section howmany="1">
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<ps name="aarch32/instrs/CMN_r/T1_A.txt" mylink="aarch32.instrs.CMN_r.T1_A.txt" enclabels="" sections="1" secttype="noheading">
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<pstext mayhavelinks="1" section="Decode" rep_section="decode">n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rn); m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rm);
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(shift_t, shift_n) = (<a link="SRType_LSL" file="shared_pseudocode.xml" hover="enumeration SRType {SRType_LSL, SRType_LSR, SRType_ASR, SRType_ROR, SRType_RRX}">SRType_LSL</a>, 0);</pstext>
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</ps>
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</ps_section>
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</iclass>
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<iclass name="T2" oneof="3" id="iclass_t2" no_encodings="2" isa="T32">
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<docvars>
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<docvar key="armarmheading" value="T2" />
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<docvar key="instr-class" value="general" />
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<docvar key="isa" value="T32" />
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<docvar key="mnemonic" value="CMN" />
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</docvars>
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<iclassintro count="2"></iclassintro>
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<regdiagram form="16x2" psname="aarch32/instrs/CMN_r/T2_A.txt">
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<box hibit="31" width="7" settings="7">
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<c>1</c>
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<c>1</c>
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<c>1</c>
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<c>0</c>
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<c>1</c>
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<c>0</c>
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<c>1</c>
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</box>
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<box hibit="24" width="4" name="op1" settings="4">
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<c>1</c>
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<c>0</c>
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<c>0</c>
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<c>0</c>
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</box>
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<box hibit="20" name="S" settings="1">
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<c>1</c>
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</box>
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<box hibit="19" width="4" name="Rn" usename="1">
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<c colspan="4"></c>
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</box>
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<box hibit="15" settings="1">
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<c>(0)</c>
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</box>
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<box hibit="14" width="3" name="imm3" usename="1">
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<c colspan="3"></c>
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</box>
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<box hibit="11" width="4" name="Rd" settings="4">
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<c>1</c>
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<c>1</c>
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<c>1</c>
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<c>1</c>
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</box>
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<box hibit="7" width="2" name="imm2" usename="1">
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<c colspan="2"></c>
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</box>
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<box hibit="5" width="2" name="stype" usename="1">
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<c colspan="2"></c>
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</box>
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<box hibit="3" width="4" name="Rm" usename="1">
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<c colspan="4"></c>
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</box>
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</regdiagram>
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<encoding name="CMN_r_T2_RRX" oneofinclass="2" oneof="5" label="Rotate right with extend" bitdiffs="imm3 == 000 && imm2 == 00 && stype == 11">
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<docvars>
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<docvar key="armarmheading" value="T2" />
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<docvar key="instr-class" value="general" />
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<docvar key="isa" value="T32" />
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<docvar key="mnemonic" value="CMN" />
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<docvar key="mnemonic-shift-type" value="CMN-rrx" />
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<docvar key="shift-type" value="rrx" />
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</docvars>
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<box hibit="14" width="3" name="imm3">
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<c>0</c>
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<c>0</c>
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<c>0</c>
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</box>
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<box hibit="7" width="2" name="imm2">
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<c>0</c>
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<c>0</c>
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</box>
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<box hibit="5" width="2" name="stype">
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<c>1</c>
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<c>1</c>
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</box>
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<asmtemplate><text>CMN</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}"><c></a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}"><q></a><text>}</text><text> </text><a link="sa_rn" hover="First general-purpose source register (field "Rn")"><Rn></a><text>, </text><a link="sa_rm" hover="Second general-purpose source register (field "Rm")"><Rm></a><text>, RRX</text></asmtemplate>
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</encoding>
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<encoding name="CMN_r_T2" oneofinclass="2" oneof="5" label="Shift or rotate by value" bitdiffs="!(imm3 == 000 && imm2 == 00 && stype == 11)">
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<docvars>
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<docvar key="armarmheading" value="T2" />
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<docvar key="instr-class" value="general" />
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<docvar key="isa" value="T32" />
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<docvar key="mnemonic" value="CMN" />
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<docvar key="mnemonic-shift-type" value="CMN-shift-no-rrx" />
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<docvar key="shift-type" value="shift-no-rrx" />
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</docvars>
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<box hibit="14" width="11" name="imm3:imm2:stype">
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<c>Z</c>
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<c>Z</c>
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<c>Z</c>
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<c>Z</c>
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<c>Z</c>
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<c>N</c>
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<c>N</c>
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</box>
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<asmtemplate comment="<Rn>, <Rm> can be represented in T1"><text>CMN</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}"><c></a><text>}</text><text>.W </text><a link="sa_rn" hover="First general-purpose source register (field "Rn")"><Rn></a><text>, </text><a link="sa_rm" hover="Second general-purpose source register (field "Rm")"><Rm></a></asmtemplate>
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<asmtemplate><text>CMN</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}"><c></a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}"><q></a><text>}</text><text> </text><a link="sa_rn" hover="First general-purpose source register (field "Rn")"><Rn></a><text>, </text><a link="sa_rm" hover="Second general-purpose source register (field "Rm")"><Rm></a><text> </text><text>{</text><text>, </text><a link="sa_shift" hover="Type of shift applied to second source register (field "stype") [ASR,LSL,LSR,ROR]"><shift></a><text> #</text><a link="sa_amount" hover="Shift amount [1-31 (when <shift> = LSL or ROR) or 1 to 32 (when <shift> = LSR or ASR)] (field "imm3:imm2")"><amount></a><text>}</text></asmtemplate>
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</encoding>
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<ps_section howmany="1">
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<ps name="aarch32/instrs/CMN_r/T2_A.txt" mylink="aarch32.instrs.CMN_r.T2_A.txt" enclabels="" sections="1" secttype="noheading">
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<pstext mayhavelinks="1" section="Decode" rep_section="decode">n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rn); m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rm);
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(shift_t, shift_n) = <a link="impl-aarch32.DecodeImmShift.2" file="shared_pseudocode.xml" hover="function: (SRType, integer) DecodeImmShift(bits(2) srtype, bits(5) imm5)">DecodeImmShift</a>(stype, imm3:imm2);
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if n == 15 || m == 15 then UNPREDICTABLE; // Armv8-A removes UNPREDICTABLE for R13</pstext>
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</ps>
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</ps_section>
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</iclass>
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</classes>
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<explanations scope="all">
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<explanation enclist="CMN_r_A1, CMN_r_T1, CMN_r_T2" symboldefcount="1">
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<symbol link="sa_c"><c></symbol>
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<account encodedin="">
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<intro>
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<para>See <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
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</intro>
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</account>
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</explanation>
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<explanation enclist="CMN_r_A1, CMN_r_T1, CMN_r_T2" symboldefcount="1">
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<symbol link="sa_q"><q></symbol>
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<account encodedin="">
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<intro>
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<para>See <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
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</intro>
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</account>
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</explanation>
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<explanation enclist="CMN_r_A1" symboldefcount="1">
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<symbol link="sa_rn_1"><Rn></symbol>
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<account encodedin="Rn">
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<docvars>
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<docvar key="armarmheading" value="A1" />
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<docvar key="isa" value="A32" />
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<docvar key="mnemonic-shift-type" value="CMN-shift-no-rrx" />
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<docvar key="shift-type" value="shift-no-rrx" />
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</docvars>
|
|
<intro>
|
|
<para>For encoding A1: is the first general-purpose source register, encoded in the "Rn" field. The PC can be used, but this is deprecated.</para>
|
|
</intro>
|
|
</account>
|
|
</explanation>
|
|
<explanation enclist="CMN_r_T1, CMN_r_T2" symboldefcount="2">
|
|
<symbol link="sa_rn"><Rn></symbol>
|
|
<account encodedin="Rn">
|
|
<docvars>
|
|
<docvar key="isa" value="T32" />
|
|
</docvars>
|
|
<intro>
|
|
<para>For encoding T1 and T2: is the first general-purpose source register, encoded in the "Rn" field.</para>
|
|
</intro>
|
|
</account>
|
|
</explanation>
|
|
<explanation enclist="CMN_r_A1" symboldefcount="1">
|
|
<symbol link="sa_rm_1"><Rm></symbol>
|
|
<account encodedin="Rm">
|
|
<docvars>
|
|
<docvar key="armarmheading" value="A1" />
|
|
<docvar key="isa" value="A32" />
|
|
<docvar key="mnemonic-shift-type" value="CMN-shift-no-rrx" />
|
|
<docvar key="shift-type" value="shift-no-rrx" />
|
|
</docvars>
|
|
<intro>
|
|
<para>For encoding A1: is the second general-purpose source register, encoded in the "Rm" field. The PC can be used, but this is deprecated.</para>
|
|
</intro>
|
|
</account>
|
|
</explanation>
|
|
<explanation enclist="CMN_r_T1, CMN_r_T2" symboldefcount="2">
|
|
<symbol link="sa_rm"><Rm></symbol>
|
|
<account encodedin="Rm">
|
|
<docvars>
|
|
<docvar key="isa" value="T32" />
|
|
</docvars>
|
|
<intro>
|
|
<para>For encoding T1 and T2: is the second general-purpose source register, encoded in the "Rm" field.</para>
|
|
</intro>
|
|
</account>
|
|
</explanation>
|
|
<explanation enclist="CMN_r_A1, CMN_r_T2" symboldefcount="1">
|
|
<symbol link="sa_shift"><shift></symbol>
|
|
<definition encodedin="stype">
|
|
<intro>Is the type of shift to be applied to the second source register, </intro>
|
|
<table class="valuetable">
|
|
<tgroup cols="2">
|
|
<thead>
|
|
<row>
|
|
<entry class="bitfield">stype</entry>
|
|
<entry class="symbol"><shift></entry>
|
|
</row>
|
|
</thead>
|
|
<tbody>
|
|
<row>
|
|
<entry class="bitfield">00</entry>
|
|
<entry class="symbol">LSL</entry>
|
|
</row>
|
|
<row>
|
|
<entry class="bitfield">01</entry>
|
|
<entry class="symbol">LSR</entry>
|
|
</row>
|
|
<row>
|
|
<entry class="bitfield">10</entry>
|
|
<entry class="symbol">ASR</entry>
|
|
</row>
|
|
<row>
|
|
<entry class="bitfield">11</entry>
|
|
<entry class="symbol">ROR</entry>
|
|
</row>
|
|
</tbody>
|
|
</tgroup>
|
|
</table>
|
|
</definition>
|
|
</explanation>
|
|
<explanation enclist="CMN_r_A1" symboldefcount="1">
|
|
<symbol link="sa_amount_1"><amount></symbol>
|
|
<account encodedin="imm5">
|
|
<docvars>
|
|
<docvar key="armarmheading" value="A1" />
|
|
<docvar key="isa" value="A32" />
|
|
</docvars>
|
|
<intro>
|
|
<para>For encoding A1: is the shift amount, in the range 1 to 31 (when <shift> = LSL or ROR) or 1 to 32 (when <shift> = LSR or ASR) encoded in the "imm5" field as <amount> modulo 32.</para>
|
|
</intro>
|
|
</account>
|
|
</explanation>
|
|
<explanation enclist="CMN_r_T2" symboldefcount="2">
|
|
<symbol link="sa_amount"><amount></symbol>
|
|
<account encodedin="imm3:imm2">
|
|
<docvars>
|
|
<docvar key="armarmheading" value="T2" />
|
|
<docvar key="isa" value="T32" />
|
|
</docvars>
|
|
<intro>
|
|
<para>For encoding T2: is the shift amount, in the range 1 to 31 (when <shift> = LSL or ROR) or 1 to 32 (when <shift> = LSR or ASR), encoded in the "imm3:imm2" field as <amount> modulo 32.</para>
|
|
</intro>
|
|
</account>
|
|
</explanation>
|
|
</explanations>
|
|
<ps_section howmany="1">
|
|
<ps name="aarch32/instrs/CMN_r/Op_A.txt" mylink="execute" enclabels="" sections="1" secttype="Operation">
|
|
<pstext mayhavelinks="1" section="Execute" rep_section="execute">if <a link="impl-aarch32.ConditionPassed.0" file="shared_pseudocode.xml" hover="function: boolean ConditionPassed()">ConditionPassed</a>() then
|
|
EncodingSpecificOperations();
|
|
shifted = <a link="impl-aarch32.Shift.4" file="shared_pseudocode.xml" hover="function: bits(N) Shift(bits(N) value, SRType srtype, integer amount, bit carry_in)">Shift</a>(<a link="impl-aarch32.R.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) R[integer n]">R</a>[m], shift_t, shift_n, PSTATE.C);
|
|
(result, nzcv) = <a link="impl-shared.AddWithCarry.3" file="shared_pseudocode.xml" hover="function: (bits(N), bits(4)) AddWithCarry(bits(N) x, bits(N) y, bit carry_in)">AddWithCarry</a>(<a link="impl-aarch32.R.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) R[integer n]">R</a>[n], shifted, '0');
|
|
PSTATE.<N,Z,C,V> = nzcv;</pstext>
|
|
</ps>
|
|
</ps_section>
|
|
</instructionsection>
|