125 lines
6.5 KiB
XML
125 lines
6.5 KiB
XML
<?xml version="1.0" encoding="utf-8"?>
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<?xml-stylesheet type="text/xsl" encoding="UTF-8" href="iform.xsl" version="1.0"?>
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<!DOCTYPE instructionsection PUBLIC "-//ARM//DTD instructionsection //EN" "iform-p.dtd">
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<!-- Copyright (c) 2010-2022 Arm Limited or its affiliates. All rights reserved. -->
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<!-- This document is Non-Confidential. This document may only be used and distributed in accordance with the terms of the agreement entered into by Arm and the party that Arm delivered this document to. -->
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<instructionsection id="CBNZ" title="CBNZ, CBZ -- AArch32" type="instruction">
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<docvars>
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<docvar key="armarmheading" value="T1" />
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<docvar key="instr-class" value="general" />
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<docvar key="isa" value="T32" />
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</docvars>
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<heading>CBNZ, CBZ</heading>
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<desc>
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<brief>
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<para>Compare and Branch on Nonzero or Zero</para>
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</brief>
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<authored>
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<para>Compare and Branch on Nonzero and Compare and Branch on Zero compare the value in a register with zero, and conditionally branch forward a constant value. They do not affect the condition flags.</para>
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</authored>
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<encodingnotes>
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<para>For more information about the <arm-defined-word>constrained unpredictable</arm-defined-word> behavior, see <xref linkend="CJAEGDJC">Architectural Constraints on UNPREDICTABLE behaviors</xref>.</para>
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</encodingnotes>
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</desc>
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<alias_list howmany="0"></alias_list>
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<classes>
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<iclass name="T1" oneof="1" id="iclass_t1" no_encodings="2" isa="T32">
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<docvars>
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<docvar key="armarmheading" value="T1" />
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<docvar key="instr-class" value="general" />
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<docvar key="isa" value="T32" />
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</docvars>
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<iclassintro count="2"></iclassintro>
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<regdiagram form="16" psname="aarch32/instrs/CBNZ/T1_A.txt">
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<box hibit="31" width="4" settings="4">
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<c>1</c>
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<c>0</c>
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<c>1</c>
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<c>1</c>
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</box>
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<box hibit="27" name="op" usename="1">
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<c></c>
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</box>
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<box hibit="26" settings="1">
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<c>0</c>
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</box>
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<box hibit="25" name="i" usename="1">
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<c></c>
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</box>
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<box hibit="24" settings="1">
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<c>1</c>
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</box>
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<box hibit="23" width="5" name="imm5" usename="1">
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<c colspan="5"></c>
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</box>
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<box hibit="18" width="3" name="Rn" usename="1">
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<c colspan="3"></c>
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</box>
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</regdiagram>
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<encoding name="CBNZ_T1" oneofinclass="2" oneof="2" label="CBNZ" bitdiffs="op == 1">
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<docvars>
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<docvar key="armarmheading" value="T1" />
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<docvar key="instr-class" value="general" />
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<docvar key="isa" value="T32" />
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<docvar key="mnemonic" value="CBNZ" />
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</docvars>
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<box hibit="27" width="1" name="op">
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<c>1</c>
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</box>
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<asmtemplate><text>CBNZ</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}"><q></a><text>}</text><text> </text><a link="sa_rn" hover="General-purpose register to be tested (field "Rn")"><Rn></a><text>, </text><a link="sa_label" hover="Label to be conditionally branched to"><label></a></asmtemplate>
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</encoding>
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<encoding name="CBZ_T1" oneofinclass="2" oneof="2" label="CBZ" bitdiffs="op == 0">
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<docvars>
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<docvar key="armarmheading" value="T1" />
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<docvar key="instr-class" value="general" />
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<docvar key="isa" value="T32" />
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<docvar key="mnemonic" value="CBZ" />
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</docvars>
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<box hibit="27" width="1" name="op">
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<c>0</c>
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</box>
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<asmtemplate><text>CBZ</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}"><q></a><text>}</text><text> </text><a link="sa_rn" hover="General-purpose register to be tested (field "Rn")"><Rn></a><text>, </text><a link="sa_label" hover="Label to be conditionally branched to"><label></a></asmtemplate>
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</encoding>
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<ps_section howmany="1">
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<ps name="aarch32/instrs/CBNZ/T1_A.txt" mylink="aarch32.instrs.CBNZ.T1_A.txt" enclabels="" sections="1" secttype="noheading">
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<pstext mayhavelinks="1" section="Decode" rep_section="decode">n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rn); imm32 = <a link="impl-shared.ZeroExtend.2" file="shared_pseudocode.xml" hover="function: bits(N) ZeroExtend(bits(M) x, integer N)">ZeroExtend</a>(i:imm5:'0', 32); nonzero = (op == '1');
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if <a link="impl-aarch32.InITBlock.0" file="shared_pseudocode.xml" hover="function: boolean InITBlock()">InITBlock</a>() then UNPREDICTABLE;</pstext>
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</ps>
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</ps_section>
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</iclass>
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</classes>
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<explanations scope="all">
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<explanation enclist="CBNZ_T1" symboldefcount="1">
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<symbol link="sa_q"><q></symbol>
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<account encodedin="">
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<intro>
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<para>See <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
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</intro>
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</account>
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</explanation>
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<explanation enclist="CBNZ_T1" symboldefcount="1">
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<symbol link="sa_rn"><Rn></symbol>
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<account encodedin="Rn">
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<intro>
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<para>Is the general-purpose register to be tested, encoded in the "Rn" field.</para>
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</intro>
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</account>
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</explanation>
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<explanation enclist="CBNZ_T1" symboldefcount="1">
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<symbol link="sa_label"><label></symbol>
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<account encodedin="i:imm5">
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<intro>
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<para>Is the program label to be conditionally branched to. Its offset from the PC, a multiple of 2 and in the range 0 to 126, is encoded as "i:imm5" times 2.</para>
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</intro>
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</account>
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</explanation>
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</explanations>
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<ps_section howmany="1">
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<ps name="aarch32/instrs/CBNZ/Op_A.txt" mylink="execute" enclabels="" sections="1" secttype="Operation">
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<pstext mayhavelinks="1" section="Execute" rep_section="execute">EncodingSpecificOperations();
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if nonzero != <a link="impl-shared.IsZero.1" file="shared_pseudocode.xml" hover="function: boolean IsZero(bits(N) x)">IsZero</a>(<a link="impl-aarch32.R.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) R[integer n]">R</a>[n]) then
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<a link="impl-aarch32.CBWritePC.1" file="shared_pseudocode.xml" hover="function: CBWritePC(bits(32) address_in)">CBWritePC</a>(<a link="impl-aarch32.PC.read.none" file="shared_pseudocode.xml" hover="accessor: bits(32) PC">PC</a> + imm32);</pstext>
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</ps>
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</ps_section>
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</instructionsection>
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