269 lines
13 KiB
XML
269 lines
13 KiB
XML
<?xml version="1.0" encoding="utf-8"?>
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<?xml-stylesheet type="text/xsl" encoding="UTF-8" href="iform.xsl" version="1.0"?>
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<!DOCTYPE instructionsection PUBLIC "-//ARM//DTD instructionsection //EN" "iform-p.dtd">
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<!-- Copyright (c) 2010-2022 Arm Limited or its affiliates. All rights reserved. -->
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<!-- This document is Non-Confidential. This document may only be used and distributed in accordance with the terms of the agreement entered into by Arm and the party that Arm delivered this document to. -->
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<instructionsection id="BFI" title="BFI -- AArch32" type="instruction">
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<docvars>
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<docvar key="instr-class" value="general" />
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<docvar key="mnemonic" value="BFI" />
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</docvars>
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<heading>BFI</heading>
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<desc>
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<brief>
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<para>Bit Field Insert</para>
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</brief>
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<authored>
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<para>Bit Field Insert copies any number of low order bits from a register into the same number of adjacent bits at any position in the destination register.</para>
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</authored>
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<encodingnotes>
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<para>For more information about the <arm-defined-word>constrained unpredictable</arm-defined-word> behavior of this instruction, see <xref linkend="CJAEGDJC">Architectural Constraints on UNPREDICTABLE behaviors</xref>.</para>
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</encodingnotes>
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</desc>
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<operationalnotes>
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<para>If CPSR.DIT is 1, this instruction has passed its condition execution check, and does not use R15 as either its source or destination:</para>
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<list type="unordered">
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<listitem><content>The execution time of this instruction is independent of:<list type="unordered"><listitem><content>The values of the data supplied in any of its registers.</content></listitem><listitem><content>The values of the NZCV flags.</content></listitem></list></content></listitem>
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<listitem><content>The response of this instruction to asynchronous exceptions does not vary based on:<list type="unordered"><listitem><content>The values of the data supplied in any of its registers.</content></listitem><listitem><content>The values of the NZCV flags.</content></listitem></list></content></listitem>
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</list>
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</operationalnotes>
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<alias_list howmany="0"></alias_list>
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<classes>
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<classesintro count="2">
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<txt>It has encodings from the following instruction sets:</txt>
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<txt> A32 (</txt>
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<a href="#iclass_a1">A1</a>
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<txt>)</txt>
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<txt> and </txt>
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<txt> T32 (</txt>
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<a href="#iclass_t1">T1</a>
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<txt>)</txt>
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<txt>.</txt>
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</classesintro>
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<iclass name="A1" oneof="2" id="iclass_a1" no_encodings="1" isa="A32">
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<docvars>
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<docvar key="armarmheading" value="A1" />
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<docvar key="instr-class" value="general" />
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<docvar key="isa" value="A32" />
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<docvar key="mnemonic" value="BFI" />
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</docvars>
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<iclassintro count="1"></iclassintro>
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<regdiagram form="32" psname="aarch32/instrs/BFI/A1_A.txt" tworows="1">
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<box hibit="31" width="4" name="cond" usename="1" settings="4" constraint="!= 1111">
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<c colspan="4">!= 1111</c>
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</box>
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<box hibit="27" width="7" settings="7">
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<c>0</c>
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<c>1</c>
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<c>1</c>
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<c>1</c>
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<c>1</c>
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<c>1</c>
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<c>0</c>
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</box>
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<box hibit="20" width="5" name="msb" usename="1">
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<c colspan="5"></c>
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</box>
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<box hibit="15" width="4" name="Rd" usename="1">
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<c colspan="4"></c>
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</box>
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<box hibit="11" width="5" name="lsb" usename="1">
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<c colspan="5"></c>
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</box>
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<box hibit="6" width="3" settings="3">
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<c>0</c>
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<c>0</c>
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<c>1</c>
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</box>
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<box hibit="3" width="4" name="Rn" usename="1" settings="4" constraint="!= 1111">
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<c colspan="4">!= 1111</c>
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</box>
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</regdiagram>
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<encoding name="BFI_A1" oneofinclass="1" oneof="2" label="A1">
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<docvars>
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<docvar key="armarmheading" value="A1" />
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<docvar key="instr-class" value="general" />
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<docvar key="isa" value="A32" />
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<docvar key="mnemonic" value="BFI" />
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</docvars>
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<asmtemplate><text>BFI</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}"><c></a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}"><q></a><text>}</text><text> </text><a link="sa_rd" hover="General-purpose destination register (field "Rd")"><Rd></a><text>, </text><a link="sa_rn" hover="General-purpose source register (field "Rn")"><Rn></a><text>, #</text><a link="sa_lsb_1" hover="Least significant destination bit [0-31] (field "lsb")"><lsb></a><text>, #</text><a link="sa_width" hover="Number of bits to be copied [1-32-<lsb>] (field "msb")"><width></a></asmtemplate>
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</encoding>
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<ps_section howmany="1">
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<ps name="aarch32/instrs/BFI/A1_A.txt" mylink="aarch32.instrs.BFI.A1_A.txt" enclabels="" sections="1" secttype="noheading">
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<pstext mayhavelinks="1" section="Decode" rep_section="decode">if Rn == '1111' then SEE "BFC";
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d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rd); n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rn); msbit = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(msb); lsbit = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(lsb);
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if d == 15 then UNPREDICTABLE;
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if msbit < lsbit then UNPREDICTABLE;</pstext>
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</ps>
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</ps_section>
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<constrained_unpredictables encoding="A1" ps_block="Decode">
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<cu_case>
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<cu_cause>
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<pstext mayhavelinks="1">msbit < lsbit</pstext>
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</cu_cause>
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<cu_type constraint="Constraint_UNDEF" />
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<cu_type constraint="Constraint_NOP" />
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<cu_type constraint="Constraint_UNKNOWN" />
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</cu_case>
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</constrained_unpredictables>
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</iclass>
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<iclass name="T1" oneof="2" id="iclass_t1" no_encodings="1" isa="T32">
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<docvars>
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<docvar key="armarmheading" value="T1" />
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<docvar key="instr-class" value="general" />
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<docvar key="isa" value="T32" />
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<docvar key="mnemonic" value="BFI" />
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</docvars>
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<iclassintro count="1"></iclassintro>
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<regdiagram form="16x2" psname="aarch32/instrs/BFI/T1_A.txt" tworows="1">
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<box hibit="31" width="5" settings="5">
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<c>1</c>
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<c>1</c>
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<c>1</c>
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<c>1</c>
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<c>0</c>
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</box>
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<box hibit="26" settings="1">
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<c>(0)</c>
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</box>
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<box hibit="25" width="2" settings="2">
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<c>1</c>
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<c>1</c>
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</box>
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<box hibit="23" width="2" name="op1<2:1>" settings="2">
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<c>0</c>
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<c>1</c>
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</box>
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<box hibit="21" name="op1<0>" settings="1">
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<c>1</c>
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</box>
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<box hibit="20" settings="1">
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<c>0</c>
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</box>
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<box hibit="19" width="4" name="Rn" usename="1" settings="4" constraint="!= 1111">
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<c colspan="4">!= 1111</c>
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</box>
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<box hibit="15" settings="1">
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<c>0</c>
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</box>
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<box hibit="14" width="3" name="imm3" usename="1">
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<c colspan="3"></c>
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</box>
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<box hibit="11" width="4" name="Rd" usename="1">
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<c colspan="4"></c>
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</box>
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<box hibit="7" width="2" name="imm2" usename="1">
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<c colspan="2"></c>
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</box>
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<box hibit="5" settings="1">
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<c>(0)</c>
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</box>
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<box hibit="4" width="5" name="msb" usename="1">
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<c colspan="5"></c>
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</box>
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</regdiagram>
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<encoding name="BFI_T1" oneofinclass="1" oneof="2" label="T1">
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<docvars>
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<docvar key="armarmheading" value="T1" />
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<docvar key="instr-class" value="general" />
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<docvar key="isa" value="T32" />
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<docvar key="mnemonic" value="BFI" />
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</docvars>
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<asmtemplate><text>BFI</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}"><c></a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}"><q></a><text>}</text><text> </text><a link="sa_rd" hover="General-purpose destination register (field "Rd")"><Rd></a><text>, </text><a link="sa_rn" hover="General-purpose source register (field "Rn")"><Rn></a><text>, #</text><a link="sa_lsb" hover="Least significant destination bit [0-31] (field "imm3:imm2")"><lsb></a><text>, #</text><a link="sa_width" hover="Number of bits to be copied [1-32-<lsb>] (field "msb")"><width></a></asmtemplate>
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</encoding>
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<ps_section howmany="1">
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<ps name="aarch32/instrs/BFI/T1_A.txt" mylink="aarch32.instrs.BFI.T1_A.txt" enclabels="" sections="1" secttype="noheading">
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<pstext mayhavelinks="1" section="Decode" rep_section="decode">if Rn == '1111' then SEE "BFC";
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d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rd); n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rn); msbit = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(msb); lsbit = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(imm3:imm2);
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if d == 15 then UNPREDICTABLE; // Armv8-A removes UNPREDICTABLE for R13
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if msbit < lsbit then UNPREDICTABLE;</pstext>
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</ps>
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</ps_section>
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<constrained_unpredictables encoding="T1" ps_block="Decode">
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<cu_case>
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<cu_cause>
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<pstext mayhavelinks="1">msbit < lsbit</pstext>
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</cu_cause>
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<cu_type constraint="Constraint_UNDEF" />
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<cu_type constraint="Constraint_NOP" />
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<cu_type constraint="Constraint_UNKNOWN" />
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</cu_case>
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</constrained_unpredictables>
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</iclass>
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</classes>
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<explanations scope="all">
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<explanation enclist="BFI_A1, BFI_T1" symboldefcount="1">
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<symbol link="sa_c"><c></symbol>
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<account encodedin="">
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<intro>
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<para>See <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
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</intro>
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</account>
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</explanation>
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<explanation enclist="BFI_A1, BFI_T1" symboldefcount="1">
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<symbol link="sa_q"><q></symbol>
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<account encodedin="">
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<intro>
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<para>See <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
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</intro>
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</account>
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</explanation>
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<explanation enclist="BFI_A1, BFI_T1" symboldefcount="1">
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<symbol link="sa_rd"><Rd></symbol>
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<account encodedin="Rd">
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<intro>
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<para>Is the general-purpose destination register, encoded in the "Rd" field.</para>
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</intro>
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</account>
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</explanation>
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<explanation enclist="BFI_A1, BFI_T1" symboldefcount="1">
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<symbol link="sa_rn"><Rn></symbol>
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<account encodedin="Rn">
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<intro>
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<para>Is the general-purpose source register, encoded in the "Rn" field.</para>
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</intro>
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</account>
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</explanation>
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<explanation enclist="BFI_A1" symboldefcount="1">
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<symbol link="sa_lsb_1"><lsb></symbol>
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<account encodedin="lsb">
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<docvars>
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<docvar key="armarmheading" value="A1" />
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<docvar key="isa" value="A32" />
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</docvars>
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<intro>
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<para>For encoding A1: is the least significant destination bit, in the range 0 to 31, encoded in the "lsb" field.</para>
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</intro>
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</account>
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</explanation>
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<explanation enclist="BFI_T1" symboldefcount="2">
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<symbol link="sa_lsb"><lsb></symbol>
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<account encodedin="imm3:imm2">
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<docvars>
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<docvar key="armarmheading" value="T1" />
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<docvar key="isa" value="T32" />
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</docvars>
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<intro>
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<para>For encoding T1: is the least significant destination bit, in the range 0 to 31, encoded in the "imm3:imm2" field.</para>
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</intro>
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</account>
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</explanation>
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<explanation enclist="BFI_A1, BFI_T1" symboldefcount="1">
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<symbol link="sa_width"><width></symbol>
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<account encodedin="msb">
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<intro>
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<para>Is the number of bits to be copied, in the range 1 to 32-<lsb>, encoded in the "msb" field as <lsb>+<width>-1.</para>
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</intro>
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</account>
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</explanation>
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</explanations>
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<ps_section howmany="1">
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<ps name="aarch32/instrs/BFI/Op_A.txt" mylink="execute" enclabels="" sections="1" secttype="Operation">
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<pstext mayhavelinks="1" section="Execute" rep_section="execute">if <a link="impl-aarch32.ConditionPassed.0" file="shared_pseudocode.xml" hover="function: boolean ConditionPassed()">ConditionPassed</a>() then
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EncodingSpecificOperations();
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<a link="impl-aarch32.R.write.1" file="shared_pseudocode.xml" hover="accessor: R[integer n] = bits(32) value">R</a>[d]<msbit:lsbit> = <a link="impl-aarch32.R.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) R[integer n]">R</a>[n]<(msbit-lsbit):0>;
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// Other bits of R[d] are unchanged</pstext>
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</ps>
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</ps_section>
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</instructionsection>
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