607 lines
37 KiB
XML
607 lines
37 KiB
XML
<?xml version="1.0" encoding="utf-8"?>
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<?xml-stylesheet type="text/xsl" encoding="UTF-8" href="iform.xsl" version="1.0"?>
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<!DOCTYPE instructionsection PUBLIC "-//ARM//DTD instructionsection //EN" "iform-p.dtd">
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<!-- Copyright (c) 2010-2022 Arm Limited or its affiliates. All rights reserved. -->
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<!-- This document is Non-Confidential. This document may only be used and distributed in accordance with the terms of the agreement entered into by Arm and the party that Arm delivered this document to. -->
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<instructionsection id="AND_r" title="AND, ANDS (register) -- AArch32" type="instruction">
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<docvars>
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<docvar key="instr-class" value="general" />
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</docvars>
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<heading>AND, ANDS (register)</heading>
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<desc>
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<brief>
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<para>Bitwise AND (register)</para>
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</brief>
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<authored>
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<para>Bitwise AND (register) performs a bitwise AND of a register value and an optionally-shifted register value, and writes the result to the destination register.</para>
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<para>If the destination register is not the PC, the ANDS variant of the instruction updates the condition flags based on the result.</para>
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<para>The field descriptions for <syntax><Rd></syntax> identify the encodings where the PC is permitted as the destination register. Arm deprecates any use of these encodings. However, when the destination register is the PC:</para>
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<list type="unordered">
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<listitem><content>The AND variant of the instruction is an interworking branch, see <xref linkend="BEICJFEH">Pseudocode description of operations on the AArch32 general-purpose registers and the PC</xref>.</content></listitem>
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<listitem><content>The ANDS variant of the instruction performs an exception return without the use of the stack. In this case:<list type="unordered"><listitem><content>The PE branches to the address written to the PC, and restores <xref linkend="BEIDIGBH">PSTATE</xref> from SPSR_<current_mode>.</content></listitem><listitem><content>The PE checks SPSR_<current_mode> for an illegal return event. See <xref linkend="CHDDDJDB">Illegal return events from AArch32 state</xref>.</content></listitem><listitem><content>The instruction is <arm-defined-word>undefined</arm-defined-word> in Hyp mode.</content></listitem><listitem><content>The instruction is <arm-defined-word>constrained unpredictable</arm-defined-word> in User mode and System mode.</content></listitem></list></content></listitem>
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</list>
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</authored>
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<encodingnotes>
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<para>For more information about the <arm-defined-word>constrained unpredictable</arm-defined-word> behavior, see <xref linkend="CJAEGDJC">Architectural Constraints on UNPREDICTABLE behaviors</xref>.</para>
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</encodingnotes>
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<syntaxnotes>
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<para>In T32 assembly:</para>
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<list type="unordered">
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<listitem><content>Outside an IT block, if <syntax>ANDS <Rd>, <Rn>, <Rd></syntax> has <syntax><Rd></syntax> and <syntax><Rn></syntax> both in the range R0-R7, it is assembled using encoding T1 as though <syntax>ANDS <Rd>, <Rn></syntax> had been written.</content></listitem>
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<listitem><content>Inside an IT block, if <syntax>AND<c> <Rd>, <Rn>, <Rd></syntax> has <syntax><Rd></syntax> and <syntax><Rn></syntax> both in the range R0-R7, it is assembled using encoding T1 as though <syntax>AND<c> <Rd>, <Rn></syntax> had been written.</content></listitem>
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</list>
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<para>To prevent either of these happening, use the <syntax>.W</syntax> qualifier.</para>
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</syntaxnotes>
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</desc>
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<operationalnotes>
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<para>If CPSR.DIT is 1 and this instruction does not use R15 as either its source or destination:</para>
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<list type="unordered">
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<listitem><content>The execution time of this instruction is independent of:<list type="unordered"><listitem><content>The values of the data supplied in any of its registers.</content></listitem><listitem><content>The values of the NZCV flags.</content></listitem></list></content></listitem>
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<listitem><content>The response of this instruction to asynchronous exceptions does not vary based on:<list type="unordered"><listitem><content>The values of the data supplied in any of its registers.</content></listitem><listitem><content>The values of the NZCV flags.</content></listitem></list></content></listitem>
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</list>
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</operationalnotes>
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<alias_list howmany="0"></alias_list>
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<classes>
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<classesintro count="3">
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<txt>It has encodings from the following instruction sets:</txt>
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<txt> A32 (</txt>
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<a href="#iclass_a1">A1</a>
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<txt>)</txt>
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<txt> and </txt>
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<txt> T32 (</txt>
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<a href="#iclass_t1">T1</a>
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<txt> and </txt>
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<a href="#iclass_t2">T2</a>
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<txt>)</txt>
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<txt>.</txt>
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</classesintro>
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<iclass name="A1" oneof="3" id="iclass_a1" no_encodings="4" isa="A32">
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<docvars>
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<docvar key="armarmheading" value="A1" />
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<docvar key="instr-class" value="general" />
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<docvar key="isa" value="A32" />
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</docvars>
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<iclassintro count="4"></iclassintro>
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<regdiagram form="32" psname="aarch32/instrs/AND_r/A1_A.txt" tworows="1">
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<box hibit="31" width="4" name="cond" usename="1" settings="4" constraint="!= 1111">
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<c colspan="4">!= 1111</c>
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</box>
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<box hibit="27" width="4" settings="4">
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<c>0</c>
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<c>0</c>
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<c>0</c>
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<c>0</c>
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</box>
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<box hibit="23" width="3" name="opc" settings="3">
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<c>0</c>
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<c>0</c>
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<c>0</c>
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</box>
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<box hibit="20" name="S" usename="1">
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<c></c>
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</box>
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<box hibit="19" width="4" name="Rn" usename="1">
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<c colspan="4"></c>
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</box>
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<box hibit="15" width="4" name="Rd" usename="1">
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<c colspan="4"></c>
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</box>
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<box hibit="11" width="5" name="imm5" usename="1">
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<c colspan="5"></c>
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</box>
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<box hibit="6" width="2" name="stype" usename="1">
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<c colspan="2"></c>
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</box>
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<box hibit="4" settings="1">
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<c>0</c>
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</box>
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<box hibit="3" width="4" name="Rm" usename="1">
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<c colspan="4"></c>
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</box>
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</regdiagram>
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<encoding name="AND_r_A1_RRX" oneofinclass="4" oneof="9" label="AND, rotate right with extend" bitdiffs="S == 0 && imm5 == 00000 && stype == 11">
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<docvars>
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<docvar key="armarmheading" value="A1" />
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<docvar key="instr-class" value="general" />
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<docvar key="isa" value="A32" />
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<docvar key="mnemonic" value="AND" />
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<docvar key="mnemonic-shift-type" value="AND-rrx" />
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<docvar key="shift-type" value="rrx" />
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</docvars>
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<box hibit="20" width="1" name="S">
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<c>0</c>
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</box>
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<box hibit="11" width="5" name="imm5">
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<c>0</c>
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<c>0</c>
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<c>0</c>
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<c>0</c>
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<c>0</c>
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</box>
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<box hibit="6" width="2" name="stype">
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<c>1</c>
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<c>1</c>
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</box>
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<asmtemplate><text>AND</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}"><c></a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}"><q></a><text>}</text><text> </text><text>{</text><a link="sa_rd_1" hover="General-purpose destination register (field "Rd")"><Rd></a><text>,</text><text>}</text><text> </text><a link="sa_rn_1" hover="First general-purpose source register (field "Rn")"><Rn></a><text>, </text><a link="sa_rm_1" hover="Second general-purpose source register (field "Rm")"><Rm></a><text>, RRX</text></asmtemplate>
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</encoding>
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<encoding name="AND_r_A1" oneofinclass="4" oneof="9" label="AND, shift or rotate by value" bitdiffs="S == 0 && !(imm5 == 00000 && stype == 11)">
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<docvars>
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<docvar key="armarmheading" value="A1" />
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<docvar key="instr-class" value="general" />
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<docvar key="isa" value="A32" />
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<docvar key="mnemonic" value="AND" />
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<docvar key="mnemonic-shift-type" value="AND-shift-no-rrx" />
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<docvar key="shift-type" value="shift-no-rrx" />
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</docvars>
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<box hibit="20" width="1" name="S">
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<c>0</c>
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</box>
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<box hibit="11" width="7" name="imm5:stype">
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<c>Z</c>
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<c>Z</c>
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<c>Z</c>
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<c>Z</c>
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<c>Z</c>
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<c>N</c>
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<c>N</c>
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</box>
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<asmtemplate><text>AND</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}"><c></a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}"><q></a><text>}</text><text> </text><text>{</text><a link="sa_rd_1" hover="General-purpose destination register (field "Rd")"><Rd></a><text>,</text><text>}</text><text> </text><a link="sa_rn_1" hover="First general-purpose source register (field "Rn")"><Rn></a><text>, </text><a link="sa_rm_1" hover="Second general-purpose source register (field "Rm")"><Rm></a><text> </text><text>{</text><text>, </text><a link="sa_shift" hover="Type of shift applied to second source register (field "stype") [ASR,LSL,LSR,ROR]"><shift></a><text> #</text><a link="sa_amount_1" hover="Shift amount [1-31 (when <shift> = LSL or ROR) or 1 to 32 (when <shift> = LSR or ASR) (field "imm5")"><amount></a><text>}</text></asmtemplate>
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</encoding>
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<encoding name="ANDS_r_A1_RRX" oneofinclass="4" oneof="9" label="ANDS, rotate right with extend" bitdiffs="S == 1 && imm5 == 00000 && stype == 11">
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<docvars>
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<docvar key="armarmheading" value="A1" />
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<docvar key="instr-class" value="general" />
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<docvar key="isa" value="A32" />
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<docvar key="mnemonic" value="ANDS" />
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<docvar key="mnemonic-shift-type" value="ANDS-rrx" />
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<docvar key="shift-type" value="rrx" />
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</docvars>
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<box hibit="20" width="1" name="S">
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<c>1</c>
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</box>
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<box hibit="11" width="5" name="imm5">
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<c>0</c>
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<c>0</c>
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<c>0</c>
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<c>0</c>
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<c>0</c>
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</box>
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<box hibit="6" width="2" name="stype">
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<c>1</c>
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<c>1</c>
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</box>
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<asmtemplate><text>ANDS</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}"><c></a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}"><q></a><text>}</text><text> </text><text>{</text><a link="sa_rd_1" hover="General-purpose destination register (field "Rd")"><Rd></a><text>,</text><text>}</text><text> </text><a link="sa_rn_1" hover="First general-purpose source register (field "Rn")"><Rn></a><text>, </text><a link="sa_rm_1" hover="Second general-purpose source register (field "Rm")"><Rm></a><text>, RRX</text></asmtemplate>
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</encoding>
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<encoding name="ANDS_r_A1" oneofinclass="4" oneof="9" label="ANDS, shift or rotate by value" bitdiffs="S == 1 && !(imm5 == 00000 && stype == 11)">
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<docvars>
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<docvar key="armarmheading" value="A1" />
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<docvar key="instr-class" value="general" />
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<docvar key="isa" value="A32" />
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<docvar key="mnemonic" value="ANDS" />
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<docvar key="mnemonic-shift-type" value="ANDS-shift-no-rrx" />
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<docvar key="shift-type" value="shift-no-rrx" />
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</docvars>
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<box hibit="20" width="1" name="S">
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<c>1</c>
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</box>
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<box hibit="11" width="7" name="imm5:stype">
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<c>Z</c>
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<c>Z</c>
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<c>Z</c>
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<c>Z</c>
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<c>Z</c>
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<c>N</c>
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<c>N</c>
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</box>
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<asmtemplate><text>ANDS</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}"><c></a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}"><q></a><text>}</text><text> </text><text>{</text><a link="sa_rd_1" hover="General-purpose destination register (field "Rd")"><Rd></a><text>,</text><text>}</text><text> </text><a link="sa_rn_1" hover="First general-purpose source register (field "Rn")"><Rn></a><text>, </text><a link="sa_rm_1" hover="Second general-purpose source register (field "Rm")"><Rm></a><text> </text><text>{</text><text>, </text><a link="sa_shift" hover="Type of shift applied to second source register (field "stype") [ASR,LSL,LSR,ROR]"><shift></a><text> #</text><a link="sa_amount_1" hover="Shift amount [1-31 (when <shift> = LSL or ROR) or 1 to 32 (when <shift> = LSR or ASR) (field "imm5")"><amount></a><text>}</text></asmtemplate>
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</encoding>
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<ps_section howmany="1">
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<ps name="aarch32/instrs/AND_r/A1_A.txt" mylink="aarch32.instrs.AND_r.A1_A.txt" enclabels="" sections="1" secttype="noheading">
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<pstext mayhavelinks="1" section="Decode" rep_section="decode">d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rd); n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rn); m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rm); setflags = (S == '1');
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(shift_t, shift_n) = <a link="impl-aarch32.DecodeImmShift.2" file="shared_pseudocode.xml" hover="function: (SRType, integer) DecodeImmShift(bits(2) srtype, bits(5) imm5)">DecodeImmShift</a>(stype, imm5);</pstext>
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</ps>
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</ps_section>
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</iclass>
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<iclass name="T1" oneof="3" id="iclass_t1" no_encodings="1" isa="T32">
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<docvars>
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<docvar key="armarmheading" value="T1" />
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<docvar key="instr-class" value="general" />
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<docvar key="isa" value="T32" />
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<docvar key="mnemonic" value="AND" />
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</docvars>
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<iclassintro count="1"></iclassintro>
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<regdiagram form="16" psname="aarch32/instrs/AND_r/T1_A.txt">
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<box hibit="31" width="6" settings="6">
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<c>0</c>
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<c>1</c>
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<c>0</c>
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<c>0</c>
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<c>0</c>
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<c>0</c>
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</box>
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<box hibit="25" width="4" name="op" settings="4">
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<c>0</c>
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<c>0</c>
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<c>0</c>
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<c>0</c>
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</box>
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<box hibit="21" width="3" name="Rm" usename="1">
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<c colspan="3"></c>
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</box>
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<box hibit="18" width="3" name="Rdn" usename="1">
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<c colspan="3"></c>
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</box>
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</regdiagram>
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<encoding name="AND_r_T1" oneofinclass="1" oneof="9" label="T1">
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<docvars>
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<docvar key="armarmheading" value="T1" />
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<docvar key="instr-class" value="general" />
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<docvar key="isa" value="T32" />
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<docvar key="mnemonic" value="AND" />
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</docvars>
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<asmtemplate comment="Inside IT block"><text>AND</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}"><c></a><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}"><q></a><text>}</text><text> </text><text>{</text><a link="sa_rdn" hover="First general-purpose source register and the destination register (field "Rdn")"><Rdn></a><text>,</text><text>}</text><text> </text><a link="sa_rdn" hover="First general-purpose source register and the destination register (field "Rdn")"><Rdn></a><text>, </text><a link="sa_rm" hover="Second general-purpose source register (field "Rm")"><Rm></a></asmtemplate>
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<asmtemplate comment="Outside IT block"><text>ANDS</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}"><q></a><text>}</text><text> </text><text>{</text><a link="sa_rdn" hover="First general-purpose source register and the destination register (field "Rdn")"><Rdn></a><text>,</text><text>}</text><text> </text><a link="sa_rdn" hover="First general-purpose source register and the destination register (field "Rdn")"><Rdn></a><text>, </text><a link="sa_rm" hover="Second general-purpose source register (field "Rm")"><Rm></a></asmtemplate>
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</encoding>
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<ps_section howmany="1">
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<ps name="aarch32/instrs/AND_r/T1_A.txt" mylink="aarch32.instrs.AND_r.T1_A.txt" enclabels="" sections="1" secttype="noheading">
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<pstext mayhavelinks="1" section="Decode" rep_section="decode">d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rdn); n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rdn); m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rm); setflags = !<a link="impl-aarch32.InITBlock.0" file="shared_pseudocode.xml" hover="function: boolean InITBlock()">InITBlock</a>();
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(shift_t, shift_n) = (<a link="SRType_LSL" file="shared_pseudocode.xml" hover="enumeration SRType {SRType_LSL, SRType_LSR, SRType_ASR, SRType_ROR, SRType_RRX}">SRType_LSL</a>, 0);</pstext>
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</ps>
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</ps_section>
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</iclass>
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<iclass name="T2" oneof="3" id="iclass_t2" no_encodings="4" isa="T32">
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<docvars>
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<docvar key="armarmheading" value="T2" />
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<docvar key="instr-class" value="general" />
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<docvar key="isa" value="T32" />
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</docvars>
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<iclassintro count="4"></iclassintro>
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<regdiagram form="16x2" psname="aarch32/instrs/AND_r/T2_A.txt">
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<box hibit="31" width="7" settings="7">
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<c>1</c>
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<c>1</c>
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<c>1</c>
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<c>0</c>
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<c>1</c>
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<c>0</c>
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<c>1</c>
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</box>
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<box hibit="24" width="4" name="op1" settings="4">
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<c>0</c>
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<c>0</c>
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<c>0</c>
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<c>0</c>
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</box>
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<box hibit="20" name="S" usename="1">
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<c></c>
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</box>
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<box hibit="19" width="4" name="Rn" usename="1">
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<c colspan="4"></c>
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</box>
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<box hibit="15" settings="1">
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<c>(0)</c>
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</box>
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<box hibit="14" width="3" name="imm3" usename="1">
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<c colspan="3"></c>
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</box>
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<box hibit="11" width="4" name="Rd" usename="1">
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<c colspan="4"></c>
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</box>
|
|
<box hibit="7" width="2" name="imm2" usename="1">
|
|
<c colspan="2"></c>
|
|
</box>
|
|
<box hibit="5" width="2" name="stype" usename="1">
|
|
<c colspan="2"></c>
|
|
</box>
|
|
<box hibit="3" width="4" name="Rm" usename="1">
|
|
<c colspan="4"></c>
|
|
</box>
|
|
</regdiagram>
|
|
<encoding name="AND_r_T2_RRX" oneofinclass="4" oneof="9" label="AND, rotate right with extend" bitdiffs="S == 0 && imm3 == 000 && imm2 == 00 && stype == 11">
|
|
<docvars>
|
|
<docvar key="armarmheading" value="T2" />
|
|
<docvar key="instr-class" value="general" />
|
|
<docvar key="isa" value="T32" />
|
|
<docvar key="mnemonic" value="AND" />
|
|
<docvar key="mnemonic-shift-type" value="AND-rrx" />
|
|
<docvar key="shift-type" value="rrx" />
|
|
</docvars>
|
|
<box hibit="20" width="1" name="S">
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="14" width="3" name="imm3">
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="7" width="2" name="imm2">
|
|
<c>0</c>
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="5" width="2" name="stype">
|
|
<c>1</c>
|
|
<c>1</c>
|
|
</box>
|
|
<asmtemplate><text>AND</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}"><c></a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}"><q></a><text>}</text><text> </text><text>{</text><a link="sa_rd" hover="General-purpose destination register (field "Rd")"><Rd></a><text>,</text><text>}</text><text> </text><a link="sa_rn" hover="First general-purpose source register (field "Rn")"><Rn></a><text>, </text><a link="sa_rm" hover="Second general-purpose source register (field "Rm")"><Rm></a><text>, RRX</text></asmtemplate>
|
|
</encoding>
|
|
<encoding name="AND_r_T2" oneofinclass="4" oneof="9" label="AND, shift or rotate by value" bitdiffs="S == 0 && !(imm3 == 000 && imm2 == 00 && stype == 11)">
|
|
<docvars>
|
|
<docvar key="armarmheading" value="T2" />
|
|
<docvar key="instr-class" value="general" />
|
|
<docvar key="isa" value="T32" />
|
|
<docvar key="mnemonic" value="AND" />
|
|
<docvar key="mnemonic-shift-type" value="AND-shift-no-rrx" />
|
|
<docvar key="shift-type" value="shift-no-rrx" />
|
|
</docvars>
|
|
<box hibit="20" width="1" name="S">
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="14" width="11" name="imm3:imm2:stype">
|
|
<c>Z</c>
|
|
<c>Z</c>
|
|
<c>Z</c>
|
|
<c>Z</c>
|
|
<c>Z</c>
|
|
<c>N</c>
|
|
<c>N</c>
|
|
</box>
|
|
<asmtemplate comment="Inside IT block, and <Rd>, <Rn>, <Rm> can be represented in T1"><text>AND</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}"><c></a><text>.W </text><text>{</text><a link="sa_rd" hover="General-purpose destination register (field "Rd")"><Rd></a><text>,</text><text>}</text><text> </text><a link="sa_rn" hover="First general-purpose source register (field "Rn")"><Rn></a><text>, </text><a link="sa_rm" hover="Second general-purpose source register (field "Rm")"><Rm></a></asmtemplate>
|
|
<asmtemplate><text>AND</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}"><c></a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}"><q></a><text>}</text><text> </text><text>{</text><a link="sa_rd" hover="General-purpose destination register (field "Rd")"><Rd></a><text>,</text><text>}</text><text> </text><a link="sa_rn" hover="First general-purpose source register (field "Rn")"><Rn></a><text>, </text><a link="sa_rm" hover="Second general-purpose source register (field "Rm")"><Rm></a><text> </text><text>{</text><text>, </text><a link="sa_shift" hover="Type of shift applied to second source register (field "stype") [ASR,LSL,LSR,ROR]"><shift></a><text> #</text><a link="sa_amount" hover="Shift amount [1-31 (when <shift> = LSL or ROR) or 1 to 32 (when <shift> = LSR or ASR)] (field "imm3:imm2")"><amount></a><text>}</text></asmtemplate>
|
|
</encoding>
|
|
<encoding name="ANDS_r_T2_RRX" oneofinclass="4" oneof="9" label="ANDS, rotate right with extend" bitdiffs="S == 1 && imm3 == 000 && Rd != 1111 && imm2 == 00 && stype == 11">
|
|
<docvars>
|
|
<docvar key="armarmheading" value="T2" />
|
|
<docvar key="instr-class" value="general" />
|
|
<docvar key="isa" value="T32" />
|
|
<docvar key="mnemonic" value="ANDS" />
|
|
<docvar key="mnemonic-shift-type" value="ANDS-rrx" />
|
|
<docvar key="shift-type" value="rrx" />
|
|
</docvars>
|
|
<box hibit="20" width="1" name="S">
|
|
<c>1</c>
|
|
</box>
|
|
<box hibit="14" width="3" name="imm3">
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="11" width="4" name="Rd">
|
|
<c>N</c>
|
|
<c>N</c>
|
|
<c>N</c>
|
|
<c>N</c>
|
|
</box>
|
|
<box hibit="7" width="2" name="imm2">
|
|
<c>0</c>
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="5" width="2" name="stype">
|
|
<c>1</c>
|
|
<c>1</c>
|
|
</box>
|
|
<asmtemplate><text>ANDS</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}"><c></a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}"><q></a><text>}</text><text> </text><text>{</text><a link="sa_rd" hover="General-purpose destination register (field "Rd")"><Rd></a><text>,</text><text>}</text><text> </text><a link="sa_rn" hover="First general-purpose source register (field "Rn")"><Rn></a><text>, </text><a link="sa_rm" hover="Second general-purpose source register (field "Rm")"><Rm></a><text>, RRX</text></asmtemplate>
|
|
</encoding>
|
|
<encoding name="ANDS_r_T2" oneofinclass="4" oneof="9" label="ANDS, shift or rotate by value" bitdiffs="S == 1 && !(imm3 == 000 && imm2 == 00 && stype == 11) && Rd != 1111">
|
|
<docvars>
|
|
<docvar key="armarmheading" value="T2" />
|
|
<docvar key="instr-class" value="general" />
|
|
<docvar key="isa" value="T32" />
|
|
<docvar key="mnemonic" value="ANDS" />
|
|
<docvar key="mnemonic-shift-type" value="ANDS-shift-no-rrx" />
|
|
<docvar key="shift-type" value="shift-no-rrx" />
|
|
</docvars>
|
|
<box hibit="20" width="1" name="S">
|
|
<c>1</c>
|
|
</box>
|
|
<box hibit="14" width="11" name="imm3:imm2:stype">
|
|
<c>Z</c>
|
|
<c>Z</c>
|
|
<c>Z</c>
|
|
<c>Z</c>
|
|
<c>Z</c>
|
|
<c>N</c>
|
|
<c>N</c>
|
|
</box>
|
|
<box hibit="11" width="4" name="Rd">
|
|
<c>N</c>
|
|
<c>N</c>
|
|
<c>N</c>
|
|
<c>N</c>
|
|
</box>
|
|
<asmtemplate comment="Outside IT block, and <Rd>, <Rn>, <Rm> can be represented in T1"><text>ANDS.W </text><text>{</text><a link="sa_rd" hover="General-purpose destination register (field "Rd")"><Rd></a><text>,</text><text>}</text><text> </text><a link="sa_rn" hover="First general-purpose source register (field "Rn")"><Rn></a><text>, </text><a link="sa_rm" hover="Second general-purpose source register (field "Rm")"><Rm></a></asmtemplate>
|
|
<asmtemplate><text>ANDS</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}"><c></a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}"><q></a><text>}</text><text> </text><text>{</text><a link="sa_rd" hover="General-purpose destination register (field "Rd")"><Rd></a><text>,</text><text>}</text><text> </text><a link="sa_rn" hover="First general-purpose source register (field "Rn")"><Rn></a><text>, </text><a link="sa_rm" hover="Second general-purpose source register (field "Rm")"><Rm></a><text> </text><text>{</text><text>, </text><a link="sa_shift" hover="Type of shift applied to second source register (field "stype") [ASR,LSL,LSR,ROR]"><shift></a><text> #</text><a link="sa_amount" hover="Shift amount [1-31 (when <shift> = LSL or ROR) or 1 to 32 (when <shift> = LSR or ASR)] (field "imm3:imm2")"><amount></a><text>}</text></asmtemplate>
|
|
</encoding>
|
|
<ps_section howmany="1">
|
|
<ps name="aarch32/instrs/AND_r/T2_A.txt" mylink="aarch32.instrs.AND_r.T2_A.txt" enclabels="" sections="1" secttype="noheading">
|
|
<pstext mayhavelinks="1" section="Decode" rep_section="decode">if Rd == '1111' && S == '1' then SEE "TST (register)";
|
|
d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rd); n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rn); m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rm); setflags = (S == '1');
|
|
(shift_t, shift_n) = <a link="impl-aarch32.DecodeImmShift.2" file="shared_pseudocode.xml" hover="function: (SRType, integer) DecodeImmShift(bits(2) srtype, bits(5) imm5)">DecodeImmShift</a>(stype, imm3:imm2);
|
|
if (d == 15 && !setflags) || n == 15 || m == 15 then UNPREDICTABLE;
|
|
// Armv8-A removes UNPREDICTABLE for R13</pstext>
|
|
</ps>
|
|
</ps_section>
|
|
</iclass>
|
|
</classes>
|
|
<explanations scope="all">
|
|
<explanation enclist="AND_r_A1, AND_r_T1, AND_r_T2" symboldefcount="1">
|
|
<symbol link="sa_c"><c></symbol>
|
|
<account encodedin="">
|
|
<intro>
|
|
<para>See <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
|
|
</intro>
|
|
</account>
|
|
</explanation>
|
|
<explanation enclist="AND_r_A1, AND_r_T1, AND_r_T2" symboldefcount="1">
|
|
<symbol link="sa_q"><q></symbol>
|
|
<account encodedin="">
|
|
<intro>
|
|
<para>See <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
|
|
</intro>
|
|
</account>
|
|
</explanation>
|
|
<explanation enclist="AND_r_T1" symboldefcount="1">
|
|
<symbol link="sa_rdn"><Rdn></symbol>
|
|
<account encodedin="Rdn">
|
|
<intro>
|
|
<para>Is the first general-purpose source register and the destination register, encoded in the "Rdn" field.</para>
|
|
</intro>
|
|
</account>
|
|
</explanation>
|
|
<explanation enclist="AND_r_A1" symboldefcount="1">
|
|
<symbol link="sa_rd_1"><Rd></symbol>
|
|
<account encodedin="Rd">
|
|
<docvars>
|
|
<docvar key="armarmheading" value="A1" />
|
|
<docvar key="isa" value="A32" />
|
|
</docvars>
|
|
<intro>
|
|
<para>For encoding A1: is the general-purpose destination register, encoded in the "Rd" field. If omitted, this register is the same as <syntax><Rn></syntax>. Arm deprecates using the PC as the destination register, but if the PC is used:</para>
|
|
<list type="unordered">
|
|
<listitem><content>For the AND variant, the instruction is a branch to the address calculated by the operation. This is an interworking branch, see <xref linkend="BEICJFEH">Pseudocode description of operations on the AArch32 general-purpose registers and the PC</xref>.</content></listitem>
|
|
<listitem><content>For the ANDS variant, the instruction performs an exception return, that restores <xref linkend="BEIDIGBH">PSTATE</xref> from SPSR_<current_mode>.</content></listitem>
|
|
</list>
|
|
</intro>
|
|
</account>
|
|
</explanation>
|
|
<explanation enclist="AND_r_T2" symboldefcount="2">
|
|
<symbol link="sa_rd"><Rd></symbol>
|
|
<account encodedin="Rd">
|
|
<docvars>
|
|
<docvar key="armarmheading" value="T2" />
|
|
<docvar key="isa" value="T32" />
|
|
</docvars>
|
|
<intro>
|
|
<para>For encoding T2: is the general-purpose destination register, encoded in the "Rd" field. If omitted, this register is the same as <syntax><Rn></syntax>.</para>
|
|
</intro>
|
|
</account>
|
|
</explanation>
|
|
<explanation enclist="AND_r_A1" symboldefcount="1">
|
|
<symbol link="sa_rn_1"><Rn></symbol>
|
|
<account encodedin="Rn">
|
|
<docvars>
|
|
<docvar key="armarmheading" value="A1" />
|
|
<docvar key="isa" value="A32" />
|
|
</docvars>
|
|
<intro>
|
|
<para>For encoding A1: is the first general-purpose source register, encoded in the "Rn" field. The PC can be used, but this is deprecated.</para>
|
|
</intro>
|
|
</account>
|
|
</explanation>
|
|
<explanation enclist="AND_r_T2" symboldefcount="2">
|
|
<symbol link="sa_rn"><Rn></symbol>
|
|
<account encodedin="Rn">
|
|
<docvars>
|
|
<docvar key="armarmheading" value="T2" />
|
|
<docvar key="isa" value="T32" />
|
|
</docvars>
|
|
<intro>
|
|
<para>For encoding T2: is the first general-purpose source register, encoded in the "Rn" field.</para>
|
|
</intro>
|
|
</account>
|
|
</explanation>
|
|
<explanation enclist="AND_r_A1" symboldefcount="1">
|
|
<symbol link="sa_rm_1"><Rm></symbol>
|
|
<account encodedin="Rm">
|
|
<docvars>
|
|
<docvar key="armarmheading" value="A1" />
|
|
<docvar key="isa" value="A32" />
|
|
<docvar key="mnemonic-shift-type" value="AND-shift-no-rrx" />
|
|
<docvar key="shift-type" value="shift-no-rrx" />
|
|
</docvars>
|
|
<intro>
|
|
<para>For encoding A1: is the second general-purpose source register, encoded in the "Rm" field. The PC can be used, but this is deprecated.</para>
|
|
</intro>
|
|
</account>
|
|
</explanation>
|
|
<explanation enclist="AND_r_T1, AND_r_T2" symboldefcount="2">
|
|
<symbol link="sa_rm"><Rm></symbol>
|
|
<account encodedin="Rm">
|
|
<docvars>
|
|
<docvar key="isa" value="T32" />
|
|
</docvars>
|
|
<intro>
|
|
<para>For encoding T1 and T2: is the second general-purpose source register, encoded in the "Rm" field.</para>
|
|
</intro>
|
|
</account>
|
|
</explanation>
|
|
<explanation enclist="AND_r_A1, AND_r_T2" symboldefcount="1">
|
|
<symbol link="sa_shift"><shift></symbol>
|
|
<definition encodedin="stype">
|
|
<intro>Is the type of shift to be applied to the second source register, </intro>
|
|
<table class="valuetable">
|
|
<tgroup cols="2">
|
|
<thead>
|
|
<row>
|
|
<entry class="bitfield">stype</entry>
|
|
<entry class="symbol"><shift></entry>
|
|
</row>
|
|
</thead>
|
|
<tbody>
|
|
<row>
|
|
<entry class="bitfield">00</entry>
|
|
<entry class="symbol">LSL</entry>
|
|
</row>
|
|
<row>
|
|
<entry class="bitfield">01</entry>
|
|
<entry class="symbol">LSR</entry>
|
|
</row>
|
|
<row>
|
|
<entry class="bitfield">10</entry>
|
|
<entry class="symbol">ASR</entry>
|
|
</row>
|
|
<row>
|
|
<entry class="bitfield">11</entry>
|
|
<entry class="symbol">ROR</entry>
|
|
</row>
|
|
</tbody>
|
|
</tgroup>
|
|
</table>
|
|
</definition>
|
|
</explanation>
|
|
<explanation enclist="AND_r_A1" symboldefcount="1">
|
|
<symbol link="sa_amount_1"><amount></symbol>
|
|
<account encodedin="imm5">
|
|
<docvars>
|
|
<docvar key="armarmheading" value="A1" />
|
|
<docvar key="isa" value="A32" />
|
|
</docvars>
|
|
<intro>
|
|
<para>For encoding A1: is the shift amount, in the range 1 to 31 (when <shift> = LSL or ROR) or 1 to 32 (when <shift> = LSR or ASR) encoded in the "imm5" field as <amount> modulo 32.</para>
|
|
</intro>
|
|
</account>
|
|
</explanation>
|
|
<explanation enclist="AND_r_T2" symboldefcount="2">
|
|
<symbol link="sa_amount"><amount></symbol>
|
|
<account encodedin="imm3:imm2">
|
|
<docvars>
|
|
<docvar key="armarmheading" value="T2" />
|
|
<docvar key="isa" value="T32" />
|
|
</docvars>
|
|
<intro>
|
|
<para>For encoding T2: is the shift amount, in the range 1 to 31 (when <shift> = LSL or ROR) or 1 to 32 (when <shift> = LSR or ASR), encoded in the "imm3:imm2" field as <amount> modulo 32.</para>
|
|
</intro>
|
|
</account>
|
|
</explanation>
|
|
</explanations>
|
|
<ps_section howmany="1">
|
|
<ps name="aarch32/instrs/AND_r/Op_A.txt" mylink="execute" enclabels="" sections="1" secttype="Operation">
|
|
<pstext mayhavelinks="1" section="Execute" rep_section="execute">if <a link="impl-aarch32.ConditionPassed.0" file="shared_pseudocode.xml" hover="function: boolean ConditionPassed()">ConditionPassed</a>() then
|
|
EncodingSpecificOperations();
|
|
(shifted, carry) = <a link="impl-aarch32.Shift_C.4" file="shared_pseudocode.xml" hover="function: (bits(N), bit) Shift_C(bits(N) value, SRType srtype, integer amount, bit carry_in)">Shift_C</a>(<a link="impl-aarch32.R.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) R[integer n]">R</a>[m], shift_t, shift_n, PSTATE.C);
|
|
result = <a link="impl-aarch32.R.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) R[integer n]">R</a>[n] AND shifted;
|
|
if d == 15 then // Can only occur for A32 encoding
|
|
if setflags then
|
|
<a link="impl-aarch32.ALUExceptionReturn.1" file="shared_pseudocode.xml" hover="function: ALUExceptionReturn(bits(32) address)">ALUExceptionReturn</a>(result);
|
|
else
|
|
<a link="impl-aarch32.ALUWritePC.1" file="shared_pseudocode.xml" hover="function: ALUWritePC(bits(32) address)">ALUWritePC</a>(result);
|
|
else
|
|
<a link="impl-aarch32.R.write.1" file="shared_pseudocode.xml" hover="accessor: R[integer n] = bits(32) value">R</a>[d] = result;
|
|
if setflags then
|
|
PSTATE.N = result<31>;
|
|
PSTATE.Z = <a link="impl-shared.IsZeroBit.1" file="shared_pseudocode.xml" hover="function: bit IsZeroBit(bits(N) x)">IsZeroBit</a>(result);
|
|
PSTATE.C = carry;
|
|
// PSTATE.V unchanged</pstext>
|
|
</ps>
|
|
</ps_section>
|
|
</instructionsection>
|