314 lines
18 KiB
XML
314 lines
18 KiB
XML
<?xml version="1.0" encoding="utf-8"?>
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<?xml-stylesheet type="text/xsl" encoding="UTF-8" href="iform.xsl" version="1.0"?>
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<!DOCTYPE instructionsection PUBLIC "-//ARM//DTD instructionsection //EN" "iform-p.dtd">
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<!-- Copyright (c) 2010-2022 Arm Limited or its affiliates. All rights reserved. -->
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<!-- This document is Non-Confidential. This document may only be used and distributed in accordance with the terms of the agreement entered into by Arm and the party that Arm delivered this document to. -->
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<instructionsection id="AND_i" title="AND, ANDS (immediate) -- AArch32" type="instruction">
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<docvars>
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<docvar key="instr-class" value="general" />
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</docvars>
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<heading>AND, ANDS (immediate)</heading>
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<desc>
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<brief>
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<para>Bitwise AND (immediate)</para>
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</brief>
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<authored>
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<para>Bitwise AND (immediate) performs a bitwise AND of a register value and an immediate value, and writes the result to the destination register.</para>
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<para>If the destination register is not the PC, the ANDS variant of the instruction updates the condition flags based on the result.</para>
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<para>The field descriptions for <syntax><Rd></syntax> identify the encodings where the PC is permitted as the destination register. Arm deprecates any use of these encodings. However, when the destination register is the PC:</para>
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<list type="unordered">
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<listitem><content>The AND variant of the instruction is an interworking branch, see <xref linkend="BEICJFEH">Pseudocode description of operations on the AArch32 general-purpose registers and the PC</xref>.</content></listitem>
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<listitem><content>The ANDS variant of the instruction performs an exception return without the use of the stack. In this case:<list type="unordered"><listitem><content>The PE branches to the address written to the PC, and restores <xref linkend="BEIDIGBH">PSTATE</xref> from SPSR_<current_mode>.</content></listitem><listitem><content>The PE checks SPSR_<current_mode> for an illegal return event. See <xref linkend="CHDDDJDB">Illegal return events from AArch32 state</xref>.</content></listitem><listitem><content>The instruction is <arm-defined-word>undefined</arm-defined-word> in Hyp mode.</content></listitem><listitem><content>The instruction is <arm-defined-word>constrained unpredictable</arm-defined-word> in User mode and System mode.</content></listitem></list></content></listitem>
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</list>
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</authored>
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<encodingnotes>
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<para>For more information about the <arm-defined-word>constrained unpredictable</arm-defined-word> behavior, see <xref linkend="CJAEGDJC">Architectural Constraints on UNPREDICTABLE behaviors</xref>.</para>
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</encodingnotes>
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</desc>
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<operationalnotes>
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<para>If CPSR.DIT is 1 and this instruction does not use R15 as either its source or destination:</para>
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<list type="unordered">
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<listitem><content>The execution time of this instruction is independent of:<list type="unordered"><listitem><content>The values of the data supplied in any of its registers.</content></listitem><listitem><content>The values of the NZCV flags.</content></listitem></list></content></listitem>
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<listitem><content>The response of this instruction to asynchronous exceptions does not vary based on:<list type="unordered"><listitem><content>The values of the data supplied in any of its registers.</content></listitem><listitem><content>The values of the NZCV flags.</content></listitem></list></content></listitem>
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</list>
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</operationalnotes>
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<alias_list howmany="0"></alias_list>
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<classes>
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<classesintro count="2">
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<txt>It has encodings from the following instruction sets:</txt>
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<txt> A32 (</txt>
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<a href="#iclass_a1">A1</a>
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<txt>)</txt>
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<txt> and </txt>
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<txt> T32 (</txt>
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<a href="#iclass_t1">T1</a>
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<txt>)</txt>
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<txt>.</txt>
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</classesintro>
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<iclass name="A1" oneof="2" id="iclass_a1" no_encodings="2" isa="A32">
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<docvars>
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<docvar key="armarmheading" value="A1" />
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<docvar key="instr-class" value="general" />
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<docvar key="isa" value="A32" />
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</docvars>
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<iclassintro count="2"></iclassintro>
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<regdiagram form="32" psname="aarch32/instrs/AND_i/A1_A.txt" tworows="1">
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<box hibit="31" width="4" name="cond" usename="1" settings="4" constraint="!= 1111">
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<c colspan="4">!= 1111</c>
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</box>
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<box hibit="27" width="4" settings="4">
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<c>0</c>
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<c>0</c>
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<c>1</c>
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<c>0</c>
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</box>
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<box hibit="23" width="3" name="opc" settings="3">
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<c>0</c>
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<c>0</c>
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<c>0</c>
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</box>
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<box hibit="20" name="S" usename="1">
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<c></c>
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</box>
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<box hibit="19" width="4" name="Rn" usename="1">
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<c colspan="4"></c>
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</box>
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<box hibit="15" width="4" name="Rd" usename="1">
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<c colspan="4"></c>
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</box>
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<box hibit="11" width="12" name="imm12" usename="1">
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<c colspan="12"></c>
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</box>
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</regdiagram>
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<encoding name="AND_i_A1" oneofinclass="2" oneof="4" label="AND" bitdiffs="S == 0">
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<docvars>
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<docvar key="armarmheading" value="A1" />
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<docvar key="instr-class" value="general" />
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<docvar key="isa" value="A32" />
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<docvar key="mnemonic" value="AND" />
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</docvars>
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<box hibit="20" width="1" name="S">
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<c>0</c>
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</box>
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<asmtemplate><text>AND</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}"><c></a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}"><q></a><text>}</text><text> </text><text>{</text><a link="sa_rd_1" hover="General-purpose destination register (field "Rd")"><Rd></a><text>,</text><text>}</text><text> </text><a link="sa_rn_1" hover="General-purpose source register (field "Rn")"><Rn></a><text>, #</text><a link="sa_const_1" hover="An immediate value"><const></a></asmtemplate>
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</encoding>
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<encoding name="ANDS_i_A1" oneofinclass="2" oneof="4" label="ANDS" bitdiffs="S == 1">
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<docvars>
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<docvar key="armarmheading" value="A1" />
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<docvar key="instr-class" value="general" />
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<docvar key="isa" value="A32" />
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<docvar key="mnemonic" value="ANDS" />
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</docvars>
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<box hibit="20" width="1" name="S">
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<c>1</c>
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</box>
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<asmtemplate><text>ANDS</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}"><c></a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}"><q></a><text>}</text><text> </text><text>{</text><a link="sa_rd_1" hover="General-purpose destination register (field "Rd")"><Rd></a><text>,</text><text>}</text><text> </text><a link="sa_rn_1" hover="General-purpose source register (field "Rn")"><Rn></a><text>, #</text><a link="sa_const_1" hover="An immediate value"><const></a></asmtemplate>
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</encoding>
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<ps_section howmany="1">
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<ps name="aarch32/instrs/AND_i/A1_A.txt" mylink="aarch32.instrs.AND_i.A1_A.txt" enclabels="" sections="1" secttype="noheading">
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<pstext mayhavelinks="1" section="Decode" rep_section="decode">d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rd); n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rn); setflags = (S == '1');
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(imm32, carry) = <a link="impl-aarch32.A32ExpandImm_C.2" file="shared_pseudocode.xml" hover="function: (bits(32), bit) A32ExpandImm_C(bits(12) imm12, bit carry_in)">A32ExpandImm_C</a>(imm12, PSTATE.C);</pstext>
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</ps>
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</ps_section>
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</iclass>
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<iclass name="T1" oneof="2" id="iclass_t1" no_encodings="2" isa="T32">
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<docvars>
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<docvar key="armarmheading" value="T1" />
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<docvar key="instr-class" value="general" />
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<docvar key="isa" value="T32" />
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</docvars>
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<iclassintro count="2"></iclassintro>
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<regdiagram form="16x2" psname="aarch32/instrs/AND_i/T1_A.txt">
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<box hibit="31" width="5" settings="5">
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<c>1</c>
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<c>1</c>
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<c>1</c>
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<c>1</c>
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<c>0</c>
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</box>
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<box hibit="26" name="i" usename="1">
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<c></c>
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</box>
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<box hibit="25" settings="1">
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<c>0</c>
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</box>
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<box hibit="24" width="4" name="op1" settings="4">
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<c>0</c>
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<c>0</c>
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<c>0</c>
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<c>0</c>
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</box>
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<box hibit="20" name="S" usename="1">
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<c></c>
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</box>
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<box hibit="19" width="4" name="Rn" usename="1">
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<c colspan="4"></c>
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</box>
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<box hibit="15" settings="1">
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<c>0</c>
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</box>
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<box hibit="14" width="3" name="imm3" usename="1">
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<c colspan="3"></c>
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</box>
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<box hibit="11" width="4" name="Rd" usename="1">
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<c colspan="4"></c>
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</box>
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<box hibit="7" width="8" name="imm8" usename="1">
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<c colspan="8"></c>
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</box>
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</regdiagram>
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<encoding name="AND_i_T1" oneofinclass="2" oneof="4" label="AND" bitdiffs="S == 0">
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<docvars>
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<docvar key="armarmheading" value="T1" />
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<docvar key="instr-class" value="general" />
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<docvar key="isa" value="T32" />
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<docvar key="mnemonic" value="AND" />
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</docvars>
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<box hibit="20" width="1" name="S">
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<c>0</c>
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</box>
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<asmtemplate><text>AND</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}"><c></a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}"><q></a><text>}</text><text> </text><text>{</text><a link="sa_rd" hover="General-purpose destination register (field "Rd")"><Rd></a><text>,</text><text>}</text><text> </text><a link="sa_rn" hover="General-purpose source register (field "Rn")"><Rn></a><text>, #</text><a link="sa_const" hover="An immediate value"><const></a></asmtemplate>
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</encoding>
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<encoding name="ANDS_i_T1" oneofinclass="2" oneof="4" label="ANDS" bitdiffs="S == 1 && Rd != 1111">
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<docvars>
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<docvar key="armarmheading" value="T1" />
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<docvar key="instr-class" value="general" />
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<docvar key="isa" value="T32" />
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<docvar key="mnemonic" value="ANDS" />
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</docvars>
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<box hibit="20" width="1" name="S">
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<c>1</c>
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</box>
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<box hibit="11" width="4" name="Rd">
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<c>N</c>
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<c>N</c>
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<c>N</c>
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<c>N</c>
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</box>
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<asmtemplate><text>ANDS</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}"><c></a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}"><q></a><text>}</text><text> </text><text>{</text><a link="sa_rd" hover="General-purpose destination register (field "Rd")"><Rd></a><text>,</text><text>}</text><text> </text><a link="sa_rn" hover="General-purpose source register (field "Rn")"><Rn></a><text>, #</text><a link="sa_const" hover="An immediate value"><const></a></asmtemplate>
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</encoding>
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<ps_section howmany="1">
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<ps name="aarch32/instrs/AND_i/T1_A.txt" mylink="aarch32.instrs.AND_i.T1_A.txt" enclabels="" sections="1" secttype="noheading">
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<pstext mayhavelinks="1" section="Decode" rep_section="decode">if Rd == '1111' && S == '1' then SEE "TST (immediate)";
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d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rd); n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rn); setflags = (S == '1');
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(imm32, carry) = <a link="impl-aarch32.T32ExpandImm_C.2" file="shared_pseudocode.xml" hover="function: (bits(32), bit) T32ExpandImm_C(bits(12) imm12, bit carry_in)">T32ExpandImm_C</a>(i:imm3:imm8, PSTATE.C);
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if (d == 15 && !setflags) || n == 15 then UNPREDICTABLE; // Armv8-A removes UNPREDICTABLE for R13</pstext>
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</ps>
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</ps_section>
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</iclass>
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</classes>
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<explanations scope="all">
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<explanation enclist="AND_i_A1, AND_i_T1" symboldefcount="1">
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<symbol link="sa_c"><c></symbol>
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<account encodedin="">
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<intro>
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<para>See <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
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</intro>
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</account>
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</explanation>
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<explanation enclist="AND_i_A1, AND_i_T1" symboldefcount="1">
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<symbol link="sa_q"><q></symbol>
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<account encodedin="">
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<intro>
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<para>See <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
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</intro>
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</account>
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</explanation>
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<explanation enclist="AND_i_A1" symboldefcount="1">
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<symbol link="sa_rd_1"><Rd></symbol>
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<account encodedin="Rd">
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<docvars>
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<docvar key="armarmheading" value="A1" />
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<docvar key="isa" value="A32" />
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</docvars>
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<intro>
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<para>For encoding A1: is the general-purpose destination register, encoded in the "Rd" field. If omitted, this register is the same as <syntax><Rn></syntax>. Arm deprecates using the PC as the destination register, but if the PC is used:</para>
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<list type="unordered">
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<listitem><content>For the AND variant, the instruction is a branch to the address calculated by the operation. This is an interworking branch, see <xref linkend="BEICJFEH">Pseudocode description of operations on the AArch32 general-purpose registers and the PC</xref>.</content></listitem>
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<listitem><content>For the ANDS variant, the instruction performs an exception return, that restores <xref linkend="BEIDIGBH">PSTATE</xref> from SPSR_<current_mode>.</content></listitem>
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</list>
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</intro>
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</account>
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</explanation>
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<explanation enclist="AND_i_T1" symboldefcount="2">
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<symbol link="sa_rd"><Rd></symbol>
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<account encodedin="Rd">
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<docvars>
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<docvar key="armarmheading" value="T1" />
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<docvar key="isa" value="T32" />
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</docvars>
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<intro>
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<para>For encoding T1: is the general-purpose destination register, encoded in the "Rd" field. If omitted, this register is the same as <syntax><Rn></syntax>.</para>
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</intro>
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</account>
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</explanation>
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<explanation enclist="AND_i_A1" symboldefcount="1">
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<symbol link="sa_rn_1"><Rn></symbol>
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<account encodedin="Rn">
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<docvars>
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<docvar key="armarmheading" value="A1" />
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<docvar key="isa" value="A32" />
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</docvars>
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<intro>
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<para>For encoding A1: is the general-purpose source register, encoded in the "Rn" field. The PC can be used, but this is deprecated.</para>
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</intro>
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</account>
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</explanation>
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<explanation enclist="AND_i_T1" symboldefcount="2">
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<symbol link="sa_rn"><Rn></symbol>
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<account encodedin="Rn">
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<docvars>
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<docvar key="armarmheading" value="T1" />
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<docvar key="isa" value="T32" />
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</docvars>
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<intro>
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<para>For encoding T1: is the general-purpose source register, encoded in the "Rn" field.</para>
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</intro>
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</account>
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</explanation>
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<explanation enclist="AND_i_A1" symboldefcount="1">
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<symbol link="sa_const_1"><const></symbol>
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<account encodedin="imm12">
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<docvars>
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<docvar key="armarmheading" value="A1" />
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<docvar key="isa" value="A32" />
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</docvars>
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<intro>
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<para>For encoding A1: an immediate value. See <xref linkend="BABHDAJF">Modified immediate constants in A32 instructions</xref> for the range of values.</para>
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</intro>
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</account>
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</explanation>
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<explanation enclist="AND_i_T1" symboldefcount="2">
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<symbol link="sa_const"><const></symbol>
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<account encodedin="i:imm3:imm8">
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<docvars>
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<docvar key="armarmheading" value="T1" />
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<docvar key="isa" value="T32" />
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</docvars>
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<intro>
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<para>For encoding T1: an immediate value. See <xref linkend="BABGHAGA">Modified immediate constants in T32 instructions</xref> for the range of values.</para>
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</intro>
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</account>
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</explanation>
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</explanations>
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<ps_section howmany="1">
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<ps name="aarch32/instrs/AND_i/Op_A.txt" mylink="execute" enclabels="" sections="1" secttype="Operation">
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<pstext mayhavelinks="1" section="Execute" rep_section="execute">if <a link="impl-aarch32.ConditionPassed.0" file="shared_pseudocode.xml" hover="function: boolean ConditionPassed()">ConditionPassed</a>() then
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EncodingSpecificOperations();
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result = <a link="impl-aarch32.R.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) R[integer n]">R</a>[n] AND imm32;
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if d == 15 then // Can only occur for A32 encoding
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if setflags then
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<a link="impl-aarch32.ALUExceptionReturn.1" file="shared_pseudocode.xml" hover="function: ALUExceptionReturn(bits(32) address)">ALUExceptionReturn</a>(result);
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else
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<a link="impl-aarch32.ALUWritePC.1" file="shared_pseudocode.xml" hover="function: ALUWritePC(bits(32) address)">ALUWritePC</a>(result);
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else
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<a link="impl-aarch32.R.write.1" file="shared_pseudocode.xml" hover="accessor: R[integer n] = bits(32) value">R</a>[d] = result;
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if setflags then
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PSTATE.N = result<31>;
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PSTATE.Z = <a link="impl-shared.IsZeroBit.1" file="shared_pseudocode.xml" hover="function: bit IsZeroBit(bits(N) x)">IsZeroBit</a>(result);
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PSTATE.C = carry;
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// PSTATE.V unchanged</pstext>
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</ps>
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</ps_section>
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</instructionsection>
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