301 lines
16 KiB
XML
301 lines
16 KiB
XML
<?xml version="1.0" encoding="utf-8"?>
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<?xml-stylesheet type="text/xsl" encoding="UTF-8" href="iform.xsl" version="1.0"?>
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<!DOCTYPE instructionsection PUBLIC "-//ARM//DTD instructionsection //EN" "iform-p.dtd">
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<!-- Copyright (c) 2010-2022 Arm Limited or its affiliates. All rights reserved. -->
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<!-- This document is Non-Confidential. This document may only be used and distributed in accordance with the terms of the agreement entered into by Arm and the party that Arm delivered this document to. -->
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<instructionsection id="ADD_ADR" title="ADD (immediate, to PC) -- AArch32" type="alias">
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<docvars>
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<docvar key="alias_mnemonic" value="ADD" />
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<docvar key="instr-class" value="general" />
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<docvar key="mnemonic" value="ADR" />
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</docvars>
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<heading>ADD (immediate, to PC)</heading>
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<desc>
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<brief>Add to PC</brief>
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<longer> adds an immediate value to the Align(PC, 4) value to form a PC-relative address, and writes the result to the destination register. Arm recommends that, where possible, software avoids using this alias</longer>
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</desc>
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<aliasto refiform="adr.xml" iformid="ADR">ADR</aliasto>
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<classes>
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<classesintro count="3">
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<txt>It has encodings from the following instruction sets:</txt>
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<txt> A32 (</txt>
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<a href="#iclass_a1">A1</a>
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<txt>)</txt>
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<txt> and </txt>
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<txt> T32 (</txt>
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<a href="#iclass_t1">T1</a>
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<txt> and </txt>
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<a href="#iclass_t3">T3</a>
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<txt>)</txt>
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<txt>.</txt>
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</classesintro>
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<iclass name="A1" oneof="3" id="iclass_a1" no_encodings="1" isa="A32">
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<docvars>
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<docvar key="armarmheading" value="A1" />
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<docvar key="instr-class" value="general" />
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<docvar key="isa" value="A32" />
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<docvar key="mnemonic" value="ADR" />
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</docvars>
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<iclassintro count="1"></iclassintro>
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<regdiagram form="32" psname="" tworows="1">
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<box hibit="31" width="4" name="cond" usename="1" settings="4" constraint="!= 1111">
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<c colspan="4">!= 1111</c>
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</box>
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<box hibit="27" width="4" settings="4">
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<c>0</c>
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<c>0</c>
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<c>1</c>
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<c>0</c>
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</box>
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<box hibit="23" width="3" name="opc" settings="3">
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<c>1</c>
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<c>0</c>
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<c>0</c>
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</box>
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<box hibit="20" name="S" settings="1">
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<c>0</c>
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</box>
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<box hibit="19" width="4" name="Rn" settings="4">
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<c>1</c>
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<c>1</c>
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<c>1</c>
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<c>1</c>
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</box>
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<box hibit="15" width="4" name="Rd" usename="1">
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<c colspan="4"></c>
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</box>
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<box hibit="11" width="12" name="imm12" usename="1">
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<c colspan="12"></c>
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</box>
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</regdiagram>
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<encoding name="ADD_ADR_A1" oneofinclass="1" oneof="3" label="A1">
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<docvars>
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<docvar key="alias_mnemonic" value="ADD" />
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<docvar key="armarmheading" value="A1" />
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<docvar key="instr-class" value="general" />
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<docvar key="isa" value="A32" />
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<docvar key="mnemonic" value="ADR" />
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</docvars>
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<asmtemplate><text>ADD</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}"><c></a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}"><q></a><text>}</text><text> </text><a link="sa_rd_1" hover="General-purpose destination register (field "Rd")"><Rd></a><text>, PC, #</text><a link="sa_const" hover="An immediate value"><const></a></asmtemplate>
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<equivalent_to>
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<asmtemplate><a href="adr.xml#ADR_A1">ADR</a><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}"><c></a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}"><q></a><text>}</text><text> </text><a link="sa_rd_1" hover="General-purpose destination register (field "Rd")"><Rd></a><text>, </text><a link="sa_label_2" hover="The label of an instruction or literal data item whose address is to be loaded into {syntax{<Rd>}}"><label></a></asmtemplate>
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<aliascond>Never</aliascond>
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</equivalent_to>
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</encoding>
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</iclass>
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<iclass name="T1" oneof="3" id="iclass_t1" no_encodings="1" isa="T32">
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<docvars>
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<docvar key="armarmheading" value="T1" />
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<docvar key="instr-class" value="general" />
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<docvar key="isa" value="T32" />
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<docvar key="mnemonic" value="ADR" />
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</docvars>
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<iclassintro count="1"></iclassintro>
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<regdiagram form="16" psname="">
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<box hibit="31" width="4" settings="4">
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<c>1</c>
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<c>0</c>
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<c>1</c>
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<c>0</c>
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</box>
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<box hibit="27" name="SP" settings="1">
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<c>0</c>
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</box>
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<box hibit="26" width="3" name="Rd" usename="1">
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<c colspan="3"></c>
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</box>
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<box hibit="23" width="8" name="imm8" usename="1">
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<c colspan="8"></c>
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</box>
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</regdiagram>
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<encoding name="ADD_ADR_T1" oneofinclass="1" oneof="3" label="T1">
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<docvars>
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<docvar key="alias_mnemonic" value="ADD" />
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<docvar key="armarmheading" value="T1" />
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<docvar key="instr-class" value="general" />
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<docvar key="isa" value="T32" />
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<docvar key="mnemonic" value="ADR" />
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</docvars>
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<asmtemplate><text>ADD</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}"><c></a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}"><q></a><text>}</text><text> </text><a link="sa_rd" hover="General-purpose destination register (field "Rd")"><Rd></a><text>, PC, #</text><a link="sa_imm8" hover="Unsigned immediate, multiple of 4 [0-1020] (field "imm8")"><imm8></a></asmtemplate>
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<equivalent_to>
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<asmtemplate><a href="adr.xml#ADR_T1">ADR</a><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}"><c></a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}"><q></a><text>}</text><text> </text><a link="sa_rd" hover="General-purpose destination register (field "Rd")"><Rd></a><text>, </text><a link="sa_label" hover="The label of an instruction or literal data item whose address is to be loaded into {syntax{<Rd>}}"><label></a></asmtemplate>
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<aliascond>Never</aliascond>
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</equivalent_to>
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</encoding>
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</iclass>
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<iclass name="T3" oneof="3" id="iclass_t3" no_encodings="1" isa="T32">
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<docvars>
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<docvar key="armarmheading" value="T3" />
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<docvar key="instr-class" value="general" />
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<docvar key="isa" value="T32" />
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<docvar key="mnemonic" value="ADR" />
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</docvars>
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<iclassintro count="1"></iclassintro>
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<regdiagram form="16x2" psname="">
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<box hibit="31" width="5" settings="5">
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<c>1</c>
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<c>1</c>
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<c>1</c>
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<c>1</c>
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<c>0</c>
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</box>
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<box hibit="26" name="i" usename="1">
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<c></c>
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</box>
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<box hibit="25" width="2" settings="2">
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<c>1</c>
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<c>0</c>
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</box>
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<box hibit="23" name="o1" settings="1">
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<c>0</c>
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</box>
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<box hibit="22" settings="1">
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<c>0</c>
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</box>
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<box hibit="21" name="o2" settings="1">
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<c>0</c>
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</box>
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<box hibit="20" settings="1">
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<c>0</c>
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</box>
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<box hibit="19" width="4" name="Rn" settings="4">
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<c>1</c>
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<c>1</c>
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<c>1</c>
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<c>1</c>
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</box>
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<box hibit="15" settings="1">
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<c>0</c>
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</box>
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<box hibit="14" width="3" name="imm3" usename="1">
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<c colspan="3"></c>
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</box>
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<box hibit="11" width="4" name="Rd" usename="1">
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<c colspan="4"></c>
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</box>
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<box hibit="7" width="8" name="imm8" usename="1">
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<c colspan="8"></c>
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</box>
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</regdiagram>
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<encoding name="ADD_ADR_T3" oneofinclass="1" oneof="3" label="T3">
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<docvars>
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<docvar key="alias_mnemonic" value="ADD" />
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<docvar key="armarmheading" value="T3" />
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<docvar key="instr-class" value="general" />
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<docvar key="isa" value="T32" />
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<docvar key="mnemonic" value="ADR" />
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</docvars>
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<asmtemplate comment="<Rd>, <imm12> can be represented in T1"><text>ADDW</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}"><c></a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}"><q></a><text>}</text><text> </text><a link="sa_rd" hover="General-purpose destination register (field "Rd")"><Rd></a><text>, PC, #</text><a link="sa_imm12" hover="12-bit unsigned immediate [0-4095] (field "i:imm3:imm8")"><imm12></a></asmtemplate>
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<asmtemplate><text>ADD</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}"><c></a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}"><q></a><text>}</text><text> </text><a link="sa_rd" hover="General-purpose destination register (field "Rd")"><Rd></a><text>, PC, #</text><a link="sa_imm12" hover="12-bit unsigned immediate [0-4095] (field "i:imm3:imm8")"><imm12></a></asmtemplate>
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<equivalent_to>
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<asmtemplate><a href="adr.xml#ADR_T3">ADR</a><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}"><c></a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}"><q></a><text>}</text><text> </text><a link="sa_rd" hover="General-purpose destination register (field "Rd")"><Rd></a><text>, </text><a link="sa_label_1" hover="The label of an instruction or literal data item whose address is to be loaded into {syntax{<Rd>}}"><label></a></asmtemplate>
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<aliascond>Never</aliascond>
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</equivalent_to>
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</encoding>
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</iclass>
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</classes>
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<explanations scope="all">
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<explanation enclist="ADD_ADR_A1, ADD_ADR_T1, ADD_ADR_T3" symboldefcount="1">
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<symbol link="sa_c"><c></symbol>
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<account encodedin="">
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<intro>
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<para>See <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
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</intro>
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</account>
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</explanation>
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<explanation enclist="ADD_ADR_A1, ADD_ADR_T1, ADD_ADR_T3" symboldefcount="1">
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<symbol link="sa_q"><q></symbol>
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<account encodedin="">
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<intro>
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<para>See <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
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</intro>
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</account>
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</explanation>
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<explanation enclist="ADD_ADR_A1" symboldefcount="1">
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<symbol link="sa_rd_1"><Rd></symbol>
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<account encodedin="Rd">
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<docvars>
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<docvar key="armarmheading" value="A1" />
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</docvars>
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<intro>
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<para>For encoding A1: is the general-purpose destination register, encoded in the "Rd" field. If the PC is used, the instruction is a branch to the address calculated by the operation. This is an interworking branch, see <xref linkend="BEICJFEH">Pseudocode description of operations on the AArch32 general-purpose registers and the PC</xref>.</para>
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</intro>
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</account>
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</explanation>
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<explanation enclist="ADD_ADR_T1, ADD_ADR_T3" symboldefcount="2">
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<symbol link="sa_rd"><Rd></symbol>
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<account encodedin="Rd">
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<intro>
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<para>For encoding T1 and T3: is the general-purpose destination register, encoded in the "Rd" field.</para>
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</intro>
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</account>
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</explanation>
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<explanation enclist="ADD_ADR_A1" symboldefcount="1">
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<symbol link="sa_label_2"><label></symbol>
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<account encodedin="imm12">
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<docvars>
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<docvar key="armarmheading" value="A1" />
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<docvar key="isa" value="A32" />
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</docvars>
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<intro>
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<para>For encoding A1: the label of an instruction or literal data item whose address is to be loaded into <syntax><Rd></syntax>. The assembler calculates the required value of the offset from the <function>Align(PC, 4)</function> value of the <instruction>ADR</instruction> instruction to this label.</para>
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<para>If the offset is zero or positive, encoding A1 is used, with <field>imm32</field> equal to the offset.</para>
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<para>If the offset is negative, encoding A2 is used, with <field>imm32</field> equal to the size of the offset. That is, the use of encoding A2 indicates that the required offset is minus the value of <field>imm32</field>.</para>
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<para>Permitted values of the size of the offset are any of the constants described in <xref linkend="BABHDAJF">Modified immediate constants in A32 instructions</xref>.</para>
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</intro>
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</account>
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</explanation>
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<explanation enclist="ADD_ADR_T1" symboldefcount="2">
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<symbol link="sa_label"><label></symbol>
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<account encodedin="imm8">
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<docvars>
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<docvar key="armarmheading" value="T1" />
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<docvar key="isa" value="T32" />
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</docvars>
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<intro>
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<para>For encoding T1: the label of an instruction or literal data item whose address is to be loaded into <syntax><Rd></syntax>. The assembler calculates the required value of the offset from the <function>Align(PC, 4)</function> value of the <instruction>ADR</instruction> instruction to this label. Permitted values of the size of the offset are multiples of 4 in the range 0 to 1020.</para>
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</intro>
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</account>
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</explanation>
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<explanation enclist="ADD_ADR_T3" symboldefcount="3">
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<symbol link="sa_label_1"><label></symbol>
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<account encodedin="i:imm3:imm8">
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<docvars>
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<docvar key="armarmheading" value="T3" />
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<docvar key="isa" value="T32" />
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</docvars>
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<intro>
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<para>For encoding T3: the label of an instruction or literal data item whose address is to be loaded into <syntax><Rd></syntax>. The assembler calculates the required value of the offset from the <function>Align(PC, 4)</function> value of the <instruction>ADR</instruction> instruction to this label.</para>
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<para>If the offset is zero or positive, encoding T3 is used, with <field>imm32</field> equal to the offset.</para>
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<para>If the offset is negative, encoding T2 is used, with <field>imm32</field> equal to the size of the offset. That is, the use of encoding T2 indicates that the required offset is minus the value of <field>imm32</field>.</para>
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<para>Permitted values of the size of the offset are 0-4095.</para>
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</intro>
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</account>
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</explanation>
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<explanation enclist="ADD_ADR_T1" symboldefcount="1">
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<symbol link="sa_imm8"><imm8></symbol>
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<account encodedin="imm8">
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<intro>
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<para>Is an unsigned immediate, a multiple of 4, in the range 0 to 1020, encoded in the "imm8" field as <imm8>/4.</para>
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</intro>
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</account>
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</explanation>
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<explanation enclist="ADD_ADR_T3" symboldefcount="1">
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<symbol link="sa_imm12"><imm12></symbol>
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<account encodedin="i:imm3:imm8">
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<intro>
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<para>Is a 12-bit unsigned immediate, in the range 0 to 4095, encoded in the "i:imm3:imm8" field.</para>
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</intro>
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</account>
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</explanation>
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<explanation enclist="ADD_ADR_A1" symboldefcount="1">
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<symbol link="sa_const"><const></symbol>
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<account encodedin="imm12">
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<intro>
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<para>An immediate value. See <xref linkend="BABHDAJF">Modified immediate constants in A32 instructions</xref> for the range of values.</para>
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</intro>
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</account>
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</explanation>
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</explanations>
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</instructionsection>
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