VSHRN (zero) Vector Shift Right Narrow takes each element in a vector, right shifts them by an immediate value, and places the truncated results in the destination vector VMOVN It has encodings from the following instruction sets: A32 ( A1 ) and T32 ( T1 ) . 1 1 1 1 0 0 1 1 1 1 1 1 0 0 0 1 0 0 0 0 VSHRN{<c>}{<q>}.<dt> <Dd>, <Qm>, #0 VMOVN{<c>}{<q>}.<dt> <Dd>, <Qm> Never 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 1 0 0 0 0 VSHRN{<c>}{<q>}.<dt> <Dd>, <Qm>, #0 VMOVN{<c>}{<q>}.<dt> <Dd>, <Qm> Never <c> For encoding A1: see Standard assembler syntax fields. This encoding must be unconditional. <c> For encoding T1: see Standard assembler syntax fields. <q> See Standard assembler syntax fields. <dt> Is the data type for the elements of the operand, size <dt> 00 I16 01 I32 10 I64 11 RESERVED <Dd> Is the 64-bit name of the SIMD&FP destination register, encoded in the "D:Vd" field. <Qm> Is the 128-bit name of the SIMD&FP source register, encoded in the "M:Vm" field as <Qm>*2.