VRINTZ (Advanced SIMD)
Vector round floating-point to integer towards Zero
Vector round floating-point to integer towards Zero rounds a vector of floating-point values to integral floating-point values of the same size, using the Round towards Zero rounding mode. A zero input gives a zero result with the same sign, an infinite input gives an infinite result with the same sign, and a NaN is propagated as for normal arithmetic.
For more information about the constrained unpredictable behavior of this instruction, see Architectural Constraints on UNPREDICTABLE behaviors.
It has encodings from the following instruction sets:
A32 (
A1
)
and
T32 (
T1
)
.
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VRINTZ{<q>}.<dt> <Dd>, <Dm>
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VRINTZ{<q>}.<dt> <Qd>, <Qm>
if Q == '1' && (Vd<0> == '1' || Vm<0> == '1') then UNDEFINED;
if (size == '01' && !HaveFP16Ext()) || size IN {'00', '11'} then UNDEFINED;
rounding = FPRounding_ZERO; exact = FALSE;
integer esize;
integer elements;
case size of
when '01' esize = 16; elements = 4;
when '10' esize = 32; elements = 2;
d = UInt(D:Vd); m = UInt(M:Vm); regs = if Q == '0' then 1 else 2;
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VRINTZ{<q>}.<dt> <Dd>, <Dm>
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VRINTZ{<q>}.<dt> <Qd>, <Qm>
if Q == '1' && (Vd<0> == '1' || Vm<0> == '1') then UNDEFINED;
if (size == '01' && !HaveFP16Ext()) || size IN {'00', '11'} then UNDEFINED;
rounding = FPRounding_ZERO; exact = FALSE;
integer esize;
integer elements;
case size of
when '01' esize = 16; elements = 4;
when '10' esize = 32; elements = 2;
d = UInt(D:Vd); m = UInt(M:Vm); regs = if Q == '0' then 1 else 2;
if InITBlock() then UNPREDICTABLE;
InITBlock()
The instruction executes as if it passes the Condition code check.
The instruction executes as NOP. This means it behaves as if it fails the Condition code check.
<q>
See Standard assembler syntax fields.
<dt>
Is the data type for the elements of the vectors,
<Qd>
Is the 128-bit name of the SIMD&FP destination register, encoded in the "D:Vd" field as <Qd>*2.
<Qm>
Is the 128-bit name of the SIMD&FP source register, encoded in the "M:Vm" field as <Qm>*2.
<Dd>
Is the 64-bit name of the SIMD&FP destination register, encoded in the "D:Vd" field.
<Dm>
Is the 64-bit name of the SIMD&FP source register, encoded in the "M:Vm" field.
EncodingSpecificOperations(); CheckAdvSIMDEnabled();
for r = 0 to regs-1
for e = 0 to elements-1
op1 = Elem[D[m+r],e,esize];
result = FPRoundInt(op1, StandardFPSCRValue(), rounding, exact);
Elem[D[d+r],e,esize] = result;