STLEXB Store-Release Exclusive Byte Store-Release Exclusive Byte stores a byte from a register to memory if the executing PE has exclusive access to the memory at that address, and returns a status value of 0 if the store was successful, or of 1 if no store was performed. The instruction also has memory ordering semantics as described in Load-Acquire, Store-Release. For more information about support for shared memory see Synchronization and semaphores. For information about memory accesses see Memory accesses. For more information about the constrained unpredictable behavior of this instruction, see Architectural Constraints on UNPREDICTABLE behaviors. Aborts If a synchronous Data Abort exception is generated by the execution of this instruction: Memory is not updated. <Rd> is not updated. If AArch32.ExclusiveMonitorsPass() returns FALSE and the memory address, if accessed, would generate a synchronous Data Abort exception, it is implementation defined whether the exception is generated. If CPSR.DIT is 1, the timing of this instruction is insensitive to the value of the data being loaded or stored. It has encodings from the following instruction sets: A32 ( A1 ) and T32 ( T1 ) . != 1111 0 0 0 1 1 1 0 0 (1) (1) 1 0 1 0 0 1 STLEXB{<c>}{<q>} <Rd>, <Rt>, [<Rn>] d = UInt(Rd); t = UInt(Rt); n = UInt(Rn); if d == 15 || t == 15 || n == 15 then UNPREDICTABLE; if d == n || d == t then UNPREDICTABLE; d == t d == n The instruction performs the store to an unknown address. 1 1 1 0 1 0 0 0 1 1 0 0 (1) (1) (1) (1) 1 1 0 0 STLEXB{<c>}{<q>} <Rd>, <Rt>, [<Rn>] d = UInt(Rd); t = UInt(Rt); n = UInt(Rn); if d == 15 || t == 15 || n == 15 then UNPREDICTABLE; if d == n || d == t then UNPREDICTABLE; d == t d == n The instruction performs the store to an unknown address. <c> See Standard assembler syntax fields. <q> See Standard assembler syntax fields. <Rd> Is the destination general-purpose register into which the status result of the store exclusive is written, encoded in the "Rd" field. The value returned is: 0If the operation updates memory. 1If the operation fails to update memory. <Rt> Is the general-purpose register to be transferred, encoded in the "Rt" field. <Rn> Is the general-purpose base register, encoded in the "Rn" field. if ConditionPassed() then EncodingSpecificOperations(); address = R[n]; if AArch32.ExclusiveMonitorsPass(address,1) then MemO[address, 1] = R[t]<7:0>; R[d] = ZeroExtend('0', 32); else R[d] = ZeroExtend('1', 32);