REV Byte-Reverse Word Byte-Reverse Word reverses the byte order in a 32-bit register. For more information about the constrained unpredictable behavior of this instruction, see Architectural Constraints on UNPREDICTABLE behaviors. If CPSR.DIT is 1, this instruction has passed its condition execution check, and does not use R15 as either its source or destination: The execution time of this instruction is independent of:The values of the data supplied in any of its registers.The values of the NZCV flags. The response of this instruction to asynchronous exceptions does not vary based on:The values of the data supplied in any of its registers.The values of the NZCV flags. It has encodings from the following instruction sets: A32 ( A1 ) and T32 ( T1 and T2 ) . != 1111 0 1 1 0 1 0 1 1 (1) (1) (1) (1) (1) (1) (1) (1) 0 0 1 1 REV{<c>}{<q>} <Rd>, <Rm> d = UInt(Rd); m = UInt(Rm); if d == 15 || m == 15 then UNPREDICTABLE; 1 0 1 1 1 0 1 0 0 0 REV{<c>}{<q>} <Rd>, <Rm> d = UInt(Rd); m = UInt(Rm); 1 1 1 1 1 0 1 0 1 0 0 1 1 1 1 1 1 0 0 0 REV{<c>}.W <Rd>, <Rm> REV{<c>}{<q>} <Rd>, <Rm> d = UInt(Rd); m = UInt(Rm); n = UInt(Rn); if m != n || d == 15 || m == 15 then UNPREDICTABLE; // Armv8-A removes UNPREDICTABLE for R13 m != n <c> See Standard assembler syntax fields. <q> See Standard assembler syntax fields. <Rd> Is the general-purpose destination register, encoded in the "Rd" field. <Rm> For encoding A1 and T1: is the general-purpose source register, encoded in the "Rm" field. <Rm> For encoding T2: is the general-purpose source register, encoded in the "Rm" field. It must be encoded with an identical value in the "Rn" field. if ConditionPassed() then EncodingSpecificOperations(); bits(32) result; result<31:24> = R[m]<7:0>; result<23:16> = R[m]<15:8>; result<15:8> = R[m]<23:16>; result<7:0> = R[m]<31:24>; R[d] = result;