EOR, EORS (register)
Bitwise Exclusive-OR (register)
Bitwise Exclusive-OR (register) performs a bitwise exclusive-OR of a register value and an optionally-shifted register value, and writes the result to the destination register.
If the destination register is not the PC, the EORS variant of the instruction updates the condition flags based on the result.
The field descriptions for <Rd> identify the encodings where the PC is permitted as the destination register. Arm deprecates any use of these encodings. However, when the destination register is the PC:
The EOR variant of the instruction is an interworking branch, see Pseudocode description of operations on the AArch32 general-purpose registers and the PC.
The EORS variant of the instruction performs an exception return without the use of the stack. In this case:The PE branches to the address written to the PC, and restores PSTATE from SPSR_<current_mode>.The PE checks SPSR_<current_mode> for an illegal return event. See Illegal return events from AArch32 state.The instruction is undefined in Hyp mode.The instruction is constrained unpredictable in User mode and System mode.
For more information about the constrained unpredictable behavior, see Architectural Constraints on UNPREDICTABLE behaviors.
In T32 assembly:
Outside an IT block, if EORS <Rd>, <Rn>, <Rd> has <Rd> and <Rn> both in the range R0-R7, it is assembled using encoding T1 as though EORS <Rd>, <Rn> had been written
Inside an IT block, if EOR<c> <Rd>, <Rn>, <Rd> has <Rd> and <Rn> both in the range R0-R7, it is assembled using encoding T1 as though EOR<c> <Rd>, <Rn> had been written.
To prevent either of these happening, use the .W qualifier.
If CPSR.DIT is 1 and this instruction does not use R15 as either its source or destination:
The execution time of this instruction is independent of:The values of the data supplied in any of its registers.The values of the NZCV flags.
The response of this instruction to asynchronous exceptions does not vary based on:The values of the data supplied in any of its registers.The values of the NZCV flags.
It has encodings from the following instruction sets:
A32 (
A1
)
and
T32 (
T1
and
T2
)
.
!= 1111
0
0
0
0
0
0
1
0
0
0
0
0
0
0
1
1
EOR{<c>}{<q>} {<Rd>,} <Rn>, <Rm>, RRX
0
Z
Z
Z
Z
Z
N
N
EOR{<c>}{<q>} {<Rd>,} <Rn>, <Rm> {, <shift> #<amount>}
1
0
0
0
0
0
1
1
EORS{<c>}{<q>} {<Rd>,} <Rn>, <Rm>, RRX
1
Z
Z
Z
Z
Z
N
N
EORS{<c>}{<q>} {<Rd>,} <Rn>, <Rm> {, <shift> #<amount>}
d = UInt(Rd); n = UInt(Rn); m = UInt(Rm); setflags = (S == '1');
(shift_t, shift_n) = DecodeImmShift(stype, imm5);
0
1
0
0
0
0
0
0
0
1
EOR<c>{<q>} {<Rdn>,} <Rdn>, <Rm>
EORS{<q>} {<Rdn>,} <Rdn>, <Rm>
d = UInt(Rdn); n = UInt(Rdn); m = UInt(Rm); setflags = !InITBlock();
(shift_t, shift_n) = (SRType_LSL, 0);
1
1
1
0
1
0
1
0
1
0
0
(0)
0
0
0
0
0
0
1
1
EOR{<c>}{<q>} {<Rd>,} <Rn>, <Rm>, RRX
0
Z
Z
Z
Z
Z
N
N
EOR<c>.W {<Rd>,} <Rn>, <Rm>
EOR{<c>}{<q>} {<Rd>,} <Rn>, <Rm> {, <shift> #<amount>}
1
0
0
0
N
N
N
N
0
0
1
1
EORS{<c>}{<q>} {<Rd>,} <Rn>, <Rm>, RRX
1
Z
Z
Z
Z
Z
N
N
N
N
N
N
EORS.W {<Rd>,} <Rn>, <Rm>
EORS{<c>}{<q>} {<Rd>,} <Rn>, <Rm> {, <shift> #<amount>}
if Rd == '1111' && S == '1' then SEE "TEQ (register)";
d = UInt(Rd); n = UInt(Rn); m = UInt(Rm); setflags = (S == '1');
(shift_t, shift_n) = DecodeImmShift(stype, imm3:imm2);
if (d == 15 && !setflags) || n == 15 || m == 15 then UNPREDICTABLE;
// Armv8-A removes UNPREDICTABLE for R13
<c>
See Standard assembler syntax fields.
<q>
See Standard assembler syntax fields.
<Rdn>
Is the first general-purpose source register and the destination register, encoded in the "Rdn" field.
<Rd>
For encoding A1: is the general-purpose destination register, encoded in the "Rd" field. If omitted, this register is the same as <Rn>. Arm deprecates using the PC as the destination register, but if the PC is used:
For the EOR variant, the instruction is a branch to the address calculated by the operation. This is an interworking branch, see Pseudocode description of operations on the AArch32 general-purpose registers and the PC.
For the EORS variant, the instruction performs an exception return, that restores PSTATE from SPSR_<current_mode>.
<Rd>
For encoding T2: is the general-purpose destination register, encoded in the "Rd" field. If omitted, this register is the same as <Rn>.
<Rn>
For encoding A1: is the first general-purpose source register, encoded in the "Rn" field. The PC can be used, but this is deprecated.
<Rn>
For encoding T2: is the first general-purpose source register, encoded in the "Rn" field.
<Rm>
For encoding A1: is the second general-purpose source register, encoded in the "Rm" field. The PC can be used, but this is deprecated.
<Rm>
For encoding T1 and T2: is the second general-purpose source register, encoded in the "Rm" field.
<shift>
Is the type of shift to be applied to the second source register,
stype
<shift>
00
LSL
01
LSR
10
ASR
11
ROR
<amount>
For encoding A1: is the shift amount, in the range 1 to 31 (when <shift> = LSL or ROR) or 1 to 32 (when <shift> = LSR or ASR) encoded in the "imm5" field as <amount> modulo 32.
<amount>
For encoding T2: is the shift amount, in the range 1 to 31 (when <shift> = LSL or ROR) or 1 to 32 (when <shift> = LSR or ASR), encoded in the "imm3:imm2" field as <amount> modulo 32.
if ConditionPassed() then
EncodingSpecificOperations();
(shifted, carry) = Shift_C(R[m], shift_t, shift_n, PSTATE.C);
result = R[n] EOR shifted;
if d == 15 then // Can only occur for A32 encoding
if setflags then
ALUExceptionReturn(result);
else
ALUWritePC(result);
else
R[d] = result;
if setflags then
PSTATE.N = result<31>;
PSTATE.Z = IsZeroBit(result);
PSTATE.C = carry;
// PSTATE.V unchanged