VPUSH Push SIMD&FP registers to stack Push SIMD&FP registers to stack stores multiple consecutive registers from the Advanced SIMD and floating-point register file to the stack. If CPSR.DIT is 1, the timing of this instruction is insensitive to the value of the data being loaded or stored. VSTM, VSTMDB, VSTMIA It has encodings from the following instruction sets: A32 ( A1 and A2 ) and T32 ( T1 and T2 ) . != 1111 1 1 0 1 0 1 0 1 1 0 1 1 0 1 1 0 VPUSH{<c>}{<q>}{.<size>} <dreglist> VSTMDB{<c>}{<q>}{.<size>} SP!, <dreglist> Unconditionally != 1111 1 1 0 1 0 1 0 1 1 0 1 1 0 1 0 VPUSH{<c>}{<q>}{.<size>} <sreglist> VSTMDB{<c>}{<q>}{.<size>} SP!, <sreglist> Unconditionally 1 1 1 0 1 1 0 1 0 1 0 1 1 0 1 1 0 1 1 0 VPUSH{<c>}{<q>}{.<size>} <dreglist> VSTMDB{<c>}{<q>}{.<size>} SP!, <dreglist> Unconditionally 1 1 1 0 1 1 0 1 0 1 0 1 1 0 1 1 0 1 0 VPUSH{<c>}{<q>}{.<size>} <sreglist> VSTMDB{<c>}{<q>}{.<size>} SP!, <sreglist> Unconditionally <c> See Standard assembler syntax fields. <q> See Standard assembler syntax fields. <size> An optional data size specifier. If present, it must be equal to the size in bits, 32 or 64, of the registers being transferred. <sreglist> Is the list of consecutively numbered 32-bit SIMD&FP registers to be transferred. The first register in the list is encoded in "Vd:D", and "imm8" is set to the number of registers in the list. The list must contain at least one register. <dreglist> Is the list of consecutively numbered 64-bit SIMD&FP registers to be transferred. The first register in the list is encoded in "D:Vd", and "imm8" is set to twice the number of registers in the list. The list must contain at least one register, and must not contain more than 16 registers.