STRB (register)
Store Register Byte (register)
Store Register Byte (register) calculates an address from a base register value and an offset register value, and stores a byte from a register to memory. The offset register value can optionally be shifted. For information about memory accesses see Memory accesses.
For more information about the constrained unpredictable behavior of this instruction, see Architectural Constraints on UNPREDICTABLE behaviors.
If CPSR.DIT is 1, the timing of this instruction is insensitive to the value of the data being loaded or stored.
It has encodings from the following instruction sets:
A32 (
A1
)
and
T32 (
T1
and
T2
)
.
!= 1111
0
1
1
1
0
0
1
0
STRB{<c>}{<q>} <Rt>, [<Rn>, {+/-}<Rm>{, <shift>}]
0
0
STRB{<c>}{<q>} <Rt>, [<Rn>], {+/-}<Rm>{, <shift>}
1
1
STRB{<c>}{<q>} <Rt>, [<Rn>, {+/-}<Rm>{, <shift>}]!
if P == '0' && W == '1' then SEE "STRBT";
t = UInt(Rt); n = UInt(Rn); m = UInt(Rm);
index = (P == '1'); add = (U == '1'); wback = (P == '0') || (W == '1');
(shift_t, shift_n) = DecodeImmShift(stype, imm5);
if t == 15 || m == 15 then UNPREDICTABLE;
if wback && (n == 15 || n == t) then UNPREDICTABLE;
t == 15
The store instruction performs the store using the specified addressing mode but the value corresponding to R15 is unknown.
wback && n == t
wback && n == 15
The instruction uses the addressing mode described in the equivalent immediate offset instruction.
0
1
0
1
0
1
0
STRB{<c>}{<q>} <Rt>, [<Rn>, {+}<Rm>]
t = UInt(Rt); n = UInt(Rn); m = UInt(Rm);
index = TRUE; add = TRUE; wback = FALSE;
(shift_t, shift_n) = (SRType_LSL, 0);
1
1
1
1
1
0
0
0
0
0
0
0
!= 1111
0
0
0
0
0
0
STRB{<c>}.W <Rt>, [<Rn>, {+}<Rm>]
STRB{<c>}{<q>} <Rt>, [<Rn>, {+}<Rm>{, LSL #<imm>}]
if Rn == '1111' then UNDEFINED;
t = UInt(Rt); n = UInt(Rn); m = UInt(Rm);
index = TRUE; add = TRUE; wback = FALSE;
(shift_t, shift_n) = (SRType_LSL, UInt(imm2));
if t == 15 || m == 15 then UNPREDICTABLE; // Armv8-A removes UNPREDICTABLE for R13
t == 15
The store instruction performs the store using the specified addressing mode but the value corresponding to R15 is unknown.
<c>
See Standard assembler syntax fields.
<q>
See Standard assembler syntax fields.
<Rt>
Is the general-purpose register to be transferred, encoded in the "Rt" field.
<Rn>
For encoding A1: is the general-purpose base register, encoded in the "Rn" field. The PC can be used in the offset variant, but this is deprecated.
<Rn>
For encoding T1 and T2: is the general-purpose base register, encoded in the "Rn" field.
+/-
Specifies the index register is added to or subtracted from the base register, defaulting to + if omitted and
+
Specifies the index register is added to the base register.
<Rm>
Is the general-purpose index register, encoded in the "Rm" field.
<shift>
The shift to apply to the value read from <Rm>. If absent, no shift is applied. Otherwise, see Shifts applied to a register.
<imm>
If present, the size of the left shift to apply to the value from <Rm>, in the range 1-3. <imm> is encoded in imm2. If absent, no shift is specified and imm2 is encoded as 0b00.
if ConditionPassed() then
EncodingSpecificOperations();
offset = Shift(R[m], shift_t, shift_n, PSTATE.C);
offset_addr = if add then (R[n] + offset) else (R[n] - offset);
address = if index then offset_addr else R[n];
MemU[address,1] = R[t]<7:0>;
if wback then R[n] = offset_addr;