STC
Store data to System register
Store data to System register calculates an address from a base register value and an immediate offset, and stores a word from the DBGDTRRXint System register to memory. It can use offset, post-indexed, pre-indexed, or unindexed addressing. For information about memory accesses, see Memory accesses.
In an implementation that includes EL2, the permitted STC access to DBGDTRRXint can be trapped to Hyp mode, meaning that an attempt to execute an STC instruction in a Non-secure mode other than Hyp mode, that would be permitted in the absence of the Hyp trap controls, generates a Hyp Trap exception. For more information, see Trapping general Non-secure System register accesses to debug registers.
For simplicity, the STC pseudocode does not show this possible trap to Hyp mode.
For more information about the constrained unpredictable behavior of this instruction, see Architectural Constraints on UNPREDICTABLE behaviors.
If CPSR.DIT is 1, the timing of this instruction is insensitive to the value of the data being loaded or stored.
It has encodings from the following instruction sets:
A32 (
A1
)
and
T32 (
T1
)
.
!= 1111
1
1
0
0
0
0
1
0
1
1
1
1
0
1
0
STC{<c>}{<q>} p14, c5, [<Rn>{, #{+/-}<imm>}]
0
1
STC{<c>}{<q>} p14, c5, [<Rn>], #{+/-}<imm>
1
1
STC{<c>}{<q>} p14, c5, [<Rn>, #{+/-}<imm>]!
0
1
0
STC{<c>}{<q>} p14, c5, [<Rn>], <option>
if P == '0' && U == '0' && W == '0' then UNDEFINED;
n = UInt(Rn); cp = 14;
imm32 = ZeroExtend(imm8:'00', 32); index = (P == '1'); add = (U == '1'); wback = (W == '1');
if n == 15 && (wback || CurrentInstrSet() != InstrSet_A32) then UNPREDICTABLE;
n == 15 && wback
The instruction executes with writeback to the PC. The instruction is handled as described in Using R15.
1
1
1
0
1
1
0
0
0
0
1
0
1
1
1
1
0
1
0
STC{<c>}{<q>} p14, c5, [<Rn>{, #{+/-}<imm>}]
0
1
STC{<c>}{<q>} p14, c5, [<Rn>], #{+/-}<imm>
1
1
STC{<c>}{<q>} p14, c5, [<Rn>, #{+/-}<imm>]!
0
1
0
STC{<c>}{<q>} p14, c5, [<Rn>], <option>
if P == '0' && U == '0' && W == '0' then UNDEFINED;
n = UInt(Rn); cp = 14;
imm32 = ZeroExtend(imm8:'00', 32); index = (P == '1'); add = (U == '1'); wback = (W == '1');
if n == 15 && (wback || CurrentInstrSet() != InstrSet_A32) then UNPREDICTABLE;
n == 15
The instruction executes with writeback to the PC. The instruction is handled as described in Using R15.
<c>
See Standard assembler syntax fields.
<q>
See Standard assembler syntax fields.
<Rn>
For the offset or unindexed variant: is the general-purpose base register, encoded in the "Rn" field. The PC can be used, but this is deprecated.
<Rn>
For the offset, post-indexed or pre-indexed variant: is the general-purpose base register, encoded in the "Rn" field.
<option>
Is an 8-bit immediate, in the range 0 to 255 enclosed in { }, encoded in the "imm8" field. The value of this field is ignored when executing this instruction.
+/-
Specifies the offset is added to or subtracted from the base register, defaulting to + if omitted and
<imm>
Is the immediate offset used for forming the address, a multiple of 4 in the range 0-1020, defaulting to 0 and encoded in the "imm8" field, as <imm>/4.
if ConditionPassed() then
EncodingSpecificOperations();
offset_addr = if add then (R[n] + imm32) else (R[n] - imm32);
address = if index then offset_addr else R[n];
// System register read from DBGDTRRXint.
AArch32.SysRegRead(cp, ThisInstr(), address<31:0>);
if wback then R[n] = offset_addr;