RORS (immediate) Rotate Right, setting flags (immediate) Rotate Right, setting flags (immediate) provides the value of the contents of a register rotated by a constant value. The bits that are rotated off the right end are inserted into the vacated bit positions on the left. If the destination register is not the PC, this instruction updates the condition flags based on the result. The field descriptions for <Rd> identify the encodings where the PC is permitted as the destination register. Arm deprecates any use of these encodings. However, when the destination register is the PC: The PE branches to the address written to the PC, and restores PSTATE from SPSR_<current_mode>. The PE checks SPSR_<current_mode> for an illegal return event. See Illegal return events from AArch32 state. The instruction is undefined in Hyp mode. The instruction is constrained unpredictable in User mode and System mode. MOV, MOVS (register) It has encodings from the following instruction sets: A32 ( A1 ) and T32 ( T3 ) . != 1111 0 0 0 1 1 0 1 1 (0) (0) (0) (0) != 00000 1 1 0 RORS{<c>}{<q>} {<Rd>,} <Rm>, #<imm> MOVS{<c>}{<q>} <Rd>, <Rm>, ROR #<imm> Unconditionally 1 1 1 0 1 0 1 0 0 1 0 1 1 1 1 1 (0) 1 1 Z Z Z Z Z RORS{<c>}{<q>} {<Rd>,} <Rm>, #<imm> MOVS{<c>}{<q>} <Rd>, <Rm>, ROR #<imm> Unconditionally <c> See Standard assembler syntax fields. <q> See Standard assembler syntax fields. <Rd> For encoding A1: is the general-purpose destination register, encoded in the "Rd" field. Arm deprecates using the PC as the destination register, but if the PC is used, the instruction performs an exception return, that restores PSTATE from SPSR_<current_mode>. <Rd> For encoding T3: is the general-purpose destination register, encoded in the "Rd" field. <Rm> For encoding A1: is the general-purpose source register, encoded in the "Rm" field. The PC can be used, but this is deprecated. <Rm> For encoding T3: is the general-purpose source register, encoded in the "Rm" field. <imm> For encoding A1: is the shift amount, in the range 1 to 31, encoded in the "imm5" field. <imm> For encoding T3: is the shift amount, in the range 1 to 31, encoded in the "imm3:imm2" field.