LDRSB (immediate)
Load Register Signed Byte (immediate)
Load Register Signed Byte (immediate) calculates an address from a base register value and an immediate offset, loads a byte from memory, sign-extends it to form a 32-bit word, and writes it to a register. It can use offset, post-indexed, or pre-indexed addressing. For information about memory accesses see Memory accesses.
For more information about the constrained unpredictable behavior of this instruction, see Architectural Constraints on UNPREDICTABLE behaviors.
If CPSR.DIT is 1, the timing of this instruction is insensitive to the value of the data being loaded or stored.
It has encodings from the following instruction sets:
A32 (
A1
)
and
T32 (
T1
and
T2
)
.
!= 1111
0
0
0
1
1
!= 1111
1
1
0
1
1
0
LDRSB{<c>}{<q>} <Rt>, [<Rn> {, #{+/-}<imm>}]
0
0
LDRSB{<c>}{<q>} <Rt>, [<Rn>], #{+/-}<imm>
1
1
LDRSB{<c>}{<q>} <Rt>, [<Rn>, #{+/-}<imm>]!
if Rn == '1111' then SEE "LDRSB (literal)";
if P == '0' && W == '1' then SEE "LDRSBT";
t = UInt(Rt); n = UInt(Rn); imm32 = ZeroExtend(imm4H:imm4L, 32);
index = (P == '1'); add = (U == '1'); wback = (P == '0') || (W == '1');
if t == 15 || (wback && n == t) then UNPREDICTABLE;
wback && n == t
The instruction performs all of the loads using the specified addressing mode and the content of the register that is written back is UNKNOWN. In addition, if an exception occurs during such an instruction, the base address might be corrupted so that the instruction cannot be repeated.
1
1
1
1
1
0
0
1
1
0
0
1
!= 1111
!= 1111
LDRSB{<c>}{<q>} <Rt>, [<Rn> {, #{+}<imm>}]
if Rt == '1111' then SEE "PLI";
if Rn == '1111' then SEE "LDRSB (literal)";
t = UInt(Rt); n = UInt(Rn); imm32 = ZeroExtend(imm12, 32);
index = TRUE; add = TRUE; wback = FALSE;
// Armv8-A removes UNPREDICTABLE for R13
1
1
1
1
1
0
0
1
0
0
0
1
!= 1111
1
N
N
N
N
1
0
0
LDRSB{<c>}{<q>} <Rt>, [<Rn> {, #-<imm>}]
0
1
LDRSB{<c>}{<q>} <Rt>, [<Rn>], #{+/-}<imm>
1
1
LDRSB{<c>}{<q>} <Rt>, [<Rn>, #{+/-}<imm>]!
if Rt == '1111' && P == '1' && U == '0' && W == '0' then SEE "PLI";
if Rn == '1111' then SEE "LDRSB (literal)";
if P == '1' && U == '1' && W == '0' then SEE "LDRSBT";
if P == '0' && W == '0' then UNDEFINED;
t = UInt(Rt); n = UInt(Rn); imm32 = ZeroExtend(imm8, 32);
index = (P == '1'); add = (U == '1'); wback = (W == '1');
if (t == 15 && W == '1') || (wback && n == t) then UNPREDICTABLE;
// Armv8-A removes UNPREDICTABLE for R13
wback && n == t
The instruction performs all of the loads using the specified addressing mode and the content of the register that is written back is UNKNOWN. In addition, if an exception occurs during such an instruction, the base address might be corrupted so that the instruction cannot be repeated.
<c>
See Standard assembler syntax fields.
<q>
See Standard assembler syntax fields.
<Rt>
Is the general-purpose register to be transferred, encoded in the "Rt" field.
<Rn>
Is the general-purpose base register, encoded in the "Rn" field. For PC use see LDRSB (literal).
+/-
Specifies the offset is added to or subtracted from the base register, defaulting to + if omitted and
+
Specifies the offset is added to the base register.
<imm>
For encoding A1: is the 8-bit unsigned immediate byte offset, in the range 0 to 255, defaulting to 0 if omitted, and encoded in the "imm4H:imm4L" field.
<imm>
For encoding T1: is an optional 12-bit unsigned immediate byte offset, in the range 0 to 4095, defaulting to 0 and encoded in the "imm12" field.
<imm>
For encoding T2: is an 8-bit unsigned immediate byte offset, in the range 0 to 255, defaulting to 0 if omitted, and encoded in the "imm8" field.
if ConditionPassed() then
EncodingSpecificOperations();
offset_addr = if add then (R[n] + imm32) else (R[n] - imm32);
address = if index then offset_addr else R[n];
R[t] = SignExtend(MemU[address,1], 32);
if wback then R[n] = offset_addr;