AESMC AES mix columns AES mix columns. For more information about the constrained unpredictable behavior of this instruction, see Architectural Constraints on UNPREDICTABLE behaviors. If CPSR.DIT is 1: The execution time of this instruction is independent of:The values of the data supplied in any of its registers.The values of the NZCV flags. The response of this instruction to asynchronous exceptions does not vary based on:The values of the data supplied in any of its registers.The values of the NZCV flags. It has encodings from the following instruction sets: A32 ( A1 ) and T32 ( T1 ) . 1 1 1 1 0 0 1 1 1 1 1 0 0 0 0 1 1 1 0 0 AESMC.<dt> <Qd>, <Qm> if !HaveAESExt() then UNDEFINED; if size != '00' then UNDEFINED; if Vd<0> == '1' || Vm<0> == '1' then UNDEFINED; d = UInt(D:Vd); m = UInt(M:Vm); 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 0 0 AESMC.<dt> <Qd>, <Qm> if InITBlock() then UNPREDICTABLE; if !HaveAESExt() then UNDEFINED; if size != '00' then UNDEFINED; if Vd<0> == '1' || Vm<0> == '1' then UNDEFINED; d = UInt(D:Vd); m = UInt(M:Vm); <dt> Is the data type, size <dt> 00 8 01 RESERVED 1x RESERVED <Qd> Is the 128-bit name of the SIMD&FP destination register, encoded in the "D:Vd" field as <Qd>*2. <Qm> Is the 128-bit name of the SIMD&FP source register, encoded in the "M:Vm" field as <Qm>*2. if ConditionPassed() then EncodingSpecificOperations(); CheckCryptoEnabled32(); Q[d>>1] = AESMixColumns(Q[m>>1]);