VRINTR
Round floating-point to integer
Round floating-point to integer rounds a floating-point value to an integral floating-point value of the same size using the rounding mode specified in the FPSCR. A zero input gives a zero result with the same sign, an infinite input gives an infinite result with the same sign, and a NaN is propagated as for normal arithmetic.
It has encodings from the following instruction sets:
A32 (
A1
)
and
T32 (
T1
)
.
!= 1111
1
1
1
0
1
1
1
0
1
1
0
1
0
0
1
0
0
1
VRINTR{<c>}{<q>}.F16 <Sd>, <Sm>
1
0
VRINTR{<c>}{<q>}.F32 <Sd>, <Sm>
1
1
VRINTR{<c>}{<q>}.F64 <Dd>, <Dm>
if size == '00' || (size == '01' && !HaveFP16Ext()) then UNDEFINED;
if size == '01' && cond != '1110' then UNPREDICTABLE;
rounding = if op == '1' then FPRounding_ZERO else FPRoundingMode(FPSCR[]);
exact = FALSE;
integer esize;
integer d;
integer m;
case size of
when '01' esize = 16; d = UInt(Vd:D); m = UInt(Vm:M);
when '10' esize = 32; d = UInt(Vd:D); m = UInt(Vm:M);
when '11' esize = 64; d = UInt(D:Vd); m = UInt(M:Vm);
1
1
1
0
1
1
1
0
1
1
1
0
1
1
0
1
0
0
1
0
0
1
VRINTR{<c>}{<q>}.F16 <Sd>, <Sm>
1
0
VRINTR{<c>}{<q>}.F32 <Sd>, <Sm>
1
1
VRINTR{<c>}{<q>}.F64 <Dd>, <Dm>
if size == '00' || (size == '01' && !HaveFP16Ext()) then UNDEFINED;
if size == '01' && InITBlock() then UNPREDICTABLE;
rounding = if op == '1' then FPRounding_ZERO else FPRoundingMode(FPSCR[]);
exact = FALSE;
integer esize;
integer d;
integer m;
case size of
when '01' esize = 16; d = UInt(Vd:D); m = UInt(Vm:M);
when '10' esize = 32; d = UInt(Vd:D); m = UInt(Vm:M);
when '11' esize = 64; d = UInt(D:Vd); m = UInt(M:Vm);
InITBlock()
The instruction executes as if it passes the Condition code check.
The instruction executes as NOP. This means it behaves as if it fails the Condition code check.
<c>
See Standard assembler syntax fields.
<q>
See Standard assembler syntax fields.
<Sd>
Is the 32-bit name of the SIMD&FP destination register, encoded in the "Vd:D" field.
<Sm>
Is the 32-bit name of the SIMD&FP source register, encoded in the "Vm:M" field.
<Dd>
Is the 64-bit name of the SIMD&FP destination register, encoded in the "D:Vd" field.
<Dm>
Is the 64-bit name of the SIMD&FP source register, encoded in the "M:Vm" field.
if ConditionPassed() then
EncodingSpecificOperations(); CheckVFPEnabled(TRUE);
case esize of
when 16
S[d] = Zeros(16) : FPRoundInt(S[m]<15:0>, FPSCR[], rounding, exact);
when 32
S[d] = FPRoundInt(S[m], FPSCR[], rounding, exact);
when 64
D[d] = FPRoundInt(D[m], FPSCR[], rounding, exact);