VACGE
Vector Absolute Compare Greater Than or Equal
Vector Absolute Compare Greater Than or Equal takes the absolute value of each element in a vector, and compares it with the absolute value of the corresponding element of a second vector. If the first is greater than or equal to the second, the corresponding element in the destination vector is set to all ones. Otherwise, it is set to all zeros.
The operands and result can be quadword or doubleword vectors. They must all be the same size.
The operand vector elements are floating-point numbers. The result vector elements are the same size as the operand vector elements.
Depending on settings in the CPACR, NSACR, and HCPTR registers, and the Security state and PE mode in which the instruction is executed, an attempt to execute the instruction might be undefined, or trapped to Hyp mode. For more information see Enabling Advanced SIMD and floating-point support.
This instruction is used by the alias
VACLE
Never
See
below for details of when the alias is preferred.
It has encodings from the following instruction sets:
A32 (
A1
)
and
T32 (
T1
)
.
1
1
1
1
0
0
1
1
0
0
1
1
1
0
1
0
VACGE{<c>}{<q>}.<dt> {<Dd>, }<Dn>, <Dm>
1
VACGE{<c>}{<q>}.<dt> {<Qd>, }<Qn>, <Qm>
if Q == '1' && (Vd<0> == '1' || Vn<0> == '1' || Vm<0> == '1') then UNDEFINED;
if sz == '1' && !HaveFP16Ext() then UNDEFINED;
or_equal = (op == '0');
integer esize;
integer elements;
case sz of
when '0' esize = 32; elements = 2;
when '1' esize = 16; elements = 4;
d = UInt(D:Vd); n = UInt(N:Vn); m = UInt(M:Vm); regs = if Q == '0' then 1 else 2;
1
1
1
1
1
1
1
1
0
0
1
1
1
0
1
0
VACGE{<c>}{<q>}.<dt> {<Dd>, }<Dn>, <Dm>
1
VACGE{<c>}{<q>}.<dt> {<Qd>, }<Qn>, <Qm>
if Q == '1' && (Vd<0> == '1' || Vn<0> == '1' || Vm<0> == '1') then UNDEFINED;
if sz == '1' && !HaveFP16Ext() then UNDEFINED;
if sz == '1' && InITBlock() then UNPREDICTABLE;
or_equal = (op == '0');
integer esize;
integer elements;
case sz of
when '0' esize = 32; elements = 2;
when '1' esize = 16; elements = 4;
d = UInt(D:Vd); n = UInt(N:Vn); m = UInt(M:Vm); regs = if Q == '0' then 1 else 2;
sz == '1' && InITBlock()
The instruction executes as if it passes the Condition code check.
The instruction executes as NOP. This means it behaves as if it fails the Condition code check.
<c>
For encoding A1: see Standard assembler syntax fields. This encoding must be unconditional.
<c>
For encoding T1: see Standard assembler syntax fields.
<q>
See Standard assembler syntax fields.
<dt>
Is the data type for the elements of the vectors,
<Qd>
Is the 128-bit name of the SIMD&FP destination register, encoded in the "D:Vd" field as <Qd>*2.
<Qn>
Is the 128-bit name of the first SIMD&FP source register, encoded in the "N:Vn" field as <Qn>*2.
<Qm>
Is the 128-bit name of the second SIMD&FP source register, encoded in the "M:Vm" field as <Qm>*2.
<Dd>
Is the 64-bit name of the SIMD&FP destination register, encoded in the "D:Vd" field.
<Dn>
Is the 64-bit name of the first SIMD&FP source register, encoded in the "N:Vn" field.
<Dm>
Is the 64-bit name of the second SIMD&FP source register, encoded in the "M:Vm" field.
Alias Conditions
if ConditionPassed() then
EncodingSpecificOperations(); CheckAdvSIMDEnabled();
for r = 0 to regs-1
for e = 0 to elements-1
op1 = FPAbs(Elem[D[n+r],e,esize]); op2 = FPAbs(Elem[D[m+r],e,esize]);
boolean test_passed;
if or_equal then
test_passed = FPCompareGE(op1, op2, StandardFPSCRValue());
else
test_passed = FPCompareGT(op1, op2, StandardFPSCRValue());
Elem[D[d+r],e,esize] = if test_passed then Ones(esize) else Zeros(esize);