UXTB Unsigned Extend Byte Unsigned Extend Byte extracts an 8-bit value from a register, zero-extends it to 32 bits, and writes the result to the destination register. The instruction can specify a rotation by 0, 8, 16, or 24 bits before extracting the 8-bit value. For more information about the constrained unpredictable behavior of this instruction, see Architectural Constraints on UNPREDICTABLE behaviors. If CPSR.DIT is 1, this instruction has passed its condition execution check, and does not use R15 as either its source or destination: The execution time of this instruction is independent of:The values of the data supplied in any of its registers.The values of the NZCV flags. The response of this instruction to asynchronous exceptions does not vary based on:The values of the data supplied in any of its registers.The values of the NZCV flags. It has encodings from the following instruction sets: A32 ( A1 ) and T32 ( T1 and T2 ) . != 1111 0 1 1 0 1 1 1 0 1 1 1 1 (0) (0) 0 1 1 1 UXTB{<c>}{<q>} {<Rd>,} <Rm> {, ROR #<amount>} d = UInt(Rd); m = UInt(Rm); rotation = UInt(rotate:'000'); if d == 15 || m == 15 then UNPREDICTABLE; 1 0 1 1 0 0 1 0 1 1 UXTB{<c>}{<q>} {<Rd>,} <Rm> d = UInt(Rd); m = UInt(Rm); rotation = 0; 1 1 1 1 1 0 1 0 0 1 0 1 1 1 1 1 1 1 1 1 1 (0) UXTB{<c>}.W {<Rd>,} <Rm> UXTB{<c>}{<q>} {<Rd>,} <Rm> {, ROR #<amount>} d = UInt(Rd); m = UInt(Rm); rotation = UInt(rotate:'000'); if d == 15 || m == 15 then UNPREDICTABLE; // Armv8-A removes UNPREDICTABLE for R13 <c> See Standard assembler syntax fields. <q> See Standard assembler syntax fields. <Rd> Is the general-purpose destination register, encoded in the "Rd" field. <Rm> Is the general-purpose source register, encoded in the "Rm" field. <amount> Is the rotate amount, rotate <amount> 00 (omitted) 01 8 10 16 11 24 if ConditionPassed() then EncodingSpecificOperations(); rotated = ROR(R[m], rotation); R[d] = ZeroExtend(rotated<7:0>, 32);