16-bit

!= 111

Shift (immediate), add, subtract, move, and compare

00xxxx 00

Add, subtract (three low registers)

0 11 0

Add, subtract (two low registers and immediate)

0 11 1

Shift (immediate)

0 != 11

Add, subtract, compare, move (one low register and immediate)

1

Data-processing (two low registers)

010000

Special data instructions and branch and exchange

010001 010001

Branch and exchange

11

Add, subtract, compare, move (two high registers)

!= 11

Load literal

01001x

Load/store (register offset)

0101xx

Load/store word/byte (immediate offset)

011xxx

Load/store halfword (immediate offset)

1000xx

Load/store (SP-relative)

1001xx

Add PC/SP (immediate)

1010xx

Miscellaneous 16-bit instructions

1011xx 1011

Adjust SP (immediate)

0000

Extend

0010

SETPAN

0110 00 0

UNALLOCATED

0110 00 1

Change Processor State

0110 01

UNALLOCATED

0110 1x

UNALLOCATED

0111

UNALLOCATED

1000

Halting breakpoint

1010 10

Reverse bytes

1010 != 10

Software breakpoint

1110

Hints

1111 0000

If-Then

1111 != 0000

Compare and branch zero/non-zero

x0x1

Push and Pop

x10x

Load/store multiple

1100xx

Conditional branch, and Supervisor Call

1101xx 1101

Exception generation

111x

Conditional branch

!= 111x

Unconditional branch

111 00

32-bit

111 != 00 111

System register access, Advanced SIMD, and floating-point

x11x 111 11

UNALLOCATED

0x 0x

UNALLOCATED

10 0x

Advanced SIMD data-processing

11 111 1111

Advanced SIMD three registers of the same length

0

Advanced SIMD two registers, or three registers of different lengths

1 0 111 11111 0

Advanced SIMD vector extract

0 11

Advanced SIMD two registers misc

1 11 0x

Advanced SIMD table permute

1 11 10

Advanced SIMD duplicate (scalar)

1 11 11

Advanced SIMD three registers of different lengths

!= 11 0

Advanced SIMD two registers and a scalar

!= 11 1

Advanced SIMD shifts and immediate generation

1 1 111 11111 1

Advanced SIMD one register and modified immediate

000xxxxxxxxxxx0

Advanced SIMD two registers and shift amount

!= 000xxxxxxxxxxx0

Advanced SIMD and System register load/store and 64-bit move

0 0x 1x 1110110 1

Advanced SIMD and floating-point 64-bit move

00x0 0x

System register 64-bit move

00x0 11

Advanced SIMD and floating-point load/store

!= 00x0 0x

System register Load/Store

!= 00x0 11

UNALLOCATED

10

Advanced SIMD and System register 32-bit move

0 10 1x 1 11101110 1 1

UNALLOCATED

000 000

Floating-point 16-bit move

000 001

Floating-point 32-bit move

000 010

UNALLOCATED

001 010

UNALLOCATED

01x 010

UNALLOCATED

10x 010

UNALLOCATED

110 010

Floating-point move special register

111 010

Advanced SIMD 8/16/32-bit element move/duplicate

011

UNALLOCATED

10x

System register 32-bit move

11x

Floating-point data-processing

0 10 10 0 11101110 10 0

Floating-point data-processing (two registers)

1x11 1

Floating-point move immediate

1x11 0

Floating-point data-processing (three registers)

!= 1x11

UNALLOCATED

0 10 11 0

Additional Advanced SIMD and floating-point instructions

1 != 11 1x 111111 1

Advanced SIMD three registers of the same length extension

0xx 0x

Floating-point conditional select

100 0 != 00 0 0

Floating-point minNum/maxNum

101 00xxxx 0 != 00 0

Floating-point extraction and insertion

101 110000 0 != 00 1 0

Floating-point directed convert to integer

101 111xxx 0 != 00 1 0

Advanced SIMD and floating-point multiply with accumulate

10x 0 00

Advanced SIMD and floating-point dot product

10x 1 0x

Load/store multiple

0100 xx0xx

Load/store dual, load/store exclusive, load-acquire/store-release, and table branch

0100 xx1xx 1110100

Load/store exclusive

0010

UNALLOCATED

0110 0 000

Table branch

0110 1 000

Load/store exclusive byte/half/dual

0110 01x

Load-acquire / Store-release

0110 1xx

Load/store dual (immediate, post-indexed)

0x11 != 1111

Load/store dual (immediate)

1x10 != 1111

Load/store dual (immediate, pre-indexed)

1x11 != 1111

Load dual (literal)

!= 0xx0 1111

Data-processing (shifted register)

0101

Branches and miscellaneous control

10xx 1 11110 1

MSR (special)

0 1110 0x 0x0 0

MSR (banked)

0 1110 0x 0x0 1

Hints

0 1110 10 0x0 000

Change processor state

0 1110 10 0x0 != 000

Miscellaneous system

0 1110 11 0x0

Branch and Exchange Jazelle

0 1111 00 0x0

Exception return

0 1111 01 0x0

MRS (special)

0 1111 1x 0x0 0

MRS (banked)

0 1111 1x 0x0 1

DCPS

1 1110 00 000

UNALLOCATED

1 1110 00 010

UNALLOCATED

1 1110 01 0x0

UNALLOCATED

1 1110 1x 0x0

UNALLOCATED

1 1111 0x 0x0

Exception generation

1 1111 1x 0x0

Conditional branch

!= 111x 0x0

Unconditional branch

0x1

Unconditional branch and link exchange

1x0

Unconditional branch and link

1x1

Data-processing (modified immediate)

10x0 0

Data-processing (plain binary immediate)

10x1 xxxx0 0 11110 1 0 0

Data-processing (simple immediate)

0 0x

Move Wide (16-bit immediate)

0 10

UNALLOCATED

0 11

Saturate, Bitfield

1

UNALLOCATED

10x1 xxxx1 0

Advanced SIMD element or structure load/store

1100 1xxx0 11111001 0

Advanced SIMD load/store multiple structures

0

Advanced SIMD load single structure to all lanes

1 11

Advanced SIMD load/store single structure to one lane

1 != 11

Load/store single

1100 != 1xxx0 1111100

Load/store, unsigned (register offset)

00 != 1111 000000

UNALLOCATED

00 != 1111 000001

UNALLOCATED

00 != 1111 00001x

UNALLOCATED

00 != 1111 0001xx

UNALLOCATED

00 != 1111 001xxx

UNALLOCATED

00 != 1111 01xxxx

UNALLOCATED

00 != 1111 10x0xx

Load/store, unsigned (immediate, post-indexed)

00 != 1111 10x1xx

Load/store, unsigned (negative immediate)

00 != 1111 1100xx

Load/store, unsigned (unprivileged)

00 != 1111 1110xx

Load/store, unsigned (immediate, pre-indexed)

00 != 1111 11x1xx

Load/store, unsigned (positive immediate)

01 != 1111

Load, unsigned (literal)

0x 1111

Load/store, signed (register offset)

10 1 != 1111 000000

UNALLOCATED

10 1 != 1111 000001

UNALLOCATED

10 1 != 1111 00001x

UNALLOCATED

10 1 != 1111 0001xx

UNALLOCATED

10 1 != 1111 001xxx

UNALLOCATED

10 1 != 1111 01xxxx

UNALLOCATED

10 1 != 1111 10x0xx

Load/store, signed (immediate, post-indexed)

10 1 != 1111 10x1xx

Load/store, signed (negative immediate)

10 1 != 1111 1100xx

Load/store, signed (unprivileged)

10 1 != 1111 1110xx

Load/store, signed (immediate, pre-indexed)

10 1 != 1111 11x1xx

Load/store, signed (positive immediate)

11 1 != 1111

Load, signed (literal)

1x 1 1111

Data-processing (register)

1101 0xxxx 11111010

Register shifts

0 1111 0000

UNALLOCATED

0 1111 0001

UNALLOCATED

0 1111 001x

UNALLOCATED

0 1111 01xx

Register extends

0 1111 1xxx

Parallel add-subtract

1 1111 0xxx

Data-processing (two source registers)

1 1111 10xx

UNALLOCATED

1 1111 11xx

UNALLOCATED

!= 1111

Multiply, multiply accumulate, and absolute difference

1101 10xxx 111110110

Multiply and absolute difference

00

UNALLOCATED

01

UNALLOCATED

1x

Long multiply and divide

1101 11xxx Instruction bits Encoding Group 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 != 111 16-bit 1 1 1 0 0 16-bit Unconditional Branch 1 1 1 != 00 32-bit 0 0 16-bit / Shift (immediate), add, subtract, move, and compare 0 1 0 0 0 0 16-bit / Data-processing 0 1 0 0 0 1 16-bit / Special data instructions and branch and exchange 0 1 0 0 1 16-bit / Load from Literal Pool 0 1 0 1 16-bit / Load/store single (register) 0 1 1 16-bit / Load/store single word and unsigned byte (immediate) 1 0 0 0 16-bit / Load/store single halfword (immediate) 1 0 0 1 16-bit / Load/store single (SP-relative) 1 0 1 0 16-bit / ADR and ADD (SP plus register) 1 0 1 1 16-bit / Miscellaneous 16-bit instructions 1 1 0 0 16-bit / Load/Store multiple registers 1 1 0 1 16-bit / Conditional branch, and Supervisor Call 1 1 1 0 1 0 0 0 32-bit / Load/store multiple 1 1 1 0 1 0 0 1 32-bit / Load/store dual, load/store exclusive, load-acquire/store-release, and table branch 1 1 1 0 1 0 1 32-bit / Data-processing (shifted register) 1 1 1 1 0 0 0 32-bit / Data-processing (modified immediate) 1 1 1 1 0 1 0 0 32-bit / Data-processing (plain binary immediate) 1 1 1 1 0 1 1 0 32-bit / UNALLOCATED 1 1 1 1 0 1 32-bit / Branches and miscellaneous control 1 1 1 1 1 0 0 != 1xxx0 32-bit / Load/store single 1 1 1 1 1 0 0 1 0 32-bit / Advanced SIMD element or structure load/store 1 1 1 1 1 0 1 0 32-bit / Data-processing (register) 1 1 1 1 1 0 1 1 0 32-bit / Multiply, multiply accumulate, and absolute difference 1 1 1 1 1 0 1 1 1 32-bit / Long multiply, long multiply accumulate, and divide 1 1 1 1 1 32-bit / System register access, Advanced SIMD, and floating-point 1 1 1 1 1 0 0 32-bit / System register access, Advanced SIMD, and floating-point / UNALLOCATED 1 1 1 1 1 1 0 0 32-bit / System register access, Advanced SIMD, and floating-point / UNALLOCATED 1 1 1 0 1 1 0 1 32-bit / System register access, Advanced SIMD, and floating-point / Advanced SIMD and System register load/store and 64-bit move 1 1 1 0 1 1 1 0 1 0 0 32-bit / System register access, Advanced SIMD, and floating-point / Floating-point data-processing 1 1 1 0 1 1 1 0 1 1 0 32-bit / System register access, Advanced SIMD, and floating-point / UNALLOCATED 1 1 1 0 1 1 1 0 1 1 32-bit / System register access, Advanced SIMD, and floating-point / Advanced SIMD and System register 32-bit move 1 1 1 1 1 1 != 11 1 32-bit / System register access, Advanced SIMD, and floating-point / Additional Advanced SIMD and floating-point instructions 1 1 1 1 1 1 1 32-bit / System register access, Advanced SIMD, and floating-point / Advanced SIMD data-processing 1 1 1 1 1 1 1 0 32-bit / System register access, Advanced SIMD, and floating-point / Advanced SIMD data-processing / Advanced SIMD three registers of the same length 1 1 1 1 1 1 1 1 0 32-bit / System register access, Advanced SIMD, and floating-point / Advanced SIMD data-processing / Advanced SIMD two registers, or three registers of different lengths 1 1 1 1 1 1 1 1 1 32-bit / System register access, Advanced SIMD, and floating-point / Advanced SIMD data-processing / Advanced SIMD shifts and immediate generation Instruction bits Instruction class 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 1 1 1 1 1 1 1 0 1 1 0 Advanced SIMD and floating-point dot product 1 1 1 1 0 1 1 1 1 0 0 0 1 0 0 0 DCPS 1 1 1 1 1 0 1 0 0 1 1 1 1 0 0 0 0 Register shifts 1 1 1 1 1 0 0 0 0 != 1111 1 1 1 0 Load/store, unsigned (unprivileged) 0 1 1 Load/store word/byte (immediate offset) 1 1 1 0 1 1 1 0 1 1 1 1 0 1 0 Floating-point data-processing (two registers) 1 1 1 1 1 0 1 1 1 Long multiply and divide 1 1 0 1 != 111x Conditional branch 1 1 1 0 1 1 1 1 1 1 1 0 Advanced SIMD vector extract 1 1 1 1 1 0 0 1 0 1 != 1111 0 0 0 1 UNALLOCATED 1 1 1 1 1 0 0 0 0 != 1111 1 1 0 0 Load/store, unsigned (negative immediate) 1 1 1 1 1 0 0 1 1 0 1 1 Advanced SIMD load single structure to all lanes 1 1 1 1 1 0 0 0 0 != 1111 1 0 0 UNALLOCATED 1 1 1 1 1 0 1 0 0 1 1 1 1 0 0 1 UNALLOCATED 1 1 1 0 0 UNALLOCATED 1 0 1 1 1 0 Push and Pop 1 1 1 1 1 0 0 1 1 1 != 1111 Load/store, signed (positive immediate) 0 1 0 0 1 Load literal 1 0 1 1 0 0 1 0 Extend 1 1 1 1 0 0 1 1 1 0 1 1 1 0 0 Miscellaneous system 1 1 1 0 1 1 1 0 1 1 0 1 UNALLOCATED 1 1 1 0 1 1 1 0 1 1 1 1 0 1 0 1 Floating-point move special register 1 1 1 0 1 1 1 0 0 0 0 1 0 1 0 1 Floating-point 32-bit move 1 1 1 1 1 0 0 1 0 1 != 1111 0 0 1 UNALLOCATED 1 1 1 1 1 1 1 0 1 0 0 0 Advanced SIMD and floating-point multiply with accumulate 0 1 0 0 0 1 != 11 Add, subtract, compare, move (two high registers) 1 1 1 1 1 1 1 1 1 1 1 1 1 0 Advanced SIMD duplicate (scalar) 1 1 1 0 1 0 0 0 1 1 0 0 1 Load/store exclusive byte/half/dual 1 1 1 0 1 1 1 0 1 1 1 1 0 0 0 Floating-point move immediate 1 1 0 1 1 1 1 Exception generation 1 1 1 1 1 1 1 0 1 0 0 1 0 != 00 0 Floating-point minNum/maxNum 1 1 1 0 1 1 1 0 1 1 1 1 System register 32-bit move 0 1 0 1 Load/store (register offset) 1 1 1 1 1 0 1 0 1 1 1 1 1 1 0 Data-processing (two source registers) 1 1 1 1 1 0 1 1 0 0 1 UNALLOCATED 1 1 1 0 1 1 1 0 1 0 1 1 1 Advanced SIMD 8/16/32-bit element move/duplicate 1 1 1 1 1 1 1 1 1 1 1 1 0 0 Advanced SIMD table permute 1 1 1 0 1 1 1 0 != 1x11 1 0 0 Floating-point data-processing (three registers) 1 1 1 0 1 1 1 0 1 0 1 0 1 0 1 UNALLOCATED 1 1 1 0 1 0 0 0 0 1 0 Load/store exclusive 1 1 1 1 1 0 0 1 0 1 != 1111 0 0 0 0 0 1 UNALLOCATED 1 1 1 0 0 Unconditional branch 1 1 1 1 0 0 1 1 1 1 0 1 1 0 0 Exception return 0 0 1 Add, subtract, compare, move (one low register and immediate) 1 1 1 1 1 0 0 0 1 1 1 1 Load, unsigned (literal) 1 1 1 1 0 1 1 0 Unconditional branch and link exchange 1 1 1 0 1 1 1 0 1 1 0 1 0 1 0 1 UNALLOCATED 1 1 1 1 0 1 0 0 0 0 Data-processing (simple immediate) 1 1 1 1 1 0 0 0 0 != 1111 0 0 1 UNALLOCATED 1 1 1 1 1 1 0 1 0 Advanced SIMD three registers of the same length extension 1 1 1 1 1 0 1 1 0 1 UNALLOCATED 1 0 1 1 1 0 1 0 != 10 Reverse bytes 0 0 0 1 1 0 Add, subtract (three low registers) 1 1 1 1 1 0 0 0 0 != 1111 0 0 0 1 UNALLOCATED 1 1 1 1 1 0 1 1 0 0 0 Multiply and absolute difference 1 1 1 1 0 0 0 Data-processing (modified immediate) 1 1 1 1 1 0 0 1 0 1 != 1111 1 1 1 Load/store, signed (immediate, pre-indexed) 1 1 1 1 1 0 0 0 0 != 1111 1 1 1 Load/store, unsigned (immediate, pre-indexed) 1 1 1 0 1 0 0 0 Load/store multiple 1 0 1 1 0 1 1 1 UNALLOCATED 1 1 1 1 1 0 0 1 0 1 != 1111 0 1 UNALLOCATED 1 0 1 1 0 0 0 0 Adjust SP (immediate) 1 1 0 0 UNALLOCATED 1 1 1 1 1 0 0 1 0 1 != 1111 1 0 0 UNALLOCATED 1 1 1 0 1 1 1 0 0 0 1 1 0 1 0 1 UNALLOCATED 1 1 1 1 1 0 1 0 1 1 1 1 1 0 Parallel add-subtract 0 1 0 0 0 0 Data-processing (two low registers) 1 1 1 1 0 1 1 1 1 0 0 1 1 0 0 UNALLOCATED 1 1 1 1 1 0 0 0 0 != 1111 0 0 0 0 0 0 Load/store, unsigned (register offset) 1 1 1 1 1 0 0 0 0 != 1111 0 0 0 0 0 1 UNALLOCATED 1 1 1 0 1 0 0 * 1 * 1 1 1 1 Load dual (literal) 1 1 1 1 1 0 1 0 0 1 1 1 1 0 0 0 1 UNALLOCATED 1 0 1 0 Add PC/SP (immediate) 0 0 0 1 1 1 Add, subtract (two low registers and immediate) 1 1 1 1 1 1 1 1 0 0 0 0 1 Advanced SIMD one register and modified immediate 1 1 1 0 1 0 0 0 1 1 0 1 0 0 0 Table branch 1 1 1 0 1 1 1 0 0 0 0 1 0 0 0 1 UNALLOCATED 1 1 1 0 1 0 0 0 1 1 0 0 0 0 0 UNALLOCATED 1 1 1 0 1 0 0 1 1 1 != 1111 Load/store dual (immediate, pre-indexed) 1 1 1 1 0 0 1 1 1 1 1 1 0 0 0 MRS (special) 1 1 1 1 0 1 1 1 1 0 0 0 1 0 1 0 UNALLOCATED 1 1 1 0 1 0 0 1 1 0 != 1111 Load/store dual (immediate) 1 1 1 0 1 0 0 0 1 1 0 1 Load-acquire / Store-release 1 1 1 1 0 1 0 1 0 0 0 Move Wide (16-bit immediate) 1 0 0 1 Load/store (SP-relative) 1 0 1 1 0 1 1 0 0 1 Change Processor State 1 1 1 1 0 1 0 1 Unconditional branch 1 1 1 0 1 1 0 0 0 0 1 0 Advanced SIMD and floating-point 64-bit move 1 1 1 1 0 1 0 1 1 0 0 UNALLOCATED 1 1 1 1 1 0 1 0 != 1111 UNALLOCATED 1 1 1 0 1 1 1 0 0 1 1 0 1 0 1 UNALLOCATED 1 0 1 1 1 1 1 0 Software breakpoint 1 1 1 1 1 0 0 1 1 1 1 1 1 Load, signed (literal) 1 1 1 0 1 1 0 0 0 0 1 1 1 System register 64-bit move 1 1 1 1 0 0 1 1 1 1 0 0 1 0 0 Branch and Exchange Jazelle 1 1 1 1 0 0 1 1 1 0 1 0 1 0 0 0 0 0 Hints 1 1 1 0 1 0 0 0 1 1 != 1111 Load/store dual (immediate, post-indexed) 1 1 1 1 1 1 1 1 1 1 1 0 0 Advanced SIMD two registers misc 1 1 1 1 0 0 1 1 1 0 0 1 0 0 1 MSR (banked) 1 1 1 1 1 0 1 0 0 1 1 1 1 0 1 UNALLOCATED 1 1 1 1 1 0 0 0 0 != 1111 1 0 1 Load/store, unsigned (immediate, post-indexed) 0 0 0 != 11 Shift (immediate) 1 1 1 1 1 0 0 1 0 1 != 1111 1 0 1 Load/store, signed (immediate, post-indexed) 1 1 1 1 1 0 1 0 1 1 1 1 1 1 1 UNALLOCATED 1 1 1 1 1 0 0 1 1 0 != 11 Advanced SIMD load/store single structure to one lane 1 1 1 1 0 0 1 1 1 0 0 1 0 0 0 MSR (special) 1 0 1 1 0 1 1 0 1 UNALLOCATED 1 1 1 1 0 1 1 1 1 1 0 1 0 0 UNALLOCATED 1 0 1 1 0 1 Compare and branch zero/non-zero 1 1 1 0 1 1 1 0 0 0 0 1 0 0 1 1 Floating-point 16-bit move 1 1 1 1 1 1 1 1 != 11 0 0 Advanced SIMD three registers of different lengths 1 1 1 1 1 1 1 1 != 11 1 0 Advanced SIMD two registers and a scalar 1 1 1 0 1 1 0 1 1 0 UNALLOCATED 1 1 0 0 Load/store multiple 1 1 1 1 1 0 0 1 0 1 != 1111 0 0 0 0 0 0 Load/store, signed (register offset) 1 1 1 0 1 1 0 != 00x0 1 0 Advanced SIMD and floating-point load/store 1 0 1 1 1 1 1 1 != 0000 If-Then 1 1 1 1 1 1 1 0 Advanced SIMD three registers of the same length 1 1 1 1 1 0 0 1 0 0 Advanced SIMD load/store multiple structures 1 1 1 0 1 0 1 Data-processing (shifted register) 1 0 0 0 Load/store halfword (immediate offset) 1 1 1 1 0 != 111x 1 0 0 Conditional branch 1 1 1 1 1 0 0 0 0 != 1111 0 1 UNALLOCATED 0 1 0 0 0 1 1 1 Branch and exchange 1 1 1 0 1 1 0 != 00x0 1 1 1 System register Load/Store 1 1 1 1 1 0 0 1 0 1 != 1111 0 0 0 0 1 UNALLOCATED 1 1 1 1 0 1 1 1 1 1 1 1 0 0 Exception generation 1 0 1 1 1 0 1 0 1 0 Halting breakpoint 1 1 1 1 1 0 1 0 0 1 1 1 1 1 Register extends 1 1 1 1 1 1 1 1 != 000xxxxxxxxxxx0 1 Advanced SIMD two registers and shift amount 1 1 1 1 1 0 0 0 1 != 1111 Load/store, unsigned (positive immediate) 1 1 1 1 0 1 1 1 1 0 1 1 0 0 UNALLOCATED 1 1 1 1 1 0 0 1 0 1 != 1111 1 1 1 0 Load/store, signed (unprivileged) 1 1 1 1 0 0 1 1 1 1 1 1 0 0 1 MRS (banked) 1 1 1 1 1 1 1 0 1 1 1 1 1 0 != 00 1 0 Floating-point directed convert to integer 1 1 1 1 1 1 1 0 0 1 0 != 00 0 0 Floating-point conditional select 1 1 1 1 1 1 1 0 1 1 1 0 0 0 0 1 0 != 00 1 0 Floating-point extraction and insertion 1 1 1 1 0 0 1 1 1 0 1 0 1 0 0 != 000 Change processor state 1 0 1 1 0 1 1 0 0 0 1 UNALLOCATED 1 0 1 1 1 0 0 0 UNALLOCATED 1 1 1 1 0 1 1 0 0 Saturate, Bitfield 1 0 1 1 1 1 1 1 0 0 0 0 Hints 1 1 1 1 1 0 0 0 0 != 1111 0 0 0 0 1 UNALLOCATED 1 0 1 1 0 1 1 0 0 0 0 SETPAN 1 1 1 1 1 0 0 1 0 1 != 1111 1 1 0 0 Load/store, signed (negative immediate) 1 1 1 1 0 1 1 1 Unconditional branch and link Shift (immediate), add, subtract, move, and compare 0 0 0 1 1 0 Decode fields Instruction page Encoding S 0 ADD, ADDS (register) T1 1 SUB, SUBS (register) T1 0 0 0 1 1 1 Decode fields Instruction page Encoding S 0 ADD, ADDS (immediate) T1 1 SUB, SUBS (immediate) T1 0 0 1 Decode fields Instruction page Encoding op 00 MOV, MOVS (immediate) T1 01 CMP (immediate) T1 10 ADD, ADDS (immediate) T2 11 SUB, SUBS (immediate) T2 0 0 0 != 11 Instruction page Encoding MOV, MOVS (register) T2 Data-processing 0 1 0 0 0 0 Decode fields Instruction page Encoding op 0000 AND, ANDS (register) T1 0001 EOR, EORS (register) T1 0010 MOV, MOVS (register-shifted register) T1, Logical shift left 0011 MOV, MOVS (register-shifted register) T1, Logical shift right 0100 MOV, MOVS (register-shifted register) T1, Arithmetic shift right 0101 ADC, ADCS (register) T1 0110 SBC, SBCS (register) T1 0111 MOV, MOVS (register-shifted register) T1, Rotate right 1000 TST (register) T1 1001 RSB, RSBS (immediate) T1 1010 CMP (register) T1 1011 CMN (register) T1 1100 ORR, ORRS (register) T1 1101 MUL, MULS T1 1110 BIC, BICS (register) T1 1111 MVN, MVNS (register) T1 Special data instructions and branch and exchange 0 1 0 0 0 1 != 11 Decode fields Instruction page Encoding op D:Rd Rs 00 != 1101 != 1101 ADD, ADDS (register) T2 00 1101 ADD, ADDS (SP plus register) T1 00 1101 != 1101 ADD, ADDS (SP plus register) T2 01 CMP (register) T2 10 MOV, MOVS (register) T1 0 1 0 0 0 1 1 1 (0) (0) (0) Decode fields Instruction page Encoding L 0 BX T1 1 BLX (register) T1 Load from Literal Pool 0 1 0 0 1 Instruction page Encoding LDR (literal) T1 Load/store single (register) 0 1 0 1 Decode fields Instruction page Encoding L B H 0 0 0 STR (register) T1 0 0 1 STRH (register) T1 0 1 0 STRB (register) T1 0 1 1 LDRSB (register) T1 1 0 0 LDR (register) T1 1 0 1 LDRH (register) T1 1 1 0 LDRB (register) T1 1 1 1 LDRSH (register) T1 Load/store single word and unsigned byte (immediate) 0 1 1 Decode fields Instruction page Encoding B L 0 0 STR (immediate) T1 0 1 LDR (immediate) T1 1 0 STRB (immediate) T1 1 1 LDRB (immediate) T1 Load/store single halfword (immediate) 1 0 0 0 Decode fields Instruction page Encoding L 0 STRH (immediate) T1 1 LDRH (immediate) T1 Load/store single (SP-relative) 1 0 0 1 Decode fields Instruction page Encoding L 0 STR (immediate) T2 1 LDR (immediate) T2 ADR and ADD (SP plus register) 1 0 1 0 Decode fields Instruction page Encoding SP 0 ADR T1 1 ADD, ADDS (SP plus immediate) T1 Miscellaneous 16-bit instructions 1 0 1 1 0 0 0 0 Decode fields Instruction page Encoding S 0 ADD, ADDS (SP plus immediate) T2 1 SUB, SUBS (SP minus immediate) T1 1 0 1 1 0 1 1 0 0 1 Decode fields Instruction page Encoding op flags 0 SETEND T1 1 0xxxx CPS, CPSID, CPSIE T1, Interrupt enable 1 1xxxx CPS, CPSID, CPSIE T1, Interrupt disable 1 0 1 1 0 1 Instruction page Encoding CBNZ, CBZ CBNZ 1 0 1 1 0 0 1 0 Decode fields Instruction page Encoding U B 0 0 SXTH T1 0 1 SXTB T1 1 0 UXTH T1 1 1 UXTB T1 1 0 1 1 1 0 1 0 1 0 Instruction page Encoding HLT T1 1 0 1 1 1 1 1 1 0 0 0 0 Decode fields Instruction page Encoding hint 0000 NOP T1 0001 YIELD T1 0010 WFE T1 0011 WFI T1 0100 SEV T1 0101 SEVL T1 011x Reserved hint, behaves as NOP 1xxx Reserved hint, behaves as NOP 1 0 1 1 1 1 1 1 != 0000 Instruction page Encoding IT 1 0 1 1 1 0 Decode fields Instruction page Encoding L 0 PUSH 1 POP 1 0 1 1 1 0 1 0 != 10 Decode fields Instruction page Encoding op 00 REV T1 01 REV16 T1 11 REVSH T1 1 0 1 1 0 1 1 0 0 0 0 (1) (0) (0) (0) Instruction page Encoding SETPAN T1 1 0 1 1 1 1 1 0 Instruction page Encoding BKPT T1 Load/Store multiple registers 1 1 0 0 Decode fields Instruction page Encoding L 0 STM, STMIA, STMEA T1 1 LDM, LDMIA, LDMFD T1 Conditional branch, and Supervisor Call 1 1 0 1 Instruction page Encoding B T1 1 1 0 1 1 1 1 Decode fields Instruction page Encoding S 0 UDF T1 1 SVC T1 16-bit Unconditional Branch 1 1 1 0 0 Instruction page Encoding B T2 Load/store multiple 1 1 1 0 1 0 0 0 Decode fields Instruction page Encoding opc L 00 0 SRS, SRSDA, SRSDB, SRSIA, SRSIB T1 00 1 RFE, RFEDA, RFEDB, RFEIA, RFEIB T1 01 0 STM, STMIA, STMEA T2 01 1 LDM, LDMIA, LDMFD T2 10 0 STMDB, STMFD T1 10 1 LDMDB, LDMEA T1 11 0 SRS, SRSDA, SRSDB, SRSIA, SRSIB T2 11 1 RFE, RFEDA, RFEDB, RFEIA, RFEIB T2 Floating-point data-processing 1 1 1 0 1 1 1 0 1 0 0 Decode fields Instruction page Encoding o0:o1 size o2 != 111 00 UNALLOCATED 000 01 0 VMLA (floating-point) T2, Half-precision scalar 000 01 1 VMLS (floating-point) T2, Half-precision scalar 000 10 0 VMLA (floating-point) T2, Single-precision scalar 000 10 1 VMLS (floating-point) T2, Single-precision scalar 000 11 0 VMLA (floating-point) T2, Double-precision scalar 000 11 1 VMLS (floating-point) T2, Double-precision scalar 001 01 0 VNMLS T1, Half-precision scalar 001 01 1 VNMLA T1, Half-precision scalar 001 10 0 VNMLS T1, Single-precision scalar 001 10 1 VNMLA T1, Single-precision scalar 001 11 0 VNMLS T1, Double-precision scalar 001 11 1 VNMLA T1, Double-precision scalar 010 01 0 VMUL (floating-point) T2, Half-precision scalar 010 01 1 VNMUL T1, Half-precision scalar 010 10 0 VMUL (floating-point) T2, Single-precision scalar 010 10 1 VNMUL T1, Single-precision scalar 010 11 0 VMUL (floating-point) T2, Double-precision scalar 010 11 1 VNMUL T1, Double-precision scalar 011 01 0 VADD (floating-point) T2, Half-precision scalar 011 01 1 VSUB (floating-point) T2, Half-precision scalar 011 10 0 VADD (floating-point) T2, Single-precision scalar 011 10 1 VSUB (floating-point) T2, Single-precision scalar 011 11 0 VADD (floating-point) T2, Double-precision scalar 011 11 1 VSUB (floating-point) T2, Double-precision scalar 100 01 0 VDIV T1, Half-precision scalar 100 10 0 VDIV T1, Single-precision scalar 100 11 0 VDIV T1, Double-precision scalar 101 01 0 VFNMS T1, Half-precision scalar 101 01 1 VFNMA T1, Half-precision scalar 101 10 0 VFNMS T1, Single-precision scalar 101 10 1 VFNMA T1, Single-precision scalar 101 11 0 VFNMS T1, Double-precision scalar 101 11 1 VFNMA T1, Double-precision scalar 110 01 0 VFMA T2, Half-precision scalar 110 01 1 VFMS T2, Half-precision scalar 110 10 0 VFMA T2, Single-precision scalar 110 10 1 VFMS T2, Single-precision scalar 110 11 0 VFMA T2, Double-precision scalar 110 11 1 VFMS T2, Double-precision scalar 1 1 1 0 1 1 1 0 1 1 1 1 0 1 0 Decode fields Instruction page Encoding o1 opc2 size o3 00 UNALLOCATED 0 000 01 0 UNALLOCATED 0 000 01 1 VABS T2, Half-precision scalar 0 000 10 0 VMOV (register) T2, Single-precision scalar 0 000 10 1 VABS T2, Single-precision scalar 0 000 11 0 VMOV (register) T2, Double-precision scalar 0 000 11 1 VABS T2, Double-precision scalar 0 001 01 0 VNEG T2, Half-precision scalar 0 001 01 1 VSQRT T1, Half-precision scalar 0 001 10 0 VNEG T2, Single-precision scalar 0 001 10 1 VSQRT T1, Single-precision scalar 0 001 11 0 VNEG T2, Double-precision scalar 0 001 11 1 VSQRT T1, Double-precision scalar 0 010 01 UNALLOCATED 0 010 10 0 VCVTB T1, Half-precision to single-precision 0 010 10 1 VCVTT T1, Half-precision to single-precision 0 010 11 0 VCVTB T1, Half-precision to double-precision 0 010 11 1 VCVTT T1, Half-precision to double-precision 0 011 01 0 VCVTB (BFloat16) T1 0 011 01 1 VCVTT (BFloat16) T1 0 011 10 0 VCVTB T1, Single-precision to half-precision 0 011 10 1 VCVTT T1, Single-precision to half-precision 0 011 11 0 VCVTB T1, Double-precision to half-precision 0 011 11 1 VCVTT T1, Double-precision to half-precision 0 100 01 0 VCMP T1, Half-precision scalar 0 100 01 1 VCMPE T1, Half-precision scalar 0 100 10 0 VCMP T1, Single-precision scalar 0 100 10 1 VCMPE T1, Single-precision scalar 0 100 11 0 VCMP T1, Double-precision scalar 0 100 11 1 VCMPE T1, Double-precision scalar 0 101 01 0 VCMP T2, Half-precision scalar 0 101 01 1 VCMPE T2, Half-precision scalar 0 101 10 0 VCMP T2, Single-precision scalar 0 101 10 1 VCMPE T2, Single-precision scalar 0 101 11 0 VCMP T2, Double-precision scalar 0 101 11 1 VCMPE T2, Double-precision scalar 0 110 01 0 VRINTR T1, Half-precision scalar 0 110 01 1 VRINTZ (floating-point) T1, Half-precision scalar 0 110 10 0 VRINTR T1, Single-precision scalar 0 110 10 1 VRINTZ (floating-point) T1, Single-precision scalar 0 110 11 0 VRINTR T1, Double-precision scalar 0 110 11 1 VRINTZ (floating-point) T1, Double-precision scalar 0 111 01 0 VRINTX (floating-point) T1, Half-precision scalar 0 111 01 1 UNALLOCATED 0 111 10 0 VRINTX (floating-point) T1, Single-precision scalar 0 111 10 1 VCVT (between double-precision and single-precision) T1, Single-precision to double-precision 0 111 11 0 VRINTX (floating-point) T1, Double-precision scalar 0 111 11 1 VCVT (between double-precision and single-precision) T1, Double-precision to single-precision 1 000 01 VCVT (integer to floating-point, floating-point) T1, Half-precision scalar 1 000 10 VCVT (integer to floating-point, floating-point) T1, Single-precision scalar 1 000 11 VCVT (integer to floating-point, floating-point) T1, Double-precision scalar 1 001 01 UNALLOCATED 1 001 10 UNALLOCATED 1 001 11 0 UNALLOCATED 1 001 11 1 VJCVT T1 1 01x 01 VCVT (between floating-point and fixed-point, floating-point) T1, Half-precision scalar 1 01x 10 VCVT (between floating-point and fixed-point, floating-point) T1, Single-precision scalar 1 01x 11 VCVT (between floating-point and fixed-point, floating-point) T1, Double-precision scalar 1 100 01 0 VCVTR T1, Half-precision scalar 1 100 01 1 VCVT (floating-point to integer, floating-point) T1, Half-precision scalar 1 100 10 0 VCVTR T1, Single-precision scalar 1 100 10 1 VCVT (floating-point to integer, floating-point) T1, Single-precision scalar 1 100 11 0 VCVTR T1, Double-precision scalar 1 100 11 1 VCVT (floating-point to integer, floating-point) T1, Double-precision scalar 1 101 01 0 VCVTR T1, Half-precision scalar 1 101 01 1 VCVT (floating-point to integer, floating-point) T1, Half-precision scalar 1 101 10 0 VCVTR T1, Single-precision scalar 1 101 10 1 VCVT (floating-point to integer, floating-point) T1, Single-precision scalar 1 101 11 0 VCVTR T1, Double-precision scalar 1 101 11 1 VCVT (floating-point to integer, floating-point) T1, Double-precision scalar 1 11x 01 VCVT (between floating-point and fixed-point, floating-point) T1, Half-precision scalar 1 11x 10 VCVT (between floating-point and fixed-point, floating-point) T1, Single-precision scalar 1 11x 11 VCVT (between floating-point and fixed-point, floating-point) T1, Double-precision scalar 1 1 1 0 1 1 1 0 1 1 1 1 0 (0) 0 (0) 0 Decode fields Instruction page Encoding size 00 UNALLOCATED 01 VMOV (immediate) T2, Half-precision scalar 10 VMOV (immediate) T2, Single-precision scalar 11 VMOV (immediate) T2, Double-precision scalar Load/store dual, load/store exclusive, load-acquire/store-release, and table branch 1 1 1 0 1 0 0 1 1 1 1 1 Decode fields Instruction page Encoding L 1 LDRD (literal) T1 1 1 1 0 1 0 0 0 1 1 0 1 Decode fields Instruction page Encoding L op sz 0 0 00 STLB T1 0 0 01 STLH T1 0 0 10 STL T1 0 0 11 UNALLOCATED 0 1 00 STLEXB T1 0 1 01 STLEXH T1 0 1 10 STLEX T1 0 1 11 STLEXD T1 1 0 00 LDAB T1 1 0 01 LDAH T1 1 0 10 LDA T1 1 0 11 UNALLOCATED 1 1 00 LDAEXB T1 1 1 01 LDAEXH T1 1 1 10 LDAEX T1 1 1 11 LDAEXD T1 1 1 1 0 1 0 0 1 1 0 != 1111 Decode fields Instruction page Encoding L 0 STRD (immediate) T1, Offset 1 LDRD (immediate) T1, Offset 1 1 1 0 1 0 0 0 1 1 != 1111 Decode fields Instruction page Encoding L 0 STRD (immediate) T1, Post-indexed 1 LDRD (immediate) T1, Post-indexed 1 1 1 0 1 0 0 1 1 1 != 1111 Decode fields Instruction page Encoding L 0 STRD (immediate) T1, Pre-indexed 1 LDRD (immediate) T1, Pre-indexed 1 1 1 0 1 0 0 0 0 1 0 Decode fields Instruction page Encoding L 0 STREX T1 1 LDREX T1 1 1 1 0 1 0 0 0 1 1 0 0 1 Decode fields Instruction page Encoding L sz 0 00 STREXB T1 0 01 STREXH T1 0 10 UNALLOCATED 0 11 STREXD T1 1 00 LDREXB T1 1 01 LDREXH T1 1 10 UNALLOCATED 1 11 LDREXD T1 1 1 1 0 1 0 0 0 1 1 0 1 (1) (1) (1) (1) (0) (0) (0) (0) 0 0 0 Instruction page Encoding TBB, TBH Halfword Advanced SIMD and System register 32-bit move 1 1 1 0 1 1 1 0 1 0 1 1 1 (0) (0) (0) (0) Decode fields Instruction page Encoding opc1 L opc2 0xx 0 VMOV (general-purpose register to scalar) T1 1 VMOV (scalar to general-purpose register) T1 1xx 0 0x VDUP (general-purpose register) T1 1xx 0 1x UNALLOCATED 1 1 1 0 1 1 1 0 0 0 0 1 0 0 1 (0) (0) 1 (0) (0) (0) (0) Instruction page Encoding VMOV (between general-purpose register and half-precision) T1, To general-purpose register 1 1 1 0 1 1 1 0 0 0 0 1 0 1 0 (0) (0) 1 (0) (0) (0) (0) Instruction page Encoding VMOV (between general-purpose register and single-precision) T1, To general-purpose register 1 1 1 0 1 1 1 0 1 1 1 1 0 1 0 (0) (0) (0) 1 (0) (0) (0) (0) Decode fields Instruction page Encoding L 0 VMSR T1 1 VMRS T1 1 1 1 0 1 1 1 0 1 1 1 1 Decode fields Instruction page Encoding L 0 MCR T1 1 MRC T1 Advanced SIMD and System register load/store and 64-bit move 1 1 1 0 1 1 0 0 0 0 1 0 Decode fields Instruction page Encoding D op size opc2 o3 0 UNALLOCATED 1 0 UNALLOCATED 1 0x 00 1 UNALLOCATED 1 01 UNALLOCATED 1 0 10 00 1 VMOV (between two general-purpose registers and two single-precision registers) T1, From general-purpose registers 1 0 11 00 1 VMOV (between two general-purpose registers and a doubleword floating-point register) T1, From general-purpose registers 1 1x UNALLOCATED 1 1 10 00 1 VMOV (between two general-purpose registers and two single-precision registers) T1, To general-purpose registers 1 1 11 00 1 VMOV (between two general-purpose registers and a doubleword floating-point register) T1, To general-purpose registers 1 1 1 0 1 1 0 1 0 Decode fields Instruction page Encoding P U W L Rn size imm8 0 0 1 UNALLOCATED 0 1 0x UNALLOCATED 0 1 0 10 VSTM, VSTMDB, VSTMIA T2, Increment After 0 1 0 11 xxxxxxx0 VSTM, VSTMDB, VSTMIA T1, Increment After 0 1 0 11 xxxxxxx1 FSTMDBX, FSTMIAX T1, Increment After 0 1 1 10 VLDM, VLDMDB, VLDMIA T2, Increment After 0 1 1 11 xxxxxxx0 VLDM, VLDMDB, VLDMIA T1, Increment After 0 1 1 11 xxxxxxx1 FLDM*X (FLDMDBX, FLDMIAX) T1, Increment After 1 0 0 01 VSTR T1, Half-precision scalar 1 0 0 10 VSTR T1, Single-precision scalar 1 0 0 11 VSTR T1, Double-precision scalar 1 0 1 != 1111 01 VLDR (immediate) T1, Half-precision scalar 1 0 1 != 1111 10 VLDR (immediate) T1, Single-precision scalar 1 0 1 != 1111 11 VLDR (immediate) T1, Double-precision scalar 1 0 1 0x UNALLOCATED 1 0 1 0 10 VSTM, VSTMDB, VSTMIA T2, Decrement Before 1 0 1 0 11 xxxxxxx0 VSTM, VSTMDB, VSTMIA T1, Decrement Before 1 0 1 0 11 xxxxxxx1 FSTMDBX, FSTMIAX T1, Decrement Before 1 0 1 1 10 VLDM, VLDMDB, VLDMIA T2, Decrement Before 1 0 1 1 11 xxxxxxx0 VLDM, VLDMDB, VLDMIA T1, Decrement Before 1 0 1 1 11 xxxxxxx1 FLDM*X (FLDMDBX, FLDMIAX) T1, Decrement Before 1 0 1 1111 01 VLDR (literal) T1, Half-precision scalar 1 0 1 1111 10 VLDR (literal) T1, Single-precision scalar 1 0 1 1111 11 VLDR (literal) T1, Double-precision scalar 1 1 1 UNALLOCATED 1 1 1 0 1 1 0 0 0 0 1 1 1 Decode fields Instruction page Encoding D L 0 UNALLOCATED 1 0 MCRR T1 1 1 MRRC T1 1 1 1 0 1 1 0 1 1 1 Decode fields Instruction page Encoding P:U:W D L Rn CRd cp15 != 000 != 0101 0 UNALLOCATED != 000 0 1 1111 0101 0 LDC (literal) T1 != 000 1 UNALLOCATED != 000 1 0101 0 UNALLOCATED 0x1 0 0 0101 0 STC T1, Post-indexed 0x1 0 1 != 1111 0101 0 LDC (immediate) T1, Post-indexed 010 0 0 0101 0 STC T1, Unindexed 010 0 1 != 1111 0101 0 LDC (immediate) T1, Unindexed 1x0 0 0 0101 0 STC T1, Offset 1x0 0 1 != 1111 0101 0 LDC (immediate) T1, Offset 1x1 0 0 0101 0 STC T1, Pre-indexed 1x1 0 1 != 1111 0101 0 LDC (immediate) T1, Pre-indexed Data-processing (shifted register) 1 1 1 0 1 0 1 (0) Decode fields Instruction page Encoding op1 S Rn imm3:imm2:stype Rd 0000 0 != 0000011 AND, ANDS (register) T2, AND, shift or rotate by value 0000 0 0000011 AND, ANDS (register) T2, AND, rotate right with extend 0000 1 != 0000011 != 1111 AND, ANDS (register) T2, ANDS, shift or rotate by value 0000 1 != 0000011 1111 TST (register) T2, Shift or rotate by value 0000 1 0000011 != 1111 AND, ANDS (register) T2, ANDS, rotate right with extend 0000 1 0000011 1111 TST (register) T2, Rotate right with extend 0001 != 0000011 BIC, BICS (register) T2, BICS, shift or rotate by value 0001 0000011 BIC, BICS (register) T2, BICS, rotate right with extend 0010 0 != 1111 != 0000011 ORR, ORRS (register) T2, ORR, shift or rotate by value 0010 0 != 1111 0000011 ORR, ORRS (register) T2, ORR, rotate right with extend 0010 0 1111 != 0000011 MOV, MOVS (register) T3, MOV, shift or rotate by value 0010 0 1111 0000011 MOV, MOVS (register) T3, MOV, rotate right with extend 0010 1 != 1111 != 0000011 ORR, ORRS (register) T2, ORRS, shift or rotate by value 0010 1 != 1111 0000011 ORR, ORRS (register) T2, ORRS, rotate right with extend 0010 1 1111 != 0000011 MOV, MOVS (register) T3, MOVS, shift or rotate by value 0010 1 1111 0000011 MOV, MOVS (register) T3, MOVS, rotate right with extend 0011 0 != 1111 != 0000011 ORN, ORNS (register) ORN, shift or rotate by value 0011 0 != 1111 0000011 ORN, ORNS (register) ORN, rotate right with extend 0011 0 1111 != 0000011 MVN, MVNS (register) T2, MVN, shift or rotate by value 0011 0 1111 0000011 MVN, MVNS (register) T2, MVN, rotate right with extend 0011 1 != 1111 != 0000011 ORN, ORNS (register) ORNS, shift or rotate by value 0011 1 != 1111 0000011 ORN, ORNS (register) ORNS, rotate right with extend 0011 1 1111 != 0000011 MVN, MVNS (register) T2, MVNS, shift or rotate by value 0011 1 1111 0000011 MVN, MVNS (register) T2, MVNS, rotate right with extend 0100 0 != 0000011 EOR, EORS (register) T2, EOR, shift or rotate by value 0100 0 0000011 EOR, EORS (register) T2, EOR, rotate right with extend 0100 1 != 0000011 != 1111 EOR, EORS (register) T2, EORS, shift or rotate by value 0100 1 != 0000011 1111 TEQ (register) T1, Shift or rotate by value 0100 1 0000011 != 1111 EOR, EORS (register) T2, EORS, rotate right with extend 0100 1 0000011 1111 TEQ (register) T1, Rotate right with extend 0101 UNALLOCATED 0110 0 xxxxx00 PKHBT, PKHTB T1, PKHBT 0110 0 xxxxx01 UNALLOCATED 0110 0 xxxxx10 PKHBT, PKHTB T1, PKHTB 0110 0 xxxxx11 UNALLOCATED 0111 UNALLOCATED 1000 0 != 1101 != 0000011 ADD, ADDS (register) T3, ADD, shift or rotate by value 1000 0 != 1101 0000011 ADD, ADDS (register) T3, ADD, rotate right with extend 1000 0 1101 != 0000011 ADD, ADDS (SP plus register) T3, ADD, shift or rotate by value 1000 0 1101 0000011 ADD, ADDS (SP plus register) T3, ADD, rotate right with extend 1000 1 != 0000011 1111 CMN (register) T2, Shift or rotate by value 1000 1 != 1101 != 0000011 != 1111 ADD, ADDS (register) T3, ADDS, shift or rotate by value 1000 1 != 1101 0000011 != 1111 ADD, ADDS (register) T3, ADDS, rotate right with extend 1000 1 0000011 1111 CMN (register) T2, Rotate right with extend 1000 1 1101 != 0000011 != 1111 ADD, ADDS (SP plus register) T3, ADDS, shift or rotate by value 1000 1 1101 0000011 != 1111 ADD, ADDS (SP plus register) T3, ADDS, rotate right with extend 1001 UNALLOCATED 1010 != 0000011 ADC, ADCS (register) T2, ADCS, shift or rotate by value 1010 0000011 ADC, ADCS (register) T2, ADCS, rotate right with extend 1011 != 0000011 SBC, SBCS (register) T2, SBCS, shift or rotate by value 1011 0000011 SBC, SBCS (register) T2, SBCS, rotate right with extend 1100 UNALLOCATED 1101 0 != 1101 != 0000011 SUB, SUBS (register) T2, SUB, shift or rotate by value 1101 0 != 1101 0000011 SUB, SUBS (register) T2, SUB, rotate right with extend 1101 0 1101 != 0000011 SUB, SUBS (SP minus register) T1, SUB, shift or rotate by value 1101 0 1101 0000011 SUB, SUBS (SP minus register) T1, SUB, rotate right with extend 1101 1 != 0000011 1111 CMP (register) T3, Shift or rotate by value 1101 1 != 1101 != 0000011 != 1111 SUB, SUBS (register) T2, SUBS, shift or rotate by value 1101 1 != 1101 0000011 != 1111 SUB, SUBS (register) T2, SUBS, rotate right with extend 1101 1 0000011 1111 CMP (register) T3, Rotate right with extend 1101 1 1101 != 0000011 != 1111 SUB, SUBS (SP minus register) T1, SUBS, shift or rotate by value 1101 1 1101 0000011 != 1111 SUB, SUBS (SP minus register) T1, SUBS, rotate right with extend 1110 != 0000011 RSB, RSBS (register) T1, RSBS, shift or rotate by value 1110 0000011 RSB, RSBS (register) T1, RSBS, rotate right with extend 1111 UNALLOCATED Additional Advanced SIMD and floating-point instructions 1 1 1 1 1 1 1 0 1 1 0 Decode fields Instruction page Encoding op1 op2 op4 Q U 0 00 0 UNALLOCATED 0 00 1 0 0 VDOT (by element) T1, 64-bit SIMD vector 0 00 1 1 UNALLOCATED 0 00 1 1 0 VDOT (by element) T1, 128-bit SIMD vector 0 01 0 UNALLOCATED 0 10 0 UNALLOCATED 0 10 1 0 0 VSDOT (by element) T1, 64-bit SIMD vector 0 10 1 0 1 VUDOT (by element) T1, 64-bit SIMD vector 0 10 1 1 0 VSDOT (by element) T1, 128-bit SIMD vector 0 10 1 1 1 VUDOT (by element) T1, 128-bit SIMD vector 0 11 UNALLOCATED 1 0 UNALLOCATED 1 00 1 0 0 VUSDOT (by element) T1, 64-bit SIMD vector 1 00 1 0 1 VSUDOT (by element) T1, 64-bit SIMD vector 1 00 1 1 0 VUSDOT (by element) T1, 128-bit SIMD vector 1 00 1 1 1 VSUDOT (by element) T1, 128-bit SIMD vector 1 01 1 UNALLOCATED 1 1x 1 UNALLOCATED 1 1 1 1 1 1 1 0 1 0 0 0 Decode fields Instruction page Encoding op1 op2 Q U 0 0 VCMLA (by element) T1, 128-bit SIMD vector of half-precision floating-point 0 00 1 VFMAL (by scalar) T1, 128-bit SIMD vector 0 01 1 VFMSL (by scalar) T1, 128-bit SIMD vector 0 10 1 UNALLOCATED 0 11 1 VFMAB, VFMAT (BFloat16, by scalar) T1 1 0 0 VCMLA (by element) T1, 64-bit SIMD vector of single-precision floating-point 1 1 UNALLOCATED 1 1 0 VCMLA (by element) T1, 128-bit SIMD vector of single-precision floating-point 1 1 1 1 1 1 0 1 0 Decode fields Instruction page Encoding op1 op2 op3 op4 Q U x1 0x 0 0 0 0 VCADD T1, 64-bit SIMD vector x1 0x 0 0 0 1 UNALLOCATED x1 0x 0 0 1 0 VCADD T1, 128-bit SIMD vector x1 0x 0 0 1 1 UNALLOCATED 00 0x 0 0 UNALLOCATED 00 0x 0 1 UNALLOCATED 00 00 1 0 0 0 UNALLOCATED 00 00 1 0 0 1 UNALLOCATED 00 00 1 0 1 0 VMMLA T1 00 00 1 0 1 1 UNALLOCATED 00 00 1 1 0 0 VDOT (vector) T1, 64-bit SIMD vector 00 00 1 1 0 1 UNALLOCATED 00 00 1 1 1 0 VDOT (vector) T1, 128-bit SIMD vector 00 00 1 1 1 1 UNALLOCATED 00 01 1 0 UNALLOCATED 00 01 1 1 UNALLOCATED 00 10 0 0 1 VFMAL (vector) T1, 128-bit SIMD vector 00 10 0 1 UNALLOCATED 00 10 1 0 0 UNALLOCATED 00 10 1 0 1 0 VSMMLA T1 00 10 1 0 1 1 VUMMLA T1 00 10 1 1 0 0 VSDOT (vector) T1, 64-bit SIMD vector 00 10 1 1 0 1 VUDOT (vector) T1, 64-bit SIMD vector 00 10 1 1 1 0 VSDOT (vector) T1, 128-bit SIMD vector 00 10 1 1 1 1 VUDOT (vector) T1, 128-bit SIMD vector 00 11 0 0 1 VFMAB, VFMAT (BFloat16, vector) T1 00 11 0 1 UNALLOCATED 00 11 1 0 UNALLOCATED 00 11 1 1 UNALLOCATED 01 10 0 0 1 VFMSL (vector) T1, 128-bit SIMD vector 01 10 0 1 UNALLOCATED 01 10 1 0 0 UNALLOCATED 01 10 1 0 1 0 VUSMMLA T1 01 10 1 0 1 1 UNALLOCATED 01 10 1 1 0 0 VUSDOT (vector) T1, 64-bit SIMD vector 01 10 1 1 1 UNALLOCATED 01 10 1 1 1 0 VUSDOT (vector) T1, 128-bit SIMD vector 01 11 0 1 UNALLOCATED 01 11 1 0 UNALLOCATED 01 11 1 1 UNALLOCATED 1x 0 0 0 VCMLA T1, 128-bit SIMD vector 10 11 0 1 UNALLOCATED 10 11 1 0 UNALLOCATED 10 11 1 1 UNALLOCATED 11 11 0 1 UNALLOCATED 11 11 1 0 UNALLOCATED 11 11 1 1 UNALLOCATED 1 1 1 1 1 1 1 0 0 1 0 != 00 0 0 Decode fields Instruction page Encoding size 01 VSELEQ, VSELGE, VSELGT, VSELVS T1, Greater than, half-precision scalar 10 VSELEQ, VSELGE, VSELGT, VSELVS T1, Greater than, single-precision scalar 11 VSELEQ, VSELGE, VSELGT, VSELVS T1, Greater than, double-precision scalar 1 1 1 1 1 1 1 0 1 1 1 1 1 0 != 00 1 0 Decode fields Instruction page Encoding o1 RM size op 0 != 00 1 UNALLOCATED 0 00 01 0 VRINTA (floating-point) T1, Half-precision scalar 0 00 10 0 VRINTA (floating-point) T1, Single-precision scalar 0 00 11 0 VRINTA (floating-point) T1, Double-precision scalar 0 01 01 0 VRINTN (floating-point) T1, Half-precision scalar 0 01 10 0 VRINTN (floating-point) T1, Single-precision scalar 0 01 11 0 VRINTN (floating-point) T1, Double-precision scalar 0 10 01 0 VRINTP (floating-point) T1, Half-precision scalar 0 10 10 0 VRINTP (floating-point) T1, Single-precision scalar 0 10 11 0 VRINTP (floating-point) T1, Double-precision scalar 0 11 01 0 VRINTM (floating-point) T1, Half-precision scalar 0 11 10 0 VRINTM (floating-point) T1, Single-precision scalar 0 11 11 0 VRINTM (floating-point) T1, Double-precision scalar 1 00 01 VCVTA (floating-point) T1, Half-precision scalar 1 00 10 VCVTA (floating-point) T1, Single-precision scalar 1 00 11 VCVTA (floating-point) T1, Double-precision scalar 1 01 01 VCVTN (floating-point) T1, Half-precision scalar 1 01 10 VCVTN (floating-point) T1, Single-precision scalar 1 01 11 VCVTN (floating-point) T1, Double-precision scalar 1 10 01 VCVTP (floating-point) T1, Half-precision scalar 1 10 10 VCVTP (floating-point) T1, Single-precision scalar 1 10 11 VCVTP (floating-point) T1, Double-precision scalar 1 11 01 VCVTM (floating-point) T1, Half-precision scalar 1 11 10 VCVTM (floating-point) T1, Single-precision scalar 1 11 11 VCVTM (floating-point) T1, Double-precision scalar 1 1 1 1 1 1 1 0 1 1 1 0 0 0 0 1 0 != 00 1 0 Decode fields Instruction page Encoding size op 01 UNALLOCATED 10 0 VMOVX T1 10 1 VINS T1 11 UNALLOCATED 1 1 1 1 1 1 1 0 1 0 0 1 0 != 00 0 Decode fields Instruction page Encoding size op 01 0 VMAXNM T2, Half-precision scalar 01 1 VMINNM T2, Half-precision scalar 10 0 VMAXNM T2, Single-precision scalar 10 1 VMINNM T2, Single-precision scalar 11 0 VMAXNM T2, Double-precision scalar 11 1 VMINNM T2, Double-precision scalar Data-processing (modified immediate) 1 1 1 1 0 0 0 Decode fields Instruction page Encoding op1 S Rn Rd 0000 0 AND, ANDS (immediate) T1, AND 0000 1 != 1111 AND, ANDS (immediate) T1, ANDS 0000 1 1111 TST (immediate) T1 0001 BIC, BICS (immediate) T1, BICS 0010 0 != 1111 ORR, ORRS (immediate) T1, ORR 0010 0 1111 MOV, MOVS (immediate) T2, MOV 0010 1 != 1111 ORR, ORRS (immediate) T1, ORRS 0010 1 1111 MOV, MOVS (immediate) T2, MOVS 0011 0 != 1111 ORN, ORNS (immediate) Not flag setting 0011 0 1111 MVN, MVNS (immediate) T1, MVN 0011 1 != 1111 ORN, ORNS (immediate) Flag setting 0011 1 1111 MVN, MVNS (immediate) T1, MVNS 0100 0 EOR, EORS (immediate) T1, EOR 0100 1 != 1111 EOR, EORS (immediate) T1, EORS 0100 1 1111 TEQ (immediate) T1 0101 UNALLOCATED 011x UNALLOCATED 1000 0 != 1101 ADD, ADDS (immediate) T3, ADD 1000 0 1101 ADD, ADDS (SP plus immediate) T3, ADD 1000 1 != 1101 != 1111 ADD, ADDS (immediate) T3, ADDS 1000 1 1101 != 1111 ADD, ADDS (SP plus immediate) T3, ADDS 1000 1 1111 CMN (immediate) T1 1001 UNALLOCATED 1010 ADC, ADCS (immediate) T1, ADCS 1011 SBC, SBCS (immediate) T1, SBCS 1100 UNALLOCATED 1101 0 != 1101 SUB, SUBS (immediate) T3, SUB 1101 0 1101 SUB, SUBS (SP minus immediate) T2, SUB 1101 1 != 1101 != 1111 SUB, SUBS (immediate) T3, SUBS 1101 1 1101 != 1111 SUB, SUBS (SP minus immediate) T2, SUBS 1101 1 1111 CMP (immediate) T2 1110 RSB, RSBS (immediate) T2, RSBS 1111 UNALLOCATED Data-processing (plain binary immediate) 1 1 1 1 0 1 0 0 0 0 Decode fields Instruction page Encoding o1 o2 Rn 0 0 != 11x1 ADD, ADDS (immediate) T4 0 0 1101 ADD, ADDS (SP plus immediate) T4 0 0 1111 ADR T3 0 1 UNALLOCATED 1 0 UNALLOCATED 1 1 != 11x1 SUB, SUBS (immediate) T4 1 1 1101 SUB, SUBS (SP minus immediate) T3 1 1 1111 ADR T2 1 1 1 1 0 1 0 1 0 0 0 Decode fields Instruction page Encoding o1 0 MOV, MOVS (immediate) T3 1 MOVT T1 1 1 1 1 0 (0) 1 1 0 0 (0) Decode fields Instruction page Encoding op1 Rn imm3:imm2 000 SSAT T1, Logical shift left 001 != 00000 SSAT T1, Arithmetic shift right 001 00000 SSAT16 T1 010 SBFX T1 011 != 1111 BFI T1 011 1111 BFC T1 100 USAT T1, Logical shift left 101 != 00000 USAT T1, Arithmetic shift right 101 00000 USAT16 T1 110 UBFX T1 111 UNALLOCATED Branches and miscellaneous control 1 1 1 1 0 0 1 1 1 1 0 0 1 0 (0) 0 (1) (1) (1) (1) (0) (0) (0) (0) (0) (0) (0) (0) Instruction page Encoding BXJ T1 1 1 1 1 0 0 1 1 1 0 1 0 (1) (1) (1) (1) 1 0 (0) 0 (0) Decode fields Instruction page Encoding imod M 00 1 CPS, CPSID, CPSIE T2, Change mode 01 UNALLOCATED 10 CPS, CPSID, CPSIE T2, Interrupt enable and change mode 11 CPS, CPSID, CPSIE T2, Interrupt disable and change mode 1 1 1 1 0 1 0 0 Instruction page Encoding B T3 1 1 1 1 0 1 1 1 1 0 0 0 1 0 0 0 Decode fields Instruction page Encoding imm4 imm10 opt != 1111 UNALLOCATED 1111 != 0000000000 UNALLOCATED 1111 0000000000 00 UNALLOCATED 1111 0000000000 01 DCPS1 1111 0000000000 10 DCPS2 1111 0000000000 11 DCPS3 1 1 1 1 0 1 1 1 1 1 1 1 0 0 Decode fields Instruction page Encoding o1 o2 0 0 HVC T1 0 1 UNALLOCATED 1 0 SMC T1 1 1 UDF T2 1 1 1 1 0 0 1 1 1 1 0 1 1 0 (0) 0 (1) (1) (1) (1) Decode fields Instruction page Encoding Rn:imm8 != 111000000000 SUB, SUBS (immediate) T5 111000000000 ERET T1 1 1 1 1 0 0 1 1 1 0 1 0 (1) (1) (1) (1) 1 0 (0) 0 (0) 0 0 0 Decode fields Instruction page Encoding hint option 0000 0000 NOP T2 0000 0001 YIELD T2 0000 0010 WFE T2 0000 0011 WFI T2 0000 0100 SEV T2 0000 0101 SEVL T2 0000 011x Reserved hint, behaves as NOP 0000 1xxx Reserved hint, behaves as NOP 0001 0000 ESB T1 0001 0001 Reserved hint, behaves as NOP 0001 0010 TSB CSYNC T1 0001 0011 Reserved hint, behaves as NOP 0001 0100 CSDB T1 0001 0101 Reserved hint, behaves as NOP 0001 0110 CLRBHB T1 0001 0111 Reserved hint, behaves as NOP 0001 1xxx Reserved hint, behaves as NOP 001x Reserved hint, behaves as NOP 01xx Reserved hint, behaves as NOP 10xx Reserved hint, behaves as NOP 110x Reserved hint, behaves as NOP 1110 Reserved hint, behaves as NOP 1111 DBG T1 1 1 1 1 0 0 1 1 1 1 1 1 0 (0) 0 (0) (0) 1 (0) (0) (0) (0) Instruction page Encoding MRS (Banked register) T1 1 1 1 1 0 0 1 1 1 1 1 (1) (1) (1) (1) 1 0 (0) 0 (0) (0) 0 (0) (0) (0) (0) (0) Instruction page Encoding MRS T1 1 1 1 1 0 0 1 1 1 0 0 1 0 (0) 0 (0) (0) 1 (0) (0) (0) (0) Instruction page Encoding MSR (Banked register) T1 1 1 1 1 0 0 1 1 1 0 0 1 0 (0) 0 (0) (0) 0 (0) (0) (0) (0) (0) Instruction page Encoding MSR (register) T1 1 1 1 1 0 0 1 1 1 0 1 1 (1) (1) (1) (1) 1 0 (0) 0 (1) (1) (1) (1) Decode fields Instruction page Encoding opc option 000x UNALLOCATED 0010 CLREX T1 0011 UNALLOCATED 0100 != 0x00 DSB T1 0100 0000 SSBB T1 0100 0100 PSSBB T1 0101 DMB T1 0110 ISB T1 0111 SB T1 1xxx UNALLOCATED 1 1 1 1 0 1 0 1 Instruction page Encoding B T4 1 1 1 1 0 1 1 1 Instruction page Encoding BL, BLX (immediate) T1 1 1 1 1 0 1 1 0 Instruction page Encoding BL, BLX (immediate) T2 Load/store single 1 1 1 1 1 0 0 1 1 1 1 1 1 Decode fields Instruction page Encoding size Rt 00 != 1111 LDRSB (literal) T1 00 1111 PLI (immediate, literal) T3 01 != 1111 LDRSH (literal) T1 01 1111 Reserved hint, behaves as NOP 1x UNALLOCATED 1 1 1 1 1 0 0 0 1 1 1 1 Decode fields Instruction page Encoding size L Rt 0x 1 1111 PLD (literal) T1 00 1 != 1111 LDRB (literal) T1 01 1 != 1111 LDRH (literal) T1 10 1 LDR (literal) T2 11 UNALLOCATED 1 1 1 1 1 0 0 1 0 1 != 1111 1 0 1 Decode fields Instruction page Encoding size 00 LDRSB (immediate) T2, Post-indexed 01 LDRSH (immediate) T2, Post-indexed 1x UNALLOCATED 1 1 1 1 1 0 0 1 0 1 != 1111 1 1 1 Decode fields Instruction page Encoding size 00 LDRSB (immediate) T2, Pre-indexed 01 LDRSH (immediate) T2, Pre-indexed 1x UNALLOCATED 1 1 1 1 1 0 0 1 0 1 != 1111 1 1 0 0 Decode fields Instruction page Encoding size Rt 00 != 1111 LDRSB (immediate) T2, Offset 00 1111 PLI (immediate, literal) T2 01 != 1111 LDRSH (immediate) T2, Offset 01 1111 Reserved hint, behaves as NOP 1x UNALLOCATED 1 1 1 1 1 0 0 1 1 1 != 1111 Decode fields Instruction page Encoding size Rt 00 != 1111 LDRSB (immediate) T1 00 1111 PLI (immediate, literal) T1 01 != 1111 LDRSH (immediate) T1 01 1111 Reserved hint, behaves as NOP 1 1 1 1 1 0 0 1 0 1 != 1111 0 0 0 0 0 0 Decode fields Instruction page Encoding size Rt 00 != 1111 LDRSB (register) T2 00 1111 PLI (register) T1 01 != 1111 LDRSH (register) T2 01 1111 Reserved hint, behaves as NOP 1x UNALLOCATED 1 1 1 1 1 0 0 1 0 1 != 1111 1 1 1 0 Decode fields Instruction page Encoding size 00 LDRSBT T1 01 LDRSHT T1 1x UNALLOCATED 1 1 1 1 1 0 0 0 0 != 1111 1 0 1 Decode fields Instruction page Encoding size L 00 0 STRB (immediate) T3, Post-indexed 00 1 LDRB (immediate) T3, Post-indexed 01 0 STRH (immediate) T3, Post-indexed 01 1 LDRH (immediate) T3, Post-indexed 10 0 STR (immediate) T4, Post-indexed 10 1 LDR (immediate) T4, Post-indexed 11 UNALLOCATED 1 1 1 1 1 0 0 0 0 != 1111 1 1 1 Decode fields Instruction page Encoding size L 00 0 STRB (immediate) T3, Pre-indexed 00 1 LDRB (immediate) T3, Pre-indexed 01 0 STRH (immediate) T3, Pre-indexed 01 1 LDRH (immediate) T3, Pre-indexed 10 0 STR (immediate) T4, Pre-indexed 10 1 LDR (immediate) T4, Pre-indexed 11 UNALLOCATED 1 1 1 1 1 0 0 0 0 != 1111 1 1 0 0 Decode fields Instruction page Encoding size L Rt 00 0 STRB (immediate) T3, Offset 00 1 != 1111 LDRB (immediate) T3, Offset 00 1 1111 PLD, PLDW (immediate) T2, Preload read 01 0 STRH (immediate) T3, Offset 01 1 != 1111 LDRH (immediate) T3, Offset 01 1 1111 PLD, PLDW (immediate) T2, Preload write 10 0 STR (immediate) T4, Offset 10 1 LDR (immediate) T4, Offset 11 UNALLOCATED 1 1 1 1 1 0 0 0 1 != 1111 Decode fields Instruction page Encoding size L Rt 00 0 STRB (immediate) T2 00 1 != 1111 LDRB (immediate) T2 00 1 1111 PLD, PLDW (immediate) T1, Preload read 01 0 STRH (immediate) T2 01 1 != 1111 LDRH (immediate) T2 01 1 1111 PLD, PLDW (immediate) T1, Preload write 10 0 STR (immediate) T3 10 1 LDR (immediate) T3 1 1 1 1 1 0 0 0 0 != 1111 0 0 0 0 0 0 Decode fields Instruction page Encoding size L Rt 00 0 STRB (register) T2 00 1 != 1111 LDRB (register) T2 00 1 1111 PLD, PLDW (register) T1, Preload read 01 0 STRH (register) T2 01 1 != 1111 LDRH (register) T2 01 1 1111 PLD, PLDW (register) T1, Preload write 10 0 STR (register) T2 10 1 LDR (register) T2 11 UNALLOCATED 1 1 1 1 1 0 0 0 0 != 1111 1 1 1 0 Decode fields Instruction page Encoding size L 00 0 STRBT T1 00 1 LDRBT T1 01 0 STRHT T1 01 1 LDRHT T1 10 0 STRT T1 10 1 LDRT T1 11 UNALLOCATED Advanced SIMD element or structure load/store 1 1 1 1 1 0 0 1 1 0 1 1 Decode fields Instruction page Encoding L N a Rm 0 UNALLOCATED 1 00 != 11x1 VLD1 (single element to all lanes) T1, Post-indexed 1 00 1101 VLD1 (single element to all lanes) T1, Post-indexed 1 00 1111 VLD1 (single element to all lanes) T1, Offset 1 01 != 11x1 VLD2 (single 2-element structure to all lanes) T1, Post-indexed 1 01 1101 VLD2 (single 2-element structure to all lanes) T1, Post-indexed 1 01 1111 VLD2 (single 2-element structure to all lanes) T1, Offset 1 10 0 != 11x1 VLD3 (single 3-element structure to all lanes) T1, Post-indexed 1 10 0 1101 VLD3 (single 3-element structure to all lanes) T1, Post-indexed 1 10 0 1111 VLD3 (single 3-element structure to all lanes) T1, Offset 1 10 1 UNALLOCATED 1 11 != 11x1 VLD4 (single 4-element structure to all lanes) T1, Post-indexed 1 11 1101 VLD4 (single 4-element structure to all lanes) T1, Post-indexed 1 11 1111 VLD4 (single 4-element structure to all lanes) T1, Offset 1 1 1 1 1 0 0 1 0 0 Decode fields Instruction page Encoding L itype Rm 0 000x != 11x1 VST4 (multiple 4-element structures) T1, Post-indexed 0 000x 1101 VST4 (multiple 4-element structures) T1, Post-indexed 0 000x 1111 VST4 (multiple 4-element structures) T1, Offset 0 0010 != 11x1 VST1 (multiple single elements) T4, Post-indexed 0 0010 1101 VST1 (multiple single elements) T4, Post-indexed 0 0010 1111 VST1 (multiple single elements) T4, Offset 0 0011 != 11x1 VST2 (multiple 2-element structures) T2, Post-indexed 0 0011 1101 VST2 (multiple 2-element structures) T2, Post-indexed 0 0011 1111 VST2 (multiple 2-element structures) T2, Offset 0 010x != 11x1 VST3 (multiple 3-element structures) T1, Post-indexed 0 010x 1101 VST3 (multiple 3-element structures) T1, Post-indexed 0 010x 1111 VST3 (multiple 3-element structures) T1, Offset 0 0110 != 11x1 VST1 (multiple single elements) T3, Post-indexed 0 0110 1101 VST1 (multiple single elements) T3, Post-indexed 0 0110 1111 VST1 (multiple single elements) T3, Offset 0 0111 != 11x1 VST1 (multiple single elements) T1, Post-indexed 0 0111 1101 VST1 (multiple single elements) T1, Post-indexed 0 0111 1111 VST1 (multiple single elements) T1, Offset 0 100x != 11x1 VST2 (multiple 2-element structures) T1, Post-indexed 0 100x 1101 VST2 (multiple 2-element structures) T1, Post-indexed 0 100x 1111 VST2 (multiple 2-element structures) T1, Offset 0 1010 != 11x1 VST1 (multiple single elements) T2, Post-indexed 0 1010 1101 VST1 (multiple single elements) T2, Post-indexed 0 1010 1111 VST1 (multiple single elements) T2, Offset 1 000x != 11x1 VLD4 (multiple 4-element structures) T1, Post-indexed 1 000x 1101 VLD4 (multiple 4-element structures) T1, Post-indexed 1 000x 1111 VLD4 (multiple 4-element structures) T1, Offset 1 0010 != 11x1 VLD1 (multiple single elements) T4, Post-indexed 1 0010 1101 VLD1 (multiple single elements) T4, Post-indexed 1 0010 1111 VLD1 (multiple single elements) T4, Offset 1 0011 != 11x1 VLD2 (multiple 2-element structures) T2, Post-indexed 1 0011 1101 VLD2 (multiple 2-element structures) T2, Post-indexed 1 0011 1111 VLD2 (multiple 2-element structures) T2, Offset 1 010x != 11x1 VLD3 (multiple 3-element structures) T1, Post-indexed 1 010x 1101 VLD3 (multiple 3-element structures) T1, Post-indexed 1 010x 1111 VLD3 (multiple 3-element structures) T1, Offset 1011 UNALLOCATED 1 0110 != 11x1 VLD1 (multiple single elements) T3, Post-indexed 1 0110 1101 VLD1 (multiple single elements) T3, Post-indexed 1 0110 1111 VLD1 (multiple single elements) T3, Offset 1 0111 != 11x1 VLD1 (multiple single elements) T1, Post-indexed 1 0111 1101 VLD1 (multiple single elements) T1, Post-indexed 1 0111 1111 VLD1 (multiple single elements) T1, Offset 11xx UNALLOCATED 1 100x != 11x1 VLD2 (multiple 2-element structures) T1, Post-indexed 1 100x 1101 VLD2 (multiple 2-element structures) T1, Post-indexed 1 100x 1111 VLD2 (multiple 2-element structures) T1, Offset 1 1010 != 11x1 VLD1 (multiple single elements) T2, Post-indexed 1 1010 1101 VLD1 (multiple single elements) T2, Post-indexed 1 1010 1111 VLD1 (multiple single elements) T2, Offset 1 1 1 1 1 0 0 1 1 0 != 11 Decode fields Instruction page Encoding L size N Rm 0 00 00 != 11x1 VST1 (single element from one lane) T1, Post-indexed 0 00 00 1101 VST1 (single element from one lane) T1, Post-indexed 0 00 00 1111 VST1 (single element from one lane) T1, Offset 0 00 01 != 11x1 VST2 (single 2-element structure from one lane) T1, Post-indexed 0 00 01 1101 VST2 (single 2-element structure from one lane) T1, Post-indexed 0 00 01 1111 VST2 (single 2-element structure from one lane) T1, Offset 0 00 10 != 11x1 VST3 (single 3-element structure from one lane) T1, Post-indexed 0 00 10 1101 VST3 (single 3-element structure from one lane) T1, Post-indexed 0 00 10 1111 VST3 (single 3-element structure from one lane) T1, Offset 0 00 11 != 11x1 VST4 (single 4-element structure from one lane) T1, Post-indexed 0 00 11 1101 VST4 (single 4-element structure from one lane) T1, Post-indexed 0 00 11 1111 VST4 (single 4-element structure from one lane) T1, Offset 0 01 00 != 11x1 VST1 (single element from one lane) T2, Post-indexed 0 01 00 1101 VST1 (single element from one lane) T2, Post-indexed 0 01 00 1111 VST1 (single element from one lane) T2, Offset 0 01 01 != 11x1 VST2 (single 2-element structure from one lane) T2, Post-indexed 0 01 01 1101 VST2 (single 2-element structure from one lane) T2, Post-indexed 0 01 01 1111 VST2 (single 2-element structure from one lane) T2, Offset 0 01 10 != 11x1 VST3 (single 3-element structure from one lane) T2, Post-indexed 0 01 10 1101 VST3 (single 3-element structure from one lane) T2, Post-indexed 0 01 10 1111 VST3 (single 3-element structure from one lane) T2, Offset 0 01 11 != 11x1 VST4 (single 4-element structure from one lane) T2, Post-indexed 0 01 11 1101 VST4 (single 4-element structure from one lane) T2, Post-indexed 0 01 11 1111 VST4 (single 4-element structure from one lane) T2, Offset 0 10 00 != 11x1 VST1 (single element from one lane) T3, Post-indexed 0 10 00 1101 VST1 (single element from one lane) T3, Post-indexed 0 10 00 1111 VST1 (single element from one lane) T3, Offset 0 10 01 != 11x1 VST2 (single 2-element structure from one lane) T3, Post-indexed 0 10 01 1101 VST2 (single 2-element structure from one lane) T3, Post-indexed 0 10 01 1111 VST2 (single 2-element structure from one lane) T3, Offset 0 10 10 != 11x1 VST3 (single 3-element structure from one lane) T3, Post-indexed 0 10 10 1101 VST3 (single 3-element structure from one lane) T3, Post-indexed 0 10 10 1111 VST3 (single 3-element structure from one lane) T3, Offset 0 10 11 != 11x1 VST4 (single 4-element structure from one lane) T3, Post-indexed 0 10 11 1101 VST4 (single 4-element structure from one lane) T3, Post-indexed 0 10 11 1111 VST4 (single 4-element structure from one lane) T3, Offset 1 00 00 != 11x1 VLD1 (single element to one lane) T1, Post-indexed 1 00 00 1101 VLD1 (single element to one lane) T1, Post-indexed 1 00 00 1111 VLD1 (single element to one lane) T1, Offset 1 00 01 != 11x1 VLD2 (single 2-element structure to one lane) T1, Post-indexed 1 00 01 1101 VLD2 (single 2-element structure to one lane) T1, Post-indexed 1 00 01 1111 VLD2 (single 2-element structure to one lane) T1, Offset 1 00 10 != 11x1 VLD3 (single 3-element structure to one lane) T1, Post-indexed 1 00 10 1101 VLD3 (single 3-element structure to one lane) T1, Post-indexed 1 00 10 1111 VLD3 (single 3-element structure to one lane) T1, Offset 1 00 11 != 11x1 VLD4 (single 4-element structure to one lane) T1, Post-indexed 1 00 11 1101 VLD4 (single 4-element structure to one lane) T1, Post-indexed 1 00 11 1111 VLD4 (single 4-element structure to one lane) T1, Offset 1 01 00 != 11x1 VLD1 (single element to one lane) T2, Post-indexed 1 01 00 1101 VLD1 (single element to one lane) T2, Post-indexed 1 01 00 1111 VLD1 (single element to one lane) T2, Offset 1 01 01 != 11x1 VLD2 (single 2-element structure to one lane) T2, Post-indexed 1 01 01 1101 VLD2 (single 2-element structure to one lane) T2, Post-indexed 1 01 01 1111 VLD2 (single 2-element structure to one lane) T2, Offset 1 01 10 != 11x1 VLD3 (single 3-element structure to one lane) T2, Post-indexed 1 01 10 1101 VLD3 (single 3-element structure to one lane) T2, Post-indexed 1 01 10 1111 VLD3 (single 3-element structure to one lane) T2, Offset 1 01 11 != 11x1 VLD4 (single 4-element structure to one lane) T2, Post-indexed 1 01 11 1101 VLD4 (single 4-element structure to one lane) T2, Post-indexed 1 01 11 1111 VLD4 (single 4-element structure to one lane) T2, Offset 1 10 00 != 11x1 VLD1 (single element to one lane) T3, Post-indexed 1 10 00 1101 VLD1 (single element to one lane) T3, Post-indexed 1 10 00 1111 VLD1 (single element to one lane) T3, Offset 1 10 01 != 11x1 VLD2 (single 2-element structure to one lane) T3, Post-indexed 1 10 01 1101 VLD2 (single 2-element structure to one lane) T3, Post-indexed 1 10 01 1111 VLD2 (single 2-element structure to one lane) T3, Offset 1 10 10 != 11x1 VLD3 (single 3-element structure to one lane) T3, Post-indexed 1 10 10 1101 VLD3 (single 3-element structure to one lane) T3, Post-indexed 1 10 10 1111 VLD3 (single 3-element structure to one lane) T3, Offset 1 10 11 != 11x1 VLD4 (single 4-element structure to one lane) T3, Post-indexed 1 10 11 1101 VLD4 (single 4-element structure to one lane) T3, Post-indexed 1 10 11 1111 VLD4 (single 4-element structure to one lane) T3, Offset Data-processing (register) 1 1 1 1 1 0 1 0 1 1 1 1 1 1 0 Decode fields Instruction page Encoding op1 op2 000 00 QADD T1 000 01 QDADD T1 000 10 QSUB T1 000 11 QDSUB T1 001 00 REV T2 001 01 REV16 T2 001 10 RBIT T1 001 11 REVSH T2 010 00 SEL T1 010 01 UNALLOCATED 010 1x UNALLOCATED 011 00 CLZ T1 011 01 UNALLOCATED 011 1x UNALLOCATED 100 00 CRC32 T1, CRC32B 100 01 CRC32 T1, CRC32H 100 10 CRC32 T1, CRC32W 100 11 UNPREDICTABLE 101 00 CRC32C T1, CRC32CB 101 01 CRC32C T1, CRC32CH 101 10 CRC32C T1, CRC32CW 101 11 UNPREDICTABLE 11x UNALLOCATED 1 1 1 1 1 0 1 0 1 1 1 1 1 0 Decode fields Instruction page Encoding op1 U H S 000 0 0 0 SADD8 T1 000 0 0 1 QADD8 T1 000 0 1 0 SHADD8 T1 000 0 1 1 UNALLOCATED 000 1 0 0 UADD8 T1 000 1 0 1 UQADD8 T1 000 1 1 0 UHADD8 T1 000 1 1 1 UNALLOCATED 001 0 0 0 SADD16 T1 001 0 0 1 QADD16 T1 001 0 1 0 SHADD16 T1 001 0 1 1 UNALLOCATED 001 1 0 0 UADD16 T1 001 1 0 1 UQADD16 T1 001 1 1 0 UHADD16 T1 001 1 1 1 UNALLOCATED 010 0 0 0 SASX T1 010 0 0 1 QASX T1 010 0 1 0 SHASX T1 010 0 1 1 UNALLOCATED 010 1 0 0 UASX T1 010 1 0 1 UQASX T1 010 1 1 0 UHASX T1 010 1 1 1 UNALLOCATED 100 0 0 0 SSUB8 T1 100 0 0 1 QSUB8 T1 100 0 1 0 SHSUB8 T1 100 0 1 1 UNALLOCATED 100 1 0 0 USUB8 T1 100 1 0 1 UQSUB8 T1 100 1 1 0 UHSUB8 T1 100 1 1 1 UNALLOCATED 101 0 0 0 SSUB16 T1 101 0 0 1 QSUB16 T1 101 0 1 0 SHSUB16 T1 101 0 1 1 UNALLOCATED 101 1 0 0 USUB16 T1 101 1 0 1 UQSUB16 T1 101 1 1 0 UHSUB16 T1 101 1 1 1 UNALLOCATED 110 0 0 0 SSAX T1 110 0 0 1 QSAX T1 110 0 1 0 SHSAX T1 110 0 1 1 UNALLOCATED 110 1 0 0 USAX T1 110 1 0 1 UQSAX T1 110 1 1 0 UHSAX T1 110 1 1 1 UNALLOCATED 111 UNALLOCATED 1 1 1 1 1 0 1 0 0 1 1 1 1 1 (0) Decode fields Instruction page Encoding op1 U Rn 00 0 != 1111 SXTAH T1 00 0 1111 SXTH T2 00 1 != 1111 UXTAH T1 00 1 1111 UXTH T2 01 0 != 1111 SXTAB16 T1 01 0 1111 SXTB16 T1 01 1 != 1111 UXTAB16 T1 01 1 1111 UXTB16 T1 10 0 != 1111 SXTAB T1 10 0 1111 SXTB T2 10 1 != 1111 UXTAB T1 10 1 1111 UXTB T2 11 UNALLOCATED 1 1 1 1 1 0 1 0 0 1 1 1 1 0 0 0 0 Instruction page Encoding MOV, MOVS (register-shifted register) T2, Flag setting Multiply, multiply accumulate, and absolute difference 1 1 1 1 1 0 1 1 0 0 0 Decode fields Instruction page Encoding op1 Ra op2 000 != 1111 00 MLA, MLAS T1 000 01 MLS T1 000 1x UNALLOCATED 000 1111 00 MUL, MULS T2 001 != 1111 00 SMLABB, SMLABT, SMLATB, SMLATT T1, SMLABB 001 != 1111 01 SMLABB, SMLABT, SMLATB, SMLATT T1, SMLABT 001 != 1111 10 SMLABB, SMLABT, SMLATB, SMLATT T1, SMLATB 001 != 1111 11 SMLABB, SMLABT, SMLATB, SMLATT T1, SMLATT 001 1111 00 SMULBB, SMULBT, SMULTB, SMULTT T1, SMULBB 001 1111 01 SMULBB, SMULBT, SMULTB, SMULTT T1, SMULBT 001 1111 10 SMULBB, SMULBT, SMULTB, SMULTT T1, SMULTB 001 1111 11 SMULBB, SMULBT, SMULTB, SMULTT T1, SMULTT 010 != 1111 00 SMLAD, SMLADX T1, SMLAD 010 != 1111 01 SMLAD, SMLADX T1, SMLADX 010 1x UNALLOCATED 010 1111 00 SMUAD, SMUADX T1, SMUAD 010 1111 01 SMUAD, SMUADX T1, SMUADX 011 != 1111 00 SMLAWB, SMLAWT T1, SMLAWB 011 != 1111 01 SMLAWB, SMLAWT T1, SMLAWT 011 1x UNALLOCATED 011 1111 00 SMULWB, SMULWT T1, SMULWB 011 1111 01 SMULWB, SMULWT T1, SMULWT 100 != 1111 00 SMLSD, SMLSDX T1, SMLSD 100 != 1111 01 SMLSD, SMLSDX T1, SMLSDX 100 1x UNALLOCATED 100 1111 00 SMUSD, SMUSDX T1, SMUSD 100 1111 01 SMUSD, SMUSDX T1, SMUSDX 101 != 1111 00 SMMLA, SMMLAR T1, SMMLA 101 != 1111 01 SMMLA, SMMLAR T1, SMMLAR 101 1x UNALLOCATED 101 1111 00 SMMUL, SMMULR T1, SMMUL 101 1111 01 SMMUL, SMMULR T1, SMMULR 110 00 SMMLS, SMMLSR T1, SMMLS 110 01 SMMLS, SMMLSR T1, SMMLSR 110 1x UNALLOCATED 111 != 1111 00 USADA8 T1 111 01 UNALLOCATED 111 1x UNALLOCATED 111 1111 00 USAD8 T1 Advanced SIMD three registers of the same length 1 1 1 1 1 1 1 0 Decode fields Instruction page Encoding U size opc Q o1 0 0x 1100 1 VFMA T1, 128-bit SIMD vector 0 0x 1101 0 VADD (floating-point) T1, 128-bit SIMD vector 0 0x 1101 1 VMLA (floating-point) T1, 128-bit SIMD vector 0 0x 1110 0 VCEQ (register) T2, 128-bit SIMD vector 0 0x 1111 0 VMAX (floating-point) T1, 128-bit SIMD vector 0 0x 1111 1 VRECPS T1, 128-bit SIMD vector 0000 0 VHADD T1, 128-bit SIMD vector 0 00 0001 1 VAND (register) T1, 128-bit SIMD vector 0000 1 VQADD T1, 128-bit SIMD vector 0001 0 VRHADD T1, 128-bit SIMD vector 0 00 1100 0 SHA1C T1 0010 0 VHSUB T1, 128-bit SIMD vector 0 01 0001 1 VBIC (register) T1, 128-bit SIMD vector 0010 1 VQSUB T1, 128-bit SIMD vector 0011 0 VCGT (register) T1, 128-bit SIMD vector 0011 1 VCGE (register) T1, 128-bit SIMD vector 0 01 1100 0 SHA1P T1 0 1x 1100 1 VFMS T1, 128-bit SIMD vector 0 1x 1101 0 VSUB (floating-point) T1, 128-bit SIMD vector 0 1x 1101 1 VMLS (floating-point) T1, 128-bit SIMD vector 0 1x 1110 0 UNALLOCATED 0 1x 1111 0 VMIN (floating-point) T1, 128-bit SIMD vector 0 1x 1111 1 VRSQRTS T1, 128-bit SIMD vector 0100 0 VSHL (register) T1, 128-bit SIMD vector 0 1000 0 VADD (integer) T1, 128-bit SIMD vector 0 10 0001 1 VORR (register) T1, 128-bit SIMD vector 0 1000 1 VTST T1, 128-bit SIMD vector 0100 1 VQSHL (register) T1, 128-bit SIMD vector 0 1001 0 VMLA (integer) T1, 128-bit SIMD vector 0101 0 VRSHL T1, 128-bit SIMD vector 0101 1 VQRSHL T1, 128-bit SIMD vector 0 1011 0 VQDMULH T1, 128-bit SIMD vector 0 10 1100 0 SHA1M T1 0 1011 1 VPADD (integer) T1 0110 0 VMAX (integer) T1, 128-bit SIMD vector 0 11 0001 1 VORN (register) T1, 128-bit SIMD vector 0110 1 VMIN (integer) T1, 128-bit SIMD vector 0111 0 VABD (integer) T1, 128-bit SIMD vector 0111 1 VABA T1, 128-bit SIMD vector 0 11 1100 0 SHA1SU0 T1 1 0x 1101 0 VPADD (floating-point) T1 1 0x 1101 1 VMUL (floating-point) T1, 128-bit SIMD vector 1 0x 1110 0 VCGE (register) T2, 128-bit SIMD vector 1 0x 1110 1 VACGE T1, 128-bit SIMD vector 1 0x 1111 0 0 VPMAX (floating-point) T1 1 0x 1111 1 VMAXNM T1, 128-bit SIMD vector 1 00 0001 1 VEOR T1, 128-bit SIMD vector 1001 1 VMUL (integer and polynomial) T1, 128-bit SIMD vector 1 00 1100 0 SHA256H T1 1010 0 0 VPMAX (integer) T1 1 01 0001 1 VBSL T1, 128-bit SIMD vector 1010 0 1 VPMIN (integer) T1 1010 1 UNALLOCATED 1 01 1100 0 SHA256H2 T1 1 1x 1101 0 VABD (floating-point) T1, 128-bit SIMD vector 1 1x 1110 0 VCGT (register) T2, 128-bit SIMD vector 1 1x 1110 1 VACGT T1, 128-bit SIMD vector 1 1x 1111 0 0 VPMIN (floating-point) T1 1 1x 1111 1 VMINNM T1, 128-bit SIMD vector 1 1000 0 VSUB (integer) T1, 128-bit SIMD vector 1 10 0001 1 VBIT T1, 128-bit SIMD vector 1 1000 1 VCEQ (register) T1, 128-bit SIMD vector 1 1001 0 VMLS (integer) T1, 128-bit SIMD vector 1 1011 0 VQRDMULH T1, 128-bit SIMD vector 1 10 1100 0 SHA256SU1 T1 1 1011 1 VQRDMLAH T1, 128-bit SIMD vector 1 11 0001 1 VBIF T1, 128-bit SIMD vector 1 1100 1 VQRDMLSH T1, 128-bit SIMD vector 1 1111 1 0 UNALLOCATED Advanced SIMD two registers, or three registers of different lengths 1 1 1 1 1 1 1 1 1 1 1 1 1 0 Decode fields Instruction page Encoding opc 000 VDUP (scalar) T1, 001 UNALLOCATED 01x UNALLOCATED 1xx UNALLOCATED 1 1 1 1 1 1 1 1 1 1 1 1 0 0 Instruction page Encoding VTBL, VTBX T1, VTBX 1 1 1 1 1 1 1 1 != 11 0 0 Decode fields Instruction page Encoding U opc 0000 VADDL T1 0001 VADDW T1 0010 VSUBL T1 0 0100 VADDHN T1 0011 VSUBW T1 0 0110 VSUBHN T1 0 1001 VQDMLAL T1 0101 VABAL T1 0 1011 VQDMLSL T1 0 1101 VQDMULL T1 0111 VABDL (integer) T1 1000 VMLAL (integer) T1 1010 VMLSL (integer) T1 1 0100 VRADDHN T1 1 0110 VRSUBHN T1 11x0 VMULL (integer and polynomial) T1 1 1001 UNALLOCATED 1 1011 UNALLOCATED 1 1101 UNALLOCATED 1111 UNALLOCATED 1 1 1 1 1 1 1 1 != 11 1 0 Decode fields Instruction page Encoding Q opc 000x VMLA (by scalar) T1, 128-bit SIMD vector 0 0011 VQDMLAL T2 0010 VMLAL (by scalar) T1 0 0111 VQDMLSL T2 010x VMLS (by scalar) T1, 128-bit SIMD vector 0 1011 VQDMULL T2 0110 VMLSL (by scalar) T1 100x VMUL (by scalar) T1, 128-bit SIMD vector 1 0011 UNALLOCATED 1010 VMULL (by scalar) T1 1 0111 UNALLOCATED 1100 VQDMULH T2, 128-bit SIMD vector 1101 VQRDMULH T2, 128-bit SIMD vector 1 1011 UNALLOCATED 1110 VQRDMLAH T2, 128-bit SIMD vector 1111 VQRDMLSH T2, 128-bit SIMD vector 1 1 1 1 1 1 1 1 1 1 1 0 0 Decode fields Instruction page Encoding size opc1 opc2 Q 00 0000 VREV64 T1, 128-bit SIMD vector 00 0001 VREV32 T1, 128-bit SIMD vector 00 0010 VREV16 T1, 128-bit SIMD vector 00 0011 UNALLOCATED 00 010x VPADDL T1, 128-bit SIMD vector 00 0110 0 AESE T1 00 0110 1 AESD T1 00 0111 0 AESMC T1 00 0111 1 AESIMC T1 00 1000 VCLS T1, 128-bit SIMD vector 00 10 0000 VSWP T1, 128-bit SIMD vector 00 1001 VCLZ T1, 128-bit SIMD vector 00 1010 VCNT T1, 128-bit SIMD vector 00 1011 VMVN (register) T1, 128-bit SIMD vector 00 10 1100 1 UNALLOCATED 00 110x VPADAL T1, 128-bit SIMD vector 00 1110 VQABS T1, 128-bit SIMD vector 00 1111 VQNEG T1, 128-bit SIMD vector 01 x000 VCGT (immediate #0) T1, 128-bit SIMD vector 01 x001 VCGE (immediate #0) T1, 128-bit SIMD vector 01 x010 VCEQ (immediate #0) T1, 128-bit SIMD vector 01 x011 VCLE (immediate #0) T1, 128-bit SIMD vector 01 x100 VCLT (immediate #0) T1, 128-bit SIMD vector 01 x110 VABS T1, 128-bit SIMD vector 01 x111 VNEG T1, 128-bit SIMD vector 01 0101 1 SHA1H T1 01 10 1100 1 VCVT (from single-precision to BFloat16, Advanced SIMD) T1 10 0001 VTRN T1, 128-bit SIMD vector 10 0010 VUZP T1, 128-bit SIMD vector 10 0011 VZIP T1, 128-bit SIMD vector 10 0100 0 VMOVN T1 10 0100 1 VQMOVN, VQMOVUN T1, Unsigned result 10 0101 VQMOVN, VQMOVUN T1, Signed result 10 0110 0 VSHLL T2 10 0111 0 SHA1SU1 T1 10 0111 1 SHA256SU0 T1 10 1000 VRINTN (Advanced SIMD) T1, 128-bit SIMD vector 10 1001 VRINTX (Advanced SIMD) T1, 128-bit SIMD vector 10 1010 VRINTA (Advanced SIMD) T1, 128-bit SIMD vector 10 1011 VRINTZ (Advanced SIMD) T1, 128-bit SIMD vector 10 10 1100 1 UNALLOCATED 10 1100 0 VCVT (between half-precision and single-precision, Advanced SIMD) T1, Single-precision to half-precision 10 1101 VRINTM (Advanced SIMD) T1, 128-bit SIMD vector 10 1110 0 VCVT (between half-precision and single-precision, Advanced SIMD) T1, Half-precision to single-precision 10 1110 1 UNALLOCATED 10 1111 VRINTP (Advanced SIMD) T1, 128-bit SIMD vector 11 000x VCVTA (Advanced SIMD) T1, 128-bit SIMD vector 11 001x VCVTN (Advanced SIMD) T1, 128-bit SIMD vector 11 010x VCVTP (Advanced SIMD) T1, 128-bit SIMD vector 11 011x VCVTM (Advanced SIMD) T1, 128-bit SIMD vector 11 10x0 VRECPE T1, 128-bit SIMD vector 11 10x1 VRSQRTE T1, 128-bit SIMD vector 11 10 1100 1 UNALLOCATED 11 11xx VCVT (between floating-point and integer, Advanced SIMD) T1, 128-bit SIMD vector 1 1 1 0 1 1 1 1 1 1 1 0 Instruction page Encoding VEXT (byte elements) T1, 128-bit SIMD vector Advanced SIMD shifts and immediate generation 1 1 1 1 1 1 1 1 0 0 0 0 1 Decode fields Instruction page Encoding cmode op 0xx0 0 VMOV (immediate) T1, 128-bit SIMD vector 0xx0 1 VMVN (immediate) T1, 128-bit SIMD vector 0xx1 0 VORR (immediate) T1, 128-bit SIMD vector 0xx1 1 VBIC (immediate) T1, 128-bit SIMD vector 10x0 0 VMOV (immediate) T3, 128-bit SIMD vector 10x0 1 VMVN (immediate) T2, 128-bit SIMD vector 10x1 0 VORR (immediate) T2, 128-bit SIMD vector 10x1 1 VBIC (immediate) T2, 128-bit SIMD vector 11xx 0 VMOV (immediate) T4, 128-bit SIMD vector 110x 1 VMVN (immediate) T3, 128-bit SIMD vector 1110 1 VMOV (immediate) T5, 128-bit SIMD vector 1111 1 UNALLOCATED 1 1 1 1 1 1 1 1 1 Decode fields Instruction page Encoding U imm3H:L imm3L opc Q != 0000 0000 VSHR T1, 128-bit SIMD vector != 0000 0001 VSRA T1, 128-bit SIMD vector != 0000 000 1010 0 VMOVL T1 != 0000 0010 VRSHR T1, 128-bit SIMD vector != 0000 0011 VRSRA T1, 128-bit SIMD vector != 0000 0111 VQSHL, VQSHLU (immediate) T1, 128-bit SIMD vector, signed result != 0000 1001 0 VQSHRN, VQSHRUN T1, Signed result != 0000 1001 1 VQRSHRN, VQRSHRUN T1, Signed result != 0000 1010 0 VSHLL T1 != 0000 11xx VCVT (between floating-point and fixed-point, Advanced SIMD) T1, 128-bit SIMD vector 0 != 0000 0101 VSHL (immediate) T1, 128-bit SIMD vector 0 != 0000 1000 0 VSHRN T1 0 != 0000 1000 1 VRSHRN T1 1 != 0000 0100 VSRI T1, 128-bit SIMD vector 1 != 0000 0101 VSLI T1, 128-bit SIMD vector 1 != 0000 0110 VQSHL, VQSHLU (immediate) T1, 128-bit SIMD vector, unsigned result 1 != 0000 1000 0 VQSHRN, VQSHRUN T1, Unsigned result 1 != 0000 1000 1 VQRSHRN, VQRSHRUN T1, Unsigned result Long multiply, long multiply accumulate, and divide 1 1 1 1 1 0 1 1 1 Decode fields Instruction page Encoding op1 op2 000 != 0000 UNALLOCATED 000 0000 SMULL, SMULLS T1 001 != 1111 UNALLOCATED 001 1111 SDIV T1 010 != 0000 UNALLOCATED 010 0000 UMULL, UMULLS T1 011 != 1111 UNALLOCATED 011 1111 UDIV T1 100 0000 SMLAL, SMLALS T1 100 0001 UNALLOCATED 100 001x UNALLOCATED 100 01xx UNALLOCATED 100 1000 SMLALBB, SMLALBT, SMLALTB, SMLALTT T1, SMLALBB 100 1001 SMLALBB, SMLALBT, SMLALTB, SMLALTT T1, SMLALBT 100 1010 SMLALBB, SMLALBT, SMLALTB, SMLALTT T1, SMLALTB 100 1011 SMLALBB, SMLALBT, SMLALTB, SMLALTT T1, SMLALTT 100 1100 SMLALD, SMLALDX T1, SMLALD 100 1101 SMLALD, SMLALDX T1, SMLALDX 100 111x UNALLOCATED 101 0xxx UNALLOCATED 101 10xx UNALLOCATED 101 1100 SMLSLD, SMLSLDX T1, SMLSLD 101 1101 SMLSLD, SMLSLDX T1, SMLSLDX 101 111x UNALLOCATED 110 0000 UMLAL, UMLALS T1 110 0001 UNALLOCATED 110 001x UNALLOCATED 110 010x UNALLOCATED 110 0110 UMAAL T1 110 0111 UNALLOCATED 110 1xxx UNALLOCATED 111 UNALLOCATED