STR (immediate)
Store Register (immediate)
Store Register (immediate) calculates an address from a base register value and an immediate offset, and stores a word from a register to memory. It can use offset, post-indexed, or pre-indexed addressing. For information about memory accesses see Memory accesses.
For more information about the constrained unpredictable behavior of this instruction, see Architectural Constraints on UNPREDICTABLE behaviors.
If CPSR.DIT is 1, the timing of this instruction is insensitive to the value of the data being loaded or stored.
This instruction is used by the alias
PUSH (single register)
P == '1' && U == '0' && W == '1' && Rn == '1101' && imm12 == '000000000100'
Rn == '1101' && P == '1' && U == '0' && W == '1' && imm8 == '00000100'
See
below for details of when the alias is preferred.
It has encodings from the following instruction sets:
A32 (
A1
)
and
T32 (
T1
,
T2
,
T3
and
T4
)
.
!= 1111
0
1
0
0
0
1
0
STR{<c>}{<q>} <Rt>, [<Rn> {, #{+/-}<imm>}]
0
0
STR{<c>}{<q>} <Rt>, [<Rn>], #{+/-}<imm>
1
1
STR{<c>}{<q>} <Rt>, [<Rn>, #{+/-}<imm>]!
if P == '0' && W == '1' then SEE "STRT";
t = UInt(Rt); n = UInt(Rn); imm32 = ZeroExtend(imm12, 32);
index = (P == '1'); add = (U == '1'); wback = (P == '0') || (W == '1');
if wback && (n == 15 || n == t) then UNPREDICTABLE;
wback && n == t
wback && n == 15
The instruction uses the addressing mode described in the equivalent immediate offset instruction.
0
1
1
0
0
STR{<c>}{<q>} <Rt>, [<Rn> {, #{+}<imm>}]
t = UInt(Rt); n = UInt(Rn); imm32 = ZeroExtend(imm5:'00', 32);
index = TRUE; add = TRUE; wback = FALSE;
1
0
0
1
0
STR{<c>}{<q>} <Rt>, [SP{, #{+}<imm>}]
t = UInt(Rt); n = 13; imm32 = ZeroExtend(imm8:'00', 32);
index = TRUE; add = TRUE; wback = FALSE;
1
1
1
1
1
0
0
0
1
1
0
0
!= 1111
STR{<c>}.W <Rt>, [<Rn> {, #{+}<imm>}]
STR{<c>}{<q>} <Rt>, [<Rn> {, #{+}<imm>}]
if Rn == '1111' then UNDEFINED;
t = UInt(Rt); n = UInt(Rn); imm32 = ZeroExtend(imm12, 32);
index = TRUE; add = TRUE; wback = FALSE;
if t == 15 then UNPREDICTABLE;
t == 15
The store instruction performs the store using the specified addressing mode but the value corresponding to R15 is unknown.
1
1
1
1
1
0
0
0
0
1
0
0
!= 1111
1
1
0
0
STR{<c>}{<q>} <Rt>, [<Rn> {, #-<imm>}]
0
1
STR{<c>}{<q>} <Rt>, [<Rn>], #{+/-}<imm>
1
1
STR{<c>}{<q>} <Rt>, [<Rn>, #{+/-}<imm>]!
if P == '1' && U == '1' && W == '0' then SEE "STRT";
if Rn == '1111' || (P == '0' && W == '0') then UNDEFINED;
t = UInt(Rt); n = UInt(Rn); imm32 = ZeroExtend(imm8, 32);
index = (P == '1'); add = (U == '1'); wback = (W == '1');
if t == 15 || (wback && n == t) then UNPREDICTABLE;
wback && n == t
t == 15
The store instruction performs the store using the specified addressing mode but the value corresponding to R15 is unknown.
<c>
See Standard assembler syntax fields.
<q>
See Standard assembler syntax fields.
<Rt>
For encoding A1: is the general-purpose register to be transferred, encoded in the "Rt" field. The PC can be used, but this is deprecated.
<Rt>
For encoding T1, T2, T3 and T4: is the general-purpose register to be transferred, encoded in the "Rt" field.
<Rn>
For encoding A1: is the general-purpose base register, encoded in the "Rn" field. The PC can be used in the offset variant, but this is deprecated.
<Rn>
For encoding T1, T3 and T4: is the general-purpose base register, encoded in the "Rn" field.
+/-
Specifies the offset is added to or subtracted from the base register, defaulting to + if omitted and
+
Specifies the offset is added to the base register.
<imm>
For encoding A1: is the 12-bit unsigned immediate byte offset, in the range 0 to 4095, defaulting to 0 if omitted, and encoded in the "imm12" field.
<imm>
For encoding T1: is the optional positive unsigned immediate byte offset, a multiple of 4, in the range 0 to 124, defaulting to 0 and encoded in the "imm5" field as <imm>/4.
<imm>
For encoding T2: is the optional positive unsigned immediate byte offset, a multiple of 4, in the range 0 to 1020, defaulting to 0 and encoded in the "imm8" field as <imm>/4.
<imm>
For encoding T3: is an optional 12-bit unsigned immediate byte offset, in the range 0 to 4095, defaulting to 0 and encoded in the "imm12" field.
<imm>
For encoding T4: is an 8-bit unsigned immediate byte offset, in the range 0 to 255, defaulting to 0 if omitted, and encoded in the "imm8" field.
Alias Conditions
if CurrentInstrSet() == InstrSet_A32 then
if ConditionPassed() then
EncodingSpecificOperations();
offset_addr = if add then (R[n] + imm32) else (R[n] - imm32);
address = if index then offset_addr else R[n];
MemU[address,4] = if t == 15 then PCStoreValue() else R[t];
if wback then R[n] = offset_addr;
else
if ConditionPassed() then
EncodingSpecificOperations();
offset_addr = if add then (R[n] + imm32) else (R[n] - imm32);
address = if index then offset_addr else R[n];
MemU[address,4] = R[t];
if wback then R[n] = offset_addr;