SHA256H SHA256 hash update part 1 SHA256 hash update part 1. For more information about the constrained unpredictable behavior of this instruction, see Architectural Constraints on UNPREDICTABLE behaviors. If CPSR.DIT is 1: The execution time of this instruction is independent of:The values of the data supplied in any of its registers.The values of the NZCV flags. The response of this instruction to asynchronous exceptions does not vary based on:The values of the data supplied in any of its registers.The values of the NZCV flags. It has encodings from the following instruction sets: A32 ( A1 ) and T32 ( T1 ) . 1 1 1 1 0 0 1 1 0 0 0 1 1 0 0 0 SHA256H.32 <Qd>, <Qn>, <Qm> if !HaveSHA256Ext() then UNDEFINED; if Q != '1' then UNDEFINED; if Vd<0> == '1' || Vn<0> == '1' || Vm<0> == '1' then UNDEFINED; d = UInt(D:Vd); n = UInt(N:Vn); m = UInt(M:Vm); 1 1 1 1 1 1 1 1 0 0 0 1 1 0 0 0 SHA256H.32 <Qd>, <Qn>, <Qm> if InITBlock() then UNPREDICTABLE; if !HaveSHA256Ext() then UNDEFINED; if Q != '1' then UNDEFINED; if Vd<0> == '1' || Vn<0> == '1' || Vm<0> == '1' then UNDEFINED; d = UInt(D:Vd); n = UInt(N:Vn); m = UInt(M:Vm); <Qd> Is the 128-bit name of the SIMD&FP destination register, encoded in the "D:Vd" field as <Qd>*2. <Qn> Is the 128-bit name of the first SIMD&FP source register, encoded in the "N:Vn" field as <Qn>*2. <Qm> Is the 128-bit name of the second SIMD&FP source register, encoded in the "M:Vm" field as <Qm>*2. if ConditionPassed() then EncodingSpecificOperations(); CheckCryptoEnabled32(); X = Q[d>>1]; Y = Q[n>>1]; W = Q[m>>1]; part1 = TRUE; Q[d>>1] = SHA256hash(X, Y, W, part1);