ESB Error Synchronization Barrier Error Synchronization Barrier is an error synchronization event that might also update DISR and VDISR. This instruction can be used at all Exception levels and in Debug state. In Debug state, this instruction behaves as if SError interrupts are masked at all Exception levels. See Error Synchronization Barrier in the ARM(R) Reliability, Availability, and Serviceability (RAS) Specification, Armv8, for Armv8-A architecture profile. If the RAS Extension is not implemented, this instruction executes as a NOP. It has encodings from the following instruction sets: A32 ( A1 ) and T32 ( T1 ) . != 1111 0 0 1 1 0 0 1 0 0 0 0 0 (1) (1) (1) (1) (0) (0) (0) (0) 0 0 0 1 0 0 0 0 ESB{<c>}{<q>} if !HaveRASExt() then EndOfInstruction(); // Instruction executes as NOP if cond != '1110' then UNPREDICTABLE; // ESB must be encoded with AL condition cond != '1110' 1 1 1 1 0 0 1 1 1 0 1 0 (1) (1) (1) (1) 1 0 (0) 0 (0) 0 0 0 0 0 0 1 0 0 0 0 ESB{<c>}{<q>} if !HaveRASExt() then EndOfInstruction(); // Instruction executes as NOP if InITBlock() then UNPREDICTABLE; InITBlock() <c> See Standard assembler syntax fields. <q> See Standard assembler syntax fields. if ConditionPassed() then EncodingSpecificOperations(); SynchronizeErrors(); AArch32.ESBOperation(); if PSTATE.EL IN {EL0, EL1} && EL2Enabled() then AArch32.vESBOperation(); TakeUnmaskedSErrorInterrupts();