VSUDOT (by element)
Dot Product index form with signed and unsigned integers (by element)
Dot Product index form with signed and unsigned integers. This instruction performs the dot product of the four signed 8-bit integer values in each 32-bit element of the first source register with the four unsigned 8-bit integer values in an indexed 32-bit element of the second source register, accumulating the result into the corresponding 32-bit element of the destination register.
From Armv8.2, this is an optional instruction. ID_ISAR6.I8MM indicates whether this instruction is supported in the T32 and A32 instruction sets.
It has encodings from the following instruction sets:
A32 (
A1
)
and
T32 (
T1
)
.
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0
VSUDOT{<q>}.U8 <Dd>, <Dn>, <Dm>[<index>]
1
VSUDOT{<q>}.U8 <Qd>, <Qn>, <Dm>[<index>]
if !HaveAArch32Int8MatMulExt() then UNDEFINED;
if Q == '1' && (Vd<0> == '1' || Vn<0> == '1') then UNDEFINED;
boolean op1_unsigned = (U == '0');
boolean op2_unsigned = (U == '1');
integer d = UInt(D:Vd);
integer n = UInt(N:Vn);
integer m = UInt(Vm);
integer i = UInt(M);
integer regs = if Q == '1' then 2 else 1;
1
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VSUDOT{<q>}.U8 <Dd>, <Dn>, <Dm>[<index>]
1
VSUDOT{<q>}.U8 <Qd>, <Qn>, <Dm>[<index>]
if InITBlock() then UNPREDICTABLE;
if !HaveAArch32Int8MatMulExt() then UNDEFINED;
if Q == '1' && (Vd<0> == '1' || Vn<0> == '1') then UNDEFINED;
boolean op1_unsigned = (U == '0');
boolean op2_unsigned = (U == '1');
integer d = UInt(D:Vd);
integer n = UInt(N:Vn);
integer m = UInt(Vm);
integer i = UInt(M);
integer regs = if Q == '1' then 2 else 1;
<q>
See Standard assembler syntax fields.
<Qd>
Is the 128-bit name of the SIMD&FP destination register, encoded in the "D:Vd" field as <Qd>*2.
<Qn>
Is the 128-bit name of the first SIMD&FP source register, encoded in the "N:Vn" field as <Qn>*2.
<Dd>
Is the 64-bit name of the SIMD&FP destination register, encoded in the "D:Vd" field.
<Dn>
Is the 64-bit name of the first SIMD&FP source register, encoded in the "N:Vn" field.
<Dm>
Is the 64-bit name of the second SIMD&FP source register, encoded in the "Vm" field.
<index>
Is the element index in the range 0 to 1, encoded in the "M" field.
CheckAdvSIMDEnabled();
bits(64) operand1;
bits(64) operand2;
bits(64) result;
operand2 = Din[m];
for r = 0 to regs-1
operand1 = Din[n+r];
result = Din[d+r];
for e = 0 to 1
bits(32) res = Elem[result, e, 32];
for b = 0 to 3
element1 = Int(Elem[operand1, 4 * e + b, 8], op1_unsigned);
element2 = Int(Elem[operand2, 4 * i + b, 8], op2_unsigned);
res = res + element1 * element2;
Elem[result, e, 32] = res;
D[d+r] = result;