VMOV (between two general-purpose registers and a doubleword floating-point register) Copy two general-purpose registers to or from a SIMD&FP register Copy two general-purpose registers to or from a SIMD&FP register copies two words from two general-purpose registers into a doubleword register in the Advanced SIMD and floating-point register file, or from a doubleword register in the Advanced SIMD and floating-point register file to two general-purpose registers. Depending on settings in the CPACR, NSACR, HCPTR, and FPEXC registers, and the Security state and PE mode in which the instruction is executed, an attempt to execute the instruction might be undefined, or trapped to Hyp mode. For more information see Enabling Advanced SIMD and floating-point support. For more information about the constrained unpredictable behavior of this instruction, see Architectural Constraints on UNPREDICTABLE behaviors, and particularly VMOV (between two general-purpose registers and a doubleword floating-point register). If CPSR.DIT is 1 and this instruction passes its condition execution check: The execution time of this instruction is independent of:The values of the data supplied in any of its registers.The values of the NZCV flags. The response of this instruction to asynchronous exceptions does not vary based on:The values of the data supplied in any of its registers.The values of the NZCV flags. It has encodings from the following instruction sets: A32 ( A1 ) and T32 ( T1 ) . != 1111 1 1 0 0 0 1 0 1 0 1 1 0 0 1 0 VMOV{<c>}{<q>} <Dm>, <Rt>, <Rt2> 1 VMOV{<c>}{<q>} <Rt>, <Rt2>, <Dm> to_arm_registers = (op == '1'); t = UInt(Rt); t2 = UInt(Rt2); m = UInt(M:Vm); if t == 15 || t2 == 15 then UNPREDICTABLE; // Armv8-A removes UNPREDICTABLE for R13 if to_arm_registers && t == t2 then UNPREDICTABLE; to_arm_registers && t == t2 1 1 1 0 1 1 0 0 0 1 0 1 0 1 1 0 0 1 0 VMOV{<c>}{<q>} <Dm>, <Rt>, <Rt2> 1 VMOV{<c>}{<q>} <Rt>, <Rt2>, <Dm> to_arm_registers = (op == '1'); t = UInt(Rt); t2 = UInt(Rt2); m = UInt(M:Vm); if t == 15 || t2 == 15 then UNPREDICTABLE; // Armv8-A removes UNPREDICTABLE for R13 if to_arm_registers && t == t2 then UNPREDICTABLE; to_arm_registers && t == t2 <Dm> Is the 64-bit name of the SIMD&FP register to be transferred, encoded in the "M:Vm" field. <Rt2> Is the second general-purpose register that <Dm>[63:32] will be transferred to or from, encoded in the "Rt2" field. <Rt> Is the first general-purpose register that <Dm>[31:0] will be transferred to or from, encoded in the "Rt" field. <c> See Standard assembler syntax fields. <q> See Standard assembler syntax fields. if ConditionPassed() then EncodingSpecificOperations(); CheckVFPEnabled(TRUE); if to_arm_registers then R[t] = D[m]<31:0>; R[t2] = D[m]<63:32>; else D[m]<31:0> = R[t]; D[m]<63:32> = R[t2];