VCVTN (floating-point)
Convert floating-point to integer with Round to Nearest
Convert floating-point to integer with Round to Nearest converts a value in a register from floating-point to a 32-bit integer using the Round to Nearest rounding mode, and places the result in a second register.
Depending on settings in the CPACR, NSACR, HCPTR, and FPEXC registers, and the Security state and PE mode in which the instruction is executed, an attempt to execute the instruction might be undefined, or trapped to Hyp mode. For more information see Enabling Advanced SIMD and floating-point support.
It has encodings from the following instruction sets:
A32 (
A1
)
and
T32 (
T1
)
.
1
1
1
1
1
1
1
0
1
1
1
1
1
0
1
1
0
!= 00
1
0
0
1
VCVTN{<q>}.<dt>.F16 <Sd>, <Sm>
1
0
VCVTN{<q>}.<dt>.F32 <Sd>, <Sm>
1
1
VCVTN{<q>}.<dt>.F64 <Sd>, <Dm>
if size == '00' || (size == '01' && !HaveFP16Ext()) then UNDEFINED;
rounding = FPDecodeRM(RM); unsigned = (op == '0');
d = UInt(Vd:D);
integer esize;
integer m;
case size of
when '01' esize = 16; m = UInt(Vm:M);
when '10' esize = 32; m = UInt(Vm:M);
when '11' esize = 64; m = UInt(M:Vm);
1
1
1
1
1
1
1
0
1
1
1
1
1
0
1
1
0
!= 00
1
0
0
1
VCVTN{<q>}.<dt>.F16 <Sd>, <Sm>
1
0
VCVTN{<q>}.<dt>.F32 <Sd>, <Sm>
1
1
VCVTN{<q>}.<dt>.F64 <Sd>, <Dm>
if InITBlock() then UNPREDICTABLE;
if size == '00' || (size == '01' && !HaveFP16Ext()) then UNDEFINED;
rounding = FPDecodeRM(RM); unsigned = (op == '0');
d = UInt(Vd:D);
integer esize;
integer m;
case size of
when '01' esize = 16; m = UInt(Vm:M);
when '10' esize = 32; m = UInt(Vm:M);
when '11' esize = 64; m = UInt(M:Vm);
InITBlock()
The instruction executes as if it passes the Condition code check.
The instruction executes as NOP. This means it behaves as if it fails the Condition code check.
<q>
See Standard assembler syntax fields.
<dt>
Is the data type for the elements of the destination,
<Sd>
Is the 32-bit name of the SIMD&FP destination register, encoded in the "Vd:D" field.
<Sm>
Is the 32-bit name of the SIMD&FP source register, encoded in the "Vm:M" field.
<Dm>
Is the 64-bit name of the SIMD&FP source register, encoded in the "M:Vm" field.
EncodingSpecificOperations(); CheckVFPEnabled(TRUE);
case esize of
when 16
S[d] = FPToFixed(S[m]<15:0>, 0, unsigned, FPSCR[], rounding, 32);
when 32
S[d] = FPToFixed(S[m], 0, unsigned, FPSCR[], rounding, 32);
when 64
S[d] = FPToFixed(D[m], 0, unsigned, FPSCR[], rounding, 32);