LDAEXB Load-Acquire Exclusive Byte Load-Acquire Exclusive Byte loads a byte from memory, zero-extends it to form a 32-bit word, writes it to a register and: If the address has the Shared Memory attribute, marks the physical address as exclusive access for the executing PE in a global monitor. Causes the executing PE to indicate an active exclusive access in the local monitor. The instruction also has memory ordering semantics as described in Load-Acquire, Store-Release. For more information about support for shared memory see Synchronization and semaphores. For information about memory accesses see Memory accesses. For more information about the constrained unpredictable behavior of this instruction, see Architectural Constraints on UNPREDICTABLE behaviors. If CPSR.DIT is 1, the timing of this instruction is insensitive to the value of the data being loaded or stored. It has encodings from the following instruction sets: A32 ( A1 ) and T32 ( T1 ) . != 1111 0 0 0 1 1 1 0 1 (1) (1) 1 0 1 0 0 1 (1) (1) (1) (1) LDAEXB{<c>}{<q>} <Rt>, [<Rn>] t = UInt(Rt); n = UInt(Rn); if t == 15 || n == 15 then UNPREDICTABLE; 1 1 1 0 1 0 0 0 1 1 0 1 (1) (1) (1) (1) 1 1 0 0 (1) (1) (1) (1) LDAEXB{<c>}{<q>} <Rt>, [<Rn>] t = UInt(Rt); n = UInt(Rn); if t == 15 || n == 15 then UNPREDICTABLE; <c> See Standard assembler syntax fields. <q> See Standard assembler syntax fields. <Rt> Is the general-purpose register to be transferred, encoded in the "Rt" field. <Rn> Is the general-purpose base register, encoded in the "Rn" field. if ConditionPassed() then EncodingSpecificOperations(); address = R[n]; AArch32.SetExclusiveMonitors(address, 1); R[t] = ZeroExtend(MemO[address, 1], 32);