CMN (register) Compare Negative (register) Compare Negative (register) adds a register value and an optionally-shifted register value. It updates the condition flags based on the result, and discards the result. For more information about the constrained unpredictable behavior, see Architectural Constraints on UNPREDICTABLE behaviors. If CPSR.DIT is 1, this instruction has passed its condition execution check, and does not use R15 as either its source or destination: The execution time of this instruction is independent of:The values of the data supplied in any of its registers.The values of the NZCV flags. The response of this instruction to asynchronous exceptions does not vary based on:The values of the data supplied in any of its registers.The values of the NZCV flags. It has encodings from the following instruction sets: A32 ( A1 ) and T32 ( T1 and T2 ) . != 1111 0 0 0 1 0 1 1 1 (0) (0) (0) (0) 0 0 0 0 0 0 1 1 CMN{<c>}{<q>} <Rn>, <Rm>, RRX Z Z Z Z Z N N CMN{<c>}{<q>} <Rn>, <Rm> {, <shift> #<amount>} n = UInt(Rn); m = UInt(Rm); (shift_t, shift_n) = DecodeImmShift(stype, imm5); 0 1 0 0 0 0 1 0 1 1 CMN{<c>}{<q>} <Rn>, <Rm> n = UInt(Rn); m = UInt(Rm); (shift_t, shift_n) = (SRType_LSL, 0); 1 1 1 0 1 0 1 1 0 0 0 1 (0) 1 1 1 1 0 0 0 0 0 1 1 CMN{<c>}{<q>} <Rn>, <Rm>, RRX Z Z Z Z Z N N CMN{<c>}.W <Rn>, <Rm> CMN{<c>}{<q>} <Rn>, <Rm> {, <shift> #<amount>} n = UInt(Rn); m = UInt(Rm); (shift_t, shift_n) = DecodeImmShift(stype, imm3:imm2); if n == 15 || m == 15 then UNPREDICTABLE; // Armv8-A removes UNPREDICTABLE for R13 <c> See Standard assembler syntax fields. <q> See Standard assembler syntax fields. <Rn> For encoding A1: is the first general-purpose source register, encoded in the "Rn" field. The PC can be used, but this is deprecated. <Rn> For encoding T1 and T2: is the first general-purpose source register, encoded in the "Rn" field. <Rm> For encoding A1: is the second general-purpose source register, encoded in the "Rm" field. The PC can be used, but this is deprecated. <Rm> For encoding T1 and T2: is the second general-purpose source register, encoded in the "Rm" field. <shift> Is the type of shift to be applied to the second source register, stype <shift> 00 LSL 01 LSR 10 ASR 11 ROR <amount> For encoding A1: is the shift amount, in the range 1 to 31 (when <shift> = LSL or ROR) or 1 to 32 (when <shift> = LSR or ASR) encoded in the "imm5" field as <amount> modulo 32. <amount> For encoding T2: is the shift amount, in the range 1 to 31 (when <shift> = LSL or ROR) or 1 to 32 (when <shift> = LSR or ASR), encoded in the "imm3:imm2" field as <amount> modulo 32. if ConditionPassed() then EncodingSpecificOperations(); shifted = Shift(R[m], shift_t, shift_n, PSTATE.C); (result, nzcv) = AddWithCarry(R[n], shifted, '0'); PSTATE.<N,Z,C,V> = nzcv;