VTRN Vector Transpose Vector Transpose treats the elements of its operand vectors as elements of 2 x 2 matrices, and transposes the matrices. The elements of the vectors can be 8-bit, 16-bit, or 32-bit. There is no distinction between data types. Depending on settings in the CPACR, NSACR, and HCPTR registers, and the Security state and PE mode in which the instruction is executed, an attempt to execute the instruction might be undefined, or trapped to Hyp mode. For more information see Enabling Advanced SIMD and floating-point support. If CPSR.DIT is 1 and this instruction passes its condition execution check: The execution time of this instruction is independent of:The values of the data supplied in any of its registers.The values of the NZCV flags. The response of this instruction to asynchronous exceptions does not vary based on:The values of the data supplied in any of its registers.The values of the NZCV flags. This instruction is used by the aliases VUZP (alias) Never VZIP (alias) Never See below for details of when each alias is preferred. It has encodings from the following instruction sets: A32 ( A1 ) and T32 ( T1 ) . 1 1 1 1 0 0 1 1 1 1 1 1 0 0 0 0 0 1 0 0 VTRN{<c>}{<q>}.<dt> <Dd>, <Dm> 1 VTRN{<c>}{<q>}.<dt> <Qd>, <Qm> if size == '11' then UNDEFINED; if Q == '1' && (Vd<0> == '1' || Vm<0> == '1') then UNDEFINED; esize = 8 << UInt(size); elements = 64 DIV esize; d = UInt(D:Vd); m = UInt(M:Vm); regs = if Q == '0' then 1 else 2; 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 1 0 0 VTRN{<c>}{<q>}.<dt> <Dd>, <Dm> 1 VTRN{<c>}{<q>}.<dt> <Qd>, <Qm> if size == '11' then UNDEFINED; if Q == '1' && (Vd<0> == '1' || Vm<0> == '1') then UNDEFINED; esize = 8 << UInt(size); elements = 64 DIV esize; d = UInt(D:Vd); m = UInt(M:Vm); regs = if Q == '0' then 1 else 2; <c> For encoding A1: see Standard assembler syntax fields. This encoding must be unconditional. <c> For encoding T1: see Standard assembler syntax fields. <q> See Standard assembler syntax fields. <dt> Is the data type for the elements of the vectors, size <dt> 00 8 01 16 10 32 11 RESERVED <Qd> Is the 128-bit name of the SIMD&FP destination register, encoded in the "D:Vd" field as <Qd>*2. <Qm> Is the 128-bit name of the SIMD&FP source register, encoded in the "M:Vm" field as <Qm>*2. <Dd> Is the 64-bit name of the SIMD&FP destination register, encoded in the "D:Vd" field. <Dm> Is the 64-bit name of the SIMD&FP source register, encoded in the "M:Vm" field. Alias Conditions if ConditionPassed() then EncodingSpecificOperations(); CheckAdvSIMDEnabled(); h = elements DIV 2; for r = 0 to regs-1 if d == m then D[d+r] = bits(64) UNKNOWN; else for e = 0 to h-1 Elem[D[d+r],2*e+1,esize] = Elem[Din[m+r],2*e,esize]; Elem[D[m+r],2*e,esize] = Elem[Din[d+r],2*e+1,esize];