VST1 (single element from one lane) Store single element from one lane of one register Store single element from one lane of one register stores one element to memory from one element of a register. For details of the addressing mode, see Advanced SIMD addressing mode. Depending on settings in the CPACR, NSACR, and HCPTR registers, and the Security state and PE mode in which the instruction is executed, an attempt to execute the instruction might be undefined, or trapped to Hyp mode. For more information, see Enabling Advanced SIMD and floating-point support. For more information about the constrained unpredictable behavior of this instruction, see Architectural Constraints on UNPREDICTABLE behaviors. For more information about the variants of this instruction, see Advanced SIMD addressing mode. If CPSR.DIT is 1, the timing of this instruction is insensitive to the value of the data being loaded or stored. It has encodings from the following instruction sets: A32 ( A1 , A2 and A3 ) and T32 ( T1 , T2 and T3 ) . 1 1 1 1 0 1 0 0 1 0 0 0 0 0 0 1 1 1 1 VST1{<c>}{<q>}.<size> <list>, [<Rn>{:<align>}] 1 1 0 1 VST1{<c>}{<q>}.<size> <list>, [<Rn>{:<align>}]! N N N VST1{<c>}{<q>}.<size> <list>, [<Rn>{:<align>}], <Rm> if size == '11' then UNDEFINED; if index_align<0> != '0' then UNDEFINED; ebytes = 1; index = UInt(index_align<3:1>); alignment = 1; d = UInt(D:Vd); n = UInt(Rn); m = UInt(Rm); wback = (m != 15); register_index = (m != 15 && m != 13); if n == 15 then UNPREDICTABLE; 1 1 1 1 0 1 0 0 1 0 0 0 1 0 0 1 1 1 1 VST1{<c>}{<q>}.<size> <list>, [<Rn>{:<align>}] 1 1 0 1 VST1{<c>}{<q>}.<size> <list>, [<Rn>{:<align>}]! N N N VST1{<c>}{<q>}.<size> <list>, [<Rn>{:<align>}], <Rm> if size == '11' then UNDEFINED; if index_align<1> != '0' then UNDEFINED; ebytes = 2; index = UInt(index_align<3:2>); alignment = if index_align<0> == '0' then 1 else 2; d = UInt(D:Vd); n = UInt(Rn); m = UInt(Rm); wback = (m != 15); register_index = (m != 15 && m != 13); if n == 15 then UNPREDICTABLE; 1 1 1 1 0 1 0 0 1 0 0 1 0 0 0 1 1 1 1 VST1{<c>}{<q>}.<size> <list>, [<Rn>{:<align>}] 1 1 0 1 VST1{<c>}{<q>}.<size> <list>, [<Rn>{:<align>}]! N N N VST1{<c>}{<q>}.<size> <list>, [<Rn>{:<align>}], <Rm> if size == '11' then UNDEFINED; if index_align<2> != '0' then UNDEFINED; if index_align<1:0> != '00' && index_align<1:0> != '11' then UNDEFINED; ebytes = 4; index = UInt(index_align<3>); alignment = if index_align<1:0> == '00' then 1 else 4; d = UInt(D:Vd); n = UInt(Rn); m = UInt(Rm); wback = (m != 15); register_index = (m != 15 && m != 13); if n == 15 then UNPREDICTABLE; 1 1 1 1 1 0 0 1 1 0 0 0 0 0 0 1 1 1 1 VST1{<c>}{<q>}.<size> <list>, [<Rn>{:<align>}] 1 1 0 1 VST1{<c>}{<q>}.<size> <list>, [<Rn>{:<align>}]! N N N VST1{<c>}{<q>}.<size> <list>, [<Rn>{:<align>}], <Rm> if size == '11' then UNDEFINED; if index_align<0> != '0' then UNDEFINED; ebytes = 1; index = UInt(index_align<3:1>); alignment = 1; d = UInt(D:Vd); n = UInt(Rn); m = UInt(Rm); wback = (m != 15); register_index = (m != 15 && m != 13); if n == 15 then UNPREDICTABLE; 1 1 1 1 1 0 0 1 1 0 0 0 1 0 0 1 1 1 1 VST1{<c>}{<q>}.<size> <list>, [<Rn>{:<align>}] 1 1 0 1 VST1{<c>}{<q>}.<size> <list>, [<Rn>{:<align>}]! N N N VST1{<c>}{<q>}.<size> <list>, [<Rn>{:<align>}], <Rm> if size == '11' then UNDEFINED; if index_align<1> != '0' then UNDEFINED; ebytes = 2; index = UInt(index_align<3:2>); alignment = if index_align<0> == '0' then 1 else 2; d = UInt(D:Vd); n = UInt(Rn); m = UInt(Rm); wback = (m != 15); register_index = (m != 15 && m != 13); if n == 15 then UNPREDICTABLE; 1 1 1 1 1 0 0 1 1 0 0 1 0 0 0 1 1 1 1 VST1{<c>}{<q>}.<size> <list>, [<Rn>{:<align>}] 1 1 0 1 VST1{<c>}{<q>}.<size> <list>, [<Rn>{:<align>}]! N N N VST1{<c>}{<q>}.<size> <list>, [<Rn>{:<align>}], <Rm> if size == '11' then UNDEFINED; if index_align<2> != '0' then UNDEFINED; if index_align<1:0> != '00' && index_align<1:0> != '11' then UNDEFINED; ebytes = 4; index = UInt(index_align<3>); alignment = if index_align<1:0> == '00' then 1 else 4; d = UInt(D:Vd); n = UInt(Rn); m = UInt(Rm); wback = (m != 15); register_index = (m != 15 && m != 13); if n == 15 then UNPREDICTABLE; <c> For encoding A1, A2 and A3: see Standard assembler syntax fields. This encoding must be unconditional. <c> For encoding T1, T2 and T3: see Standard assembler syntax fields. <q> See Standard assembler syntax fields. <size> Is the data size, size <size> 00 8 01 16 10 32 <list> Is a list containing the single 64-bit name of the SIMD&FP register holding the element. The list must be { <Dd>[<index>] }. The register <Dd> is encoded in the "D:Vd" field. The permitted values and encoding of <index> depend on <size>: <size> == 8<index> is in the range 0 to 7, encoded in the "index_align<3:1>" field. <size> == 16<index> is in the range 0 to 3, encoded in the "index_align<3:2>" field. <size> == 32<index> is 0 or 1, encoded in the "index_align<3>" field. <Rn> Is the general-purpose base register, encoded in the "Rn" field. <align> When <size> == 8, <align> must be omitted, otherwise it is the optional alignment. Whenever <align> is omitted, the standard alignment is used, see Unaligned data access, and the encoding depends on <size>: <size> == 8Encoded in the "index_align<0>" field as 0. <size> == 16Encoded in the "index_align<1:0>" field as 0b00. <size> == 32Encoded in the "index_align<2:0>" field as 0b000. Whenever <align> is present, the permitted values and encoding depend on <size>: <size> == 16<align> is 16, meaning 16-bit alignment, encoded in the "index_align<1:0>" field as 0b01. <size> == 32<align> is 32, meaning 32-bit alignment, encoded in the "index_align<2:0>" field as 0b011. : is the preferred separator before the <align> value, but the alignment can be specified as @<align>, see Advanced SIMD addressing mode. <Rm> Is the general-purpose index register containing an offset applied after the access, encoded in the "Rm" field. if ConditionPassed() then EncodingSpecificOperations(); CheckAdvSIMDEnabled(); address = R[n]; boolean nontemporal = FALSE; boolean tagchecked = FALSE; AccessDescriptor accdesc = CreateAccDescASIMD(MemOp_STORE, nontemporal, tagchecked); if !IsAligned(address, alignment) then AArch32.Abort(address, AlignmentFault(accdesc)); MemU[address,ebytes] = Elem[D[d],index,8*ebytes]; if wback then if register_index then R[n] = R[n] + R[m]; else R[n] = R[n] + ebytes;