VRSHR (zero) Vector Rounding Shift Right copies the contents of one SIMD register to another VORR (register) It has encodings from the following instruction sets: A32 ( A1 ) and T32 ( T1 ) . 1 1 1 1 0 0 1 0 0 1 0 0 0 0 1 1 0 VRSHR{<c>}{<q>}.<dt> <Dd>, <Dm>, #0 VORR{<c>}{<q>}{.<dt>} <Dd>, <Dm>, <Dm> Never 1 VRSHR{<c>}{<q>}.<dt> <Qd>, <Qm>, #0 VORR{<c>}{<q>}{.<dt>} <Qd>, <Qm>, <Qm> Never 1 1 1 0 1 1 1 1 0 1 0 0 0 0 1 1 0 VRSHR{<c>}{<q>}.<dt> <Dd>, <Dm>, #0 VORR{<c>}{<q>}{.<dt>} <Dd>, <Dm>, <Dm> Never 1 VRSHR{<c>}{<q>}.<dt> <Qd>, <Qm>, #0 VORR{<c>}{<q>}{.<dt>} <Qd>, <Qm>, <Qm> Never <c> For encoding A1: see Standard assembler syntax fields. This encoding must be unconditional. <c> For encoding T1: see Standard assembler syntax fields. <q> See Standard assembler syntax fields. <dt> Is the data type for the elements of the vectors, and must be one of: S8, S16, S32, S64, U8, U16, U32 or U64. <Qd> Is the 128-bit name of the SIMD&FP destination register, encoded in the "D:Vd" field as <Qd>*2. <Qm> Is the 128-bit name of the SIMD&FP source register, encoded in the "N:Vn" and "M:Vm" field as <Qm>*2. <Dd> Is the 64-bit name of the SIMD&FP destination register, encoded in the "D:Vd" field. <Dm> Is the 64-bit name of the SIMD&FP source register, encoded in the "N:Vn" and "M:Vm" field.