VQRSHRN (zero) Vector Saturating Rounding Shift Right, Narrow takes each element in a quadword vector of integers, right shifts them by an immediate value, and places the signed rounded results in a doubleword vector VQMOVN, VQMOVUN It has encodings from the following instruction sets: A32 ( A1 ) and T32 ( T1 ) . 1 1 1 1 0 0 1 1 1 1 1 1 0 0 0 1 0 1 x 0 VQRSHRN{<c>}{<q>}.<dt> <Dd>, <Qm>, #0 VQMOVN{<c>}{<q>}.<dt> <Dd>, <Qm> Never 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 1 0 1 x 0 VQRSHRN{<c>}{<q>}.<dt> <Dd>, <Qm>, #0 VQMOVN{<c>}{<q>}.<dt> <Dd>, <Qm> Never <c> For encoding A1: see Standard assembler syntax fields. This encoding must be unconditional. <c> For encoding T1: see Standard assembler syntax fields. <q> See Standard assembler syntax fields. <dt> Is the data type for the elements of the operand, op<0> size <dt> 0 00 S16 0 01 S32 0 10 S64 0 11 RESERVED 1 00 U16 1 01 U32 1 10 U64 1 11 RESERVED <Dd> Is the 64-bit name of the SIMD&FP destination register, encoded in the "D:Vd" field. <Qm> Is the 128-bit name of the SIMD&FP source register, encoded in the "M:Vm" field as <Qm>*2.