VFNMA Vector Fused Negate Multiply Accumulate Vector Fused Negate Multiply Accumulate negates one floating-point register value and multiplies it by another floating-point register value, adds the negation of the floating-point value in the destination register to the product, and writes the result back to the destination register. The instruction does not round the result of the multiply before the addition. Depending on settings in the CPACR, NSACR, HCPTR, and FPEXC registers, and the Security state and PE mode in which the instruction is executed, an attempt to execute the instruction might be undefined, or trapped to Hyp mode. For more information see Enabling Advanced SIMD and floating-point support. It has encodings from the following instruction sets: A32 ( A1 ) and T32 ( T1 ) . != 1111 1 1 1 0 1 0 1 1 0 1 0 0 1 VFNMA{<c>}{<q>}.F16 <Sd>, <Sn>, <Sm> 1 0 VFNMA{<c>}{<q>}.F32 <Sd>, <Sn>, <Sm> 1 1 VFNMA{<c>}{<q>}.F64 <Dd>, <Dn>, <Dm> if FPSCR.Len != '000' || FPSCR.Stride != '00' then UNDEFINED; if size == '00' || (size == '01' && !HaveFP16Ext()) then UNDEFINED; if size == '01' && cond != '1110' then UNPREDICTABLE; op1_neg = (op == '1'); integer esize; integer d; integer n; integer m; case size of when '01' esize = 16; d = UInt(Vd:D); n = UInt(Vn:N); m = UInt(Vm:M); when '10' esize = 32; d = UInt(Vd:D); n = UInt(Vn:N); m = UInt(Vm:M); when '11' esize = 64; d = UInt(D:Vd); n = UInt(N:Vn); m = UInt(M:Vm); size == '01' && cond != '1110' The instruction executes as if it passes the Condition code check. The instruction executes as NOP. This means it behaves as if it fails the Condition code check. 1 1 1 0 1 1 1 0 1 0 1 1 0 1 0 0 1 VFNMA{<c>}{<q>}.F16 <Sd>, <Sn>, <Sm> 1 0 VFNMA{<c>}{<q>}.F32 <Sd>, <Sn>, <Sm> 1 1 VFNMA{<c>}{<q>}.F64 <Dd>, <Dn>, <Dm> if FPSCR.Len != '000' || FPSCR.Stride != '00' then UNDEFINED; if size == '00' || (size == '01' && !HaveFP16Ext()) then UNDEFINED; if size == '01' && InITBlock() then UNPREDICTABLE; op1_neg = (op == '1'); integer esize; integer d; integer n; integer m; case size of when '01' esize = 16; d = UInt(Vd:D); n = UInt(Vn:N); m = UInt(Vm:M); when '10' esize = 32; d = UInt(Vd:D); n = UInt(Vn:N); m = UInt(Vm:M); when '11' esize = 64; d = UInt(D:Vd); n = UInt(N:Vn); m = UInt(M:Vm); size == '01' && InITBlock() The instruction executes as if it passes the Condition code check. The instruction executes as NOP. This means it behaves as if it fails the Condition code check. <c> See Standard assembler syntax fields. <q> See Standard assembler syntax fields. <Sd> Is the 32-bit name of the SIMD&FP destination register, encoded in the "Vd:D" field. <Sn> Is the 32-bit name of the first SIMD&FP source register, encoded in the "Vn:N" field. <Sm> Is the 32-bit name of the second SIMD&FP source register, encoded in the "Vm:M" field. <Dd> Is the 64-bit name of the SIMD&FP destination register, encoded in the "D:Vd" field. <Dn> Is the 64-bit name of the first SIMD&FP source register, encoded in the "N:Vn" field. <Dm> Is the 64-bit name of the second SIMD&FP source register, encoded in the "M:Vm" field. if ConditionPassed() then EncodingSpecificOperations(); CheckVFPEnabled(TRUE); case esize of when 16 op16 = if op1_neg then FPNeg(S[n]<15:0>) else S[n]<15:0>; S[d] = Zeros(16) : FPMulAdd(FPNeg(S[d]<15:0>), op16, S[m]<15:0>, FPSCR[]); when 32 op32 = if op1_neg then FPNeg(S[n]) else S[n]; S[d] = FPMulAdd(FPNeg(S[d]), op32, S[m], FPSCR[]); when 64 op64 = if op1_neg then FPNeg(D[n]) else D[n]; D[d] = FPMulAdd(FPNeg(D[d]), op64, D[m], FPSCR[]);