VCLT (register)
Vector Compare Less Than
Vector Compare Less Than takes each element in a vector, and compares it with the corresponding element of a second vector. If the first is less than the second, the corresponding element in the destination vector is set to all ones. Otherwise, it is set to all zeros.
The description of VCGT_r gives the operational pseudocode for this instruction.
VCGT (register)
It has encodings from the following instruction sets:
A32 (
A1
and
A2
)
and
T32 (
T1
and
T2
)
.
1
1
1
1
0
0
1
0
0
0
1
1
0
0
VCLT{<c>}{<q>}.<dt> {<Dd>, }<Dn>, <Dm>
VCGT{<c>}{<q>}.<dt> <Dd>, <Dm>, <Dn>
Never
1
VCLT{<c>}{<q>}.<dt> {<Qd>, }<Qn>, <Qm>
VCGT{<c>}{<q>}.<dt> <Qd>, <Qm>, <Qn>
Never
1
1
1
1
0
0
1
1
0
1
1
1
1
0
0
0
VCLT{<c>}{<q>}.<dt> {<Dd>, }<Dn>, <Dm>
VCGT{<c>}{<q>}.<dt> <Dd>, <Dm>, <Dn>
Never
1
VCLT{<c>}{<q>}.<dt> {<Qd>, }<Qn>, <Qm>
VCGT{<c>}{<q>}.<dt> <Qd>, <Qm>, <Qn>
Never
1
1
1
1
1
1
1
0
0
0
1
1
0
0
VCLT{<c>}{<q>}.<dt> {<Dd>, }<Dn>, <Dm>
VCGT{<c>}{<q>}.<dt> <Dd>, <Dm>, <Dn>
Never
1
VCLT{<c>}{<q>}.<dt> {<Qd>, }<Qn>, <Qm>
VCGT{<c>}{<q>}.<dt> <Qd>, <Qm>, <Qn>
Never
1
1
1
1
1
1
1
1
0
1
1
1
1
0
0
0
VCLT{<c>}{<q>}.<dt> {<Dd>, }<Dn>, <Dm>
VCGT{<c>}{<q>}.<dt> <Dd>, <Dm>, <Dn>
Never
1
VCLT{<c>}{<q>}.<dt> {<Qd>, }<Qn>, <Qm>
VCGT{<c>}{<q>}.<dt> <Qd>, <Qm>, <Qn>
Never
<Dm>
Is the 64-bit name of the second SIMD&FP source register, encoded in the "M:Vm" field.
<Dn>
Is the 64-bit name of the first SIMD&FP source register, encoded in the "N:Vn" field.
<Qm>
Is the 128-bit name of the second SIMD&FP source register, encoded in the "M:Vm" field as <Qm>*2.
<Qn>
Is the 128-bit name of the first SIMD&FP source register, encoded in the "N:Vn" field as <Qn>*2.
<c>
For encoding A1 and A2: see Standard assembler syntax fields. This encoding must be unconditional.
<c>
For encoding T1 and T2: see Standard assembler syntax fields.
<q>
See Standard assembler syntax fields.
<dt>
For encoding A1 and T1: is the data type for the elements of the operands,
U
size
<dt>
0
00
S8
0
01
S16
0
10
S32
1
00
U8
1
01
U16
1
10
U32
<dt>
For encoding A2 and T2: is the data type for the elements of the vectors,
<Qd>
Is the 128-bit name of the SIMD&FP destination register, encoded in the "D:Vd" field as <Qd>*2.
<Dd>
Is the 64-bit name of the SIMD&FP destination register, encoded in the "D:Vd" field.