STRH (immediate)
Store Register Halfword (immediate)
Store Register Halfword (immediate) calculates an address from a base register value and an immediate offset, and stores a halfword from a register to memory. It can use offset, post-indexed, or pre-indexed addressing. For information about memory accesses see Memory accesses.
For more information about the constrained unpredictable behavior of this instruction, see Architectural Constraints on UNPREDICTABLE behaviors.
If CPSR.DIT is 1, the timing of this instruction is insensitive to the value of the data being loaded or stored.
It has encodings from the following instruction sets:
A32 (
A1
)
and
T32 (
T1
,
T2
and
T3
)
.
!= 1111
0
0
0
1
0
1
0
1
1
1
0
STRH{<c>}{<q>} <Rt>, [<Rn> {, #{+/-}<imm>}]
0
0
STRH{<c>}{<q>} <Rt>, [<Rn>], #{+/-}<imm>
1
1
STRH{<c>}{<q>} <Rt>, [<Rn>, #{+/-}<imm>]!
if P == '0' && W == '1' then SEE "STRHT";
t = UInt(Rt); n = UInt(Rn); imm32 = ZeroExtend(imm4H:imm4L, 32);
index = (P == '1'); add = (U == '1'); wback = (P == '0') || (W == '1');
if t == 15 then UNPREDICTABLE;
if wback && (n == 15 || n == t) then UNPREDICTABLE;
t == 15
The store instruction performs the store using the specified addressing mode but the value corresponding to R15 is unknown.
wback && n == t
wback && n == 15
The instruction uses the addressing mode described in the equivalent immediate offset instruction.
1
0
0
0
0
STRH{<c>}{<q>} <Rt>, [<Rn> {, #{+}<imm>}]
t = UInt(Rt); n = UInt(Rn); imm32 = ZeroExtend(imm5:'0', 32);
index = TRUE; add = TRUE; wback = FALSE;
1
1
1
1
1
0
0
0
1
0
1
0
!= 1111
STRH{<c>}.W <Rt>, [<Rn> {, #{+}<imm>}]
STRH{<c>}{<q>} <Rt>, [<Rn> {, #{+}<imm>}]
if Rn == '1111' then UNDEFINED;
t = UInt(Rt); n = UInt(Rn); imm32 = ZeroExtend(imm12, 32);
index = TRUE; add = TRUE; wback = FALSE;
if t == 15 then UNPREDICTABLE; // Armv8-A removes UNPREDICTABLE for R13
t == 15
The store instruction performs the store using the specified addressing mode but the value corresponding to R15 is unknown.
1
1
1
1
1
0
0
0
0
0
1
0
!= 1111
1
1
0
0
STRH{<c>}{<q>} <Rt>, [<Rn> {, #-<imm>}]
0
1
STRH{<c>}{<q>} <Rt>, [<Rn>], #{+/-}<imm>
1
1
STRH{<c>}{<q>} <Rt>, [<Rn>, #{+/-}<imm>]!
if P == '1' && U == '1' && W == '0' then SEE "STRHT";
if Rn == '1111' || (P == '0' && W == '0') then UNDEFINED;
t = UInt(Rt); n = UInt(Rn); imm32 = ZeroExtend(imm8, 32);
index = (P == '1'); add = (U == '1'); wback = (W == '1');
if t == 15 || (wback && n == t) then UNPREDICTABLE; // Armv8-A removes UNPREDICTABLE for R13
t == 15
The store instruction performs the store using the specified addressing mode but the value corresponding to R15 is unknown.
wback && n == t
<c>
See Standard assembler syntax fields.
<q>
See Standard assembler syntax fields.
<Rt>
Is the general-purpose register to be transferred, encoded in the "Rt" field.
<Rn>
For encoding A1: is the general-purpose base register, encoded in the "Rn" field. The PC can be used in the offset variant, but this is deprecated.
<Rn>
For encoding A1, T1, T2, T3: is the general-purpose base register, encoded in the "Rn" field.
+/-
Specifies the offset is added to or subtracted from the base register, defaulting to + if omitted and
+
Specifies the offset is added to the base register.
<imm>
For encoding A1: is the 8-bit unsigned immediate byte offset, in the range 0 to 255, defaulting to 0 if omitted, and encoded in the "imm4H:imm4L" field.
<imm>
For encoding T1: is the optional positive unsigned immediate byte offset, a multiple of 2, in the range 0 to 62, defaulting to 0 and encoded in the "imm5" field as <imm>/2.
<imm>
For encoding T2: is an optional 12-bit unsigned immediate byte offset, in the range 0 to 4095, defaulting to 0 and encoded in the "imm12" field.
<imm>
For encoding T3: is an 8-bit unsigned immediate byte offset, in the range 0 to 255, defaulting to 0 if omitted, and encoded in the "imm8" field.
if CurrentInstrSet() == InstrSet_A32 then
if ConditionPassed() then
EncodingSpecificOperations();
offset_addr = if add then (R[n] + imm32) else (R[n] - imm32);
address = if index then offset_addr else R[n];
MemU[address,2] = R[t]<15:0>;
if wback then R[n] = offset_addr;
else
if ConditionPassed() then
EncodingSpecificOperations();
offset_addr = if add then (R[n] + imm32) else (R[n] - imm32);
address = if index then offset_addr else R[n];
MemU[address,2] = R[t]<15:0>;
if wback then R[n] = offset_addr;