SMLSD, SMLSDX Signed Multiply Subtract Dual Signed Multiply Subtract Dual performs two signed 16 x 16-bit multiplications. It adds the difference of the products to a 32-bit accumulate operand. Optionally, the instruction can exchange the halfwords of the second operand before performing the arithmetic. This produces top x bottom and bottom x top multiplication. This instruction sets PSTATE.Q to 1 if the accumulate operation overflows. Overflow cannot occur during the multiplications or subtraction. For more information about the constrained unpredictable behavior of this instruction, see Architectural Constraints on UNPREDICTABLE behaviors. If CPSR.DIT is 1, this instruction has passed its condition execution check, and does not use R15 as either its source or destination: The execution time of this instruction is independent of:The values of the data supplied in any of its registers.The values of the NZCV flags. The response of this instruction to asynchronous exceptions does not vary based on:The values of the data supplied in any of its registers.The values of the NZCV flags. It has encodings from the following instruction sets: A32 ( A1 ) and T32 ( T1 ) . != 1111 0 1 1 1 0 0 0 0 != 1111 0 1 1 0 SMLSD{<c>}{<q>} <Rd>, <Rn>, <Rm>, <Ra> 1 SMLSDX{<c>}{<q>} <Rd>, <Rn>, <Rm>, <Ra> if Ra == '1111' then SEE "SMUSD"; d = UInt(Rd); n = UInt(Rn); m = UInt(Rm); a = UInt(Ra); m_swap = (M == '1'); if d == 15 || n == 15 || m == 15 then UNPREDICTABLE; 1 1 1 1 1 0 1 1 0 1 0 0 != 1111 0 0 0 0 SMLSD{<c>}{<q>} <Rd>, <Rn>, <Rm>, <Ra> 1 SMLSDX{<c>}{<q>} <Rd>, <Rn>, <Rm>, <Ra> if Ra == '1111' then SEE "SMUSD"; d = UInt(Rd); n = UInt(Rn); m = UInt(Rm); a = UInt(Ra); m_swap = (M == '1'); if d == 15 || n == 15 || m == 15 then UNPREDICTABLE; // Armv8-A removes UNPREDICTABLE for R13 <c> See Standard assembler syntax fields. <q> See Standard assembler syntax fields. <Rd> Is the general-purpose destination register, encoded in the "Rd" field. <Rn> Is the first general-purpose source register, encoded in the "Rn" field. <Rm> Is the second general-purpose source register, encoded in the "Rm" field. <Ra> Is the third general-purpose source register holding the addend, encoded in the "Ra" field. if ConditionPassed() then EncodingSpecificOperations(); operand2 = if m_swap then ROR(R[m],16) else R[m]; product1 = SInt(R[n]<15:0>) * SInt(operand2<15:0>); product2 = SInt(R[n]<31:16>) * SInt(operand2<31:16>); result = (product1 - product2) + SInt(R[a]); R[d] = result<31:0>; if result != SInt(result<31:0>) then // Signed overflow PSTATE.Q = '1';