SMLALBB, SMLALBT, SMLALTB, SMLALTT Signed Multiply Accumulate Long (halfwords) Signed Multiply Accumulate Long (halfwords) multiplies two signed 16-bit values to produce a 32-bit value, and accumulates this with a 64-bit value. The multiply acts on two signed 16-bit quantities, taken from either the bottom or the top half of their respective source registers. The other halves of these source registers are ignored. The 32-bit product is sign-extended and accumulated with a 64-bit accumulate value. Overflow is possible during this instruction, but only as a result of the 64-bit addition. This overflow is not detected if it occurs. Instead, the result wraps around modulo 2⁶⁴. For more information about the constrained unpredictable behavior of this instruction, see Architectural Constraints on UNPREDICTABLE behaviors. If CPSR.DIT is 1, this instruction has passed its condition execution check, and does not use R15 as either its source or destination: The execution time of this instruction is independent of:The values of the data supplied in any of its registers.The values of the NZCV flags. The response of this instruction to asynchronous exceptions does not vary based on:The values of the data supplied in any of its registers.The values of the NZCV flags. It has encodings from the following instruction sets: A32 ( A1 ) and T32 ( T1 ) . != 1111 0 0 0 1 0 1 0 0 1 0 0 0 SMLALBB{<c>}{<q>} <RdLo>, <RdHi>, <Rn>, <Rm> 1 0 SMLALBT{<c>}{<q>} <RdLo>, <RdHi>, <Rn>, <Rm> 0 1 SMLALTB{<c>}{<q>} <RdLo>, <RdHi>, <Rn>, <Rm> 1 1 SMLALTT{<c>}{<q>} <RdLo>, <RdHi>, <Rn>, <Rm> dLo = UInt(RdLo); dHi = UInt(RdHi); n = UInt(Rn); m = UInt(Rm); n_high = (N == '1'); m_high = (M == '1'); if dLo == 15 || dHi == 15 || n == 15 || m == 15 then UNPREDICTABLE; if dHi == dLo then UNPREDICTABLE; dHi == dLo 1 1 1 1 1 0 1 1 1 1 0 0 1 0 0 0 SMLALBB{<c>}{<q>} <RdLo>, <RdHi>, <Rn>, <Rm> 0 1 SMLALBT{<c>}{<q>} <RdLo>, <RdHi>, <Rn>, <Rm> 1 0 SMLALTB{<c>}{<q>} <RdLo>, <RdHi>, <Rn>, <Rm> 1 1 SMLALTT{<c>}{<q>} <RdLo>, <RdHi>, <Rn>, <Rm> dLo = UInt(RdLo); dHi = UInt(RdHi); n = UInt(Rn); m = UInt(Rm); n_high = (N == '1'); m_high = (M == '1'); if dLo == 15 || dHi == 15 || n == 15 || m == 15 then UNPREDICTABLE; // Armv8-A removes UNPREDICTABLE for R13 if dHi == dLo then UNPREDICTABLE; dHi == dLo <c> See Standard assembler syntax fields. <q> See Standard assembler syntax fields. <RdLo> Is the general-purpose source register holding the lower 32 bits of the addend, and the destination register for the lower 32 bits of the result, encoded in the "RdLo" field. <RdHi> Is the general-purpose source register holding the upper 32 bits of the addend, and the destination register for the upper 32 bits of the result, encoded in the "RdHi" field. <Rn> For encoding A1: is the first general-purpose source register holding the multiplicand in the bottom or top half (selected by <x>), encoded in the "Rn" field. <Rn> For encoding T1: is the first general-purpose source register holding the multiplicand in the bottom or top half (selected by <x>), encoded in the "Rn" field. <Rm> For encoding A1: is the second general-purpose source register holding the multiplier in the bottom or top half (selected by <y>), encoded in the "Rm" field. <Rm> For encoding T1: is the second general-purpose source register holding the multiplier in the bottom or top half (selected by <x>), encoded in the "Rm" field. if ConditionPassed() then EncodingSpecificOperations(); operand1 = if n_high then R[n]<31:16> else R[n]<15:0>; operand2 = if m_high then R[m]<31:16> else R[m]<15:0>; result = SInt(operand1) * SInt(operand2) + SInt(R[dHi]:R[dLo]); R[dHi] = result<63:32>; R[dLo] = result<31:0>;