LDREXD Load Register Exclusive Doubleword Load Register Exclusive Doubleword derives an address from a base register value, loads a 64-bit doubleword from memory, writes it to two registers and: If the address has the Shared Memory attribute, marks the physical address as exclusive access for the executing PE in a global monitor. Causes the executing PE to indicate an active exclusive access in the local monitor. For more information about support for shared memory see Synchronization and semaphores. For information about memory accesses see Memory accesses. For more information about the constrained unpredictable behavior of this instruction, see Architectural Constraints on UNPREDICTABLE behaviors. If CPSR.DIT is 1, the timing of this instruction is insensitive to the value of the data being loaded or stored. It has encodings from the following instruction sets: A32 ( A1 ) and T32 ( T1 ) . != 1111 0 0 0 1 1 0 1 1 (1) (1) 1 1 1 0 0 1 (1) (1) (1) (1) LDREXD{<c>}{<q>} <Rt>, <Rt2>, [<Rn>] t = UInt(Rt); t2 = t + 1; n = UInt(Rn); if Rt<0> == '1' || t2 == 15 || n == 15 then UNPREDICTABLE; Rt<0> == '1' Rt == '1110' The instruction is handled as described in Using R15. 1 1 1 0 1 0 0 0 1 1 0 1 0 1 1 1 (1) (1) (1) (1) LDREXD{<c>}{<q>} <Rt>, <Rt2>, [<Rn>] t = UInt(Rt); t2 = UInt(Rt2); n = UInt(Rn); if t == 15 || t2 == 15 || t == t2 || n == 15 then UNPREDICTABLE; // Armv8-A removes UNPREDICTABLE for R13 t == t2 <c> See Standard assembler syntax fields. <q> See Standard assembler syntax fields. <Rt> For encoding A1: is the first general-purpose register to be transferred, encoded in the "Rt" field. <Rt> must be even-numbered and not R14. <Rt> For encoding T1: is the first general-purpose register to be transferred, encoded in the "Rt" field. <Rt2> For encoding A1: is the second general-purpose register to be transferred. <Rt2> must be <R(t+1)>. <Rt2> For encoding T1: is the second general-purpose register to be transferred, encoded in the "Rt2" field. <Rn> Is the general-purpose base register, encoded in the "Rn" field. if ConditionPassed() then EncodingSpecificOperations(); address = R[n]; AArch32.SetExclusiveMonitors(address,8); value = MemA[address,8]; // Extract words from 64-bit loaded value such that R[t] is // loaded from address and R[t2] from address+4. R[t] = if BigEndian(AccessType_GPR) then value<63:32> else value<31:0>; R[t2] = if BigEndian(AccessType_GPR) then value<31:0> else value<63:32>;