LDRD (literal)
Load Register Dual (literal)
Load Register Dual (literal) calculates an address from the PC value and an immediate offset, loads two words from memory, and writes them to two registers. For information about memory accesses see Memory accesses.
For more information about the constrained unpredictable behavior of this instruction, see Architectural Constraints on UNPREDICTABLE behaviors.
Related encodings: Load/Store dual, Load/Store-Exclusive, Load-Acquire/Store-Release, table branch.
The alternative syntax permits the addition or subtraction of the offset and the immediate offset to be specified separately, including permitting a subtraction of 0 that cannot be specified using the normal syntax. For more information, see Use of labels in UAL instruction syntax.
If CPSR.DIT is 1, the timing of this instruction is insensitive to the value of the data being loaded or stored.
It has encodings from the following instruction sets:
A32 (
A1
)
and
T32 (
T1
)
.
!= 1111
0
0
0
(1)
1
(0)
0
1
1
1
1
1
1
0
1
LDRD{<c>}{<q>} <Rt>, <Rt2>, <label>
LDRD{<c>}{<q>} <Rt>, <Rt2>, [PC, #{+/-}<imm>]
if Rt<0> == '1' then UNPREDICTABLE;
t = UInt(Rt); t2 = t+1; imm32 = ZeroExtend(imm4H:imm4L, 32); add = (U == '1');
if t2 == 15 then UNPREDICTABLE;
Rt<0> == '1'
The instruction executes as described, with no change to its behavior and no additional side-effects. This does not apply when Rt == '1111'.
P == '0' || W == '1'
The instruction executes as if P == 1 and W == 0.'
1
1
1
0
1
0
0
1
1
1
1
1
1
Z
Z
LDRD{<c>}{<q>} <Rt>, <Rt2>, <label>
LDRD{<c>}{<q>} <Rt>, <Rt2>, [PC, #{+/-}<imm>]
if P == '0' && W == '0' then SEE "Related encodings";
t = UInt(Rt); t2 = UInt(Rt2);
imm32 = ZeroExtend(imm8:'00', 32); add = (U == '1');
if t == 15 || t2 == 15 || t == t2 then UNPREDICTABLE; // Armv8-A removes UNPREDICTABLE for R13
if W == '1' then UNPREDICTABLE;
t == t2
W == '1'
The instruction uses post-indexed addressing when P == '0' and uses pre-indexed addressing otherwise. The instruction is handled as described in Using R15.
<c>
See Standard assembler syntax fields.
<q>
See Standard assembler syntax fields.
<Rt>
For encoding A1: is the first general-purpose register to be transferred, encoded in the "Rt" field. This register must be even-numbered and not R14.
<Rt>
For encoding T1: is the first general-purpose register to be transferred, encoded in the "Rt" field.
<Rt2>
For encoding A1: is the second general-purpose register to be transferred. This register must be <R(t+1)>.
<Rt2>
For encoding T1: is the second general-purpose register to be transferred, encoded in the "Rt2" field.
<label>
For encoding A1: the label of the literal data item that is to be loaded into <Rt>. The assembler calculates the required value of the offset from the Align(PC, 4) value of the instruction to this label. Any value in the range -255 to 255 is permitted.
If the offset is zero or positive, imm32 is equal to the offset and add == TRUE, encoded as U == 1. If the offset is negative, imm32 is equal to minus the offset and add == FALSE, encoded as U == 0.
<label>
For encoding T1: the label of the literal data item that is to be loaded into <Rt>. The assembler calculates the required value of the offset from the Align(PC, 4) value of the instruction to this label. Permitted values of the offset are multiples of 4 in the range -1020 to 1020.
If the offset is zero or positive, imm32 is equal to the offset and add == TRUE, encoded as U == 1.
If the offset is negative, imm32 is equal to minus the offset and add == FALSE, encoded as U == 0.
+/-
Specifies the offset is added to or subtracted from the base register, defaulting to + if omitted and
<imm>
For encoding A1: is the 8-bit unsigned immediate byte offset, in the range 0 to 255, defaulting to 0 if omitted, and encoded in the "imm4H:imm4L" field.
<imm>
For encoding T1: is the optional 8-bit unsigned immediate byte offset, in the range 0 to 255, defaulting to 0 and encoded in the "imm8" field.
if ConditionPassed() then
EncodingSpecificOperations();
address = if add then (Align(PC,4) + imm32) else (Align(PC,4) - imm32);
if IsAligned(address, 8) then
data = MemA[address,8];
if BigEndian(AccessType_GPR) then
R[t] = data<63:32>;
R[t2] = data<31:0>;
else
R[t] = data<31:0>;
R[t2] = data<63:32>;
else
R[t] = MemA[address,4];
R[t2] = MemA[address+4,4];