ADD, ADDS (register-shifted register) Add (register-shifted register) Add (register-shifted register) adds a register value and a register-shifted register value. It writes the result to the destination register, and can optionally update the condition flags based on the result. For more information about the constrained unpredictable behavior, see Architectural Constraints on UNPREDICTABLE behaviors. If CPSR.DIT is 1, this instruction has passed its condition execution check, and does not use R15 as either its source or destination: The execution time of this instruction is independent of:The values of the data supplied in any of its registers.The values of the NZCV flags. The response of this instruction to asynchronous exceptions does not vary based on:The values of the data supplied in any of its registers.The values of the NZCV flags. != 1111 0 0 0 0 1 0 0 0 1 1 ADDS{<c>}{<q>} {<Rd>,} <Rn>, <Rm>, <shift> <Rs> 0 ADD{<c>}{<q>} {<Rd>,} <Rn>, <Rm>, <shift> <Rs> d = UInt(Rd); n = UInt(Rn); m = UInt(Rm); s = UInt(Rs); setflags = (S == '1'); shift_t = DecodeRegShift(stype); if d == 15 || n == 15 || m == 15 || s == 15 then UNPREDICTABLE; <c> See Standard assembler syntax fields. <q> See Standard assembler syntax fields. <Rd> Is the general-purpose destination register, encoded in the "Rd" field. <Rn> Is the first general-purpose source register, encoded in the "Rn" field. <Rm> Is the second general-purpose source register, encoded in the "Rm" field. <shift> Is the type of shift to be applied to the second source register, stype <shift> 00 LSL 01 LSR 10 ASR 11 ROR <Rs> Is the third general-purpose source register holding a shift amount in its bottom 8 bits, encoded in the "Rs" field. if ConditionPassed() then EncodingSpecificOperations(); shift_n = UInt(R[s]<7:0>); shifted = Shift(R[m], shift_t, shift_n, PSTATE.C); (result, nzcv) = AddWithCarry(R[n], shifted, '0'); R[d] = result; if setflags then PSTATE.<N,Z,C,V> = nzcv;