ADD, ADDS (register) Add (register) Add (register) adds a register value and an optionally-shifted register value, and writes the result to the destination register. If the destination register is not the PC, the ADDS variant of the instruction updates the condition flags based on the result. The field descriptions for <Rd> identify the encodings where the PC is permitted as the destination register. If the destination register is the PC: The ADD variant of the instruction is an interworking branch, see Pseudocode description of operations on the AArch32 general-purpose registers and the PC. The ADDS variant of the instruction performs an exception return without the use of the stack. Arm deprecates use of this instruction. However, in this case:The PE branches to the address written to the PC, and restores PSTATE from SPSR_<current_mode>.The PE checks SPSR_<current_mode> for an illegal return event. See Illegal return events from AArch32 state.The instruction is undefined in Hyp mode.The instruction is constrained unpredictable in User mode and System mode. For more information about the constrained unpredictable behavior, see Architectural Constraints on UNPREDICTABLE behaviors. Inside an IT block, if ADD<c> <Rd>, <Rn>, <Rd> cannot be assembled using encoding T1, it is assembled using encoding T2 as though ADD<c> <Rd>, <Rn> had been written. To prevent this happening, use the .W qualifier. If CPSR.DIT is 1 and this instruction does not use R15 as either its source or destination: The execution time of this instruction is independent of:The values of the data supplied in any of its registers.The values of the NZCV flags. The response of this instruction to asynchronous exceptions does not vary based on:The values of the data supplied in any of its registers.The values of the NZCV flags. It has encodings from the following instruction sets: A32 ( A1 ) and T32 ( T1 , T2 and T3 ) . != 1111 0 0 0 0 1 0 0 != 1101 0 0 0 0 0 0 0 1 1 ADD{<c>}{<q>} {<Rd>,} <Rn>, <Rm>, RRX 0 Z Z Z Z Z N N ADD{<c>}{<q>} {<Rd>,} <Rn>, <Rm> {, <shift> #<amount>} 1 0 0 0 0 0 1 1 ADDS{<c>}{<q>} {<Rd>,} <Rn>, <Rm>, RRX 1 Z Z Z Z Z N N ADDS{<c>}{<q>} {<Rd>,} <Rn>, <Rm> {, <shift> #<amount>} if Rn == '1101' then SEE "ADD (SP plus register)"; d = UInt(Rd); n = UInt(Rn); m = UInt(Rm); setflags = (S == '1'); (shift_t, shift_n) = DecodeImmShift(stype, imm5); 0 0 0 1 1 0 0 ADD<c>{<q>} <Rd>, <Rn>, <Rm> ADDS{<q>} {<Rd>,} <Rn>, <Rm> d = UInt(Rd); n = UInt(Rn); m = UInt(Rm); setflags = !InITBlock(); (shift_t, shift_n) = (SRType_LSL, 0); 0 1 0 0 0 1 0 0 != 1101 N N Z N ADD<c>{<q>} <Rdn>, <Rm> ADD{<c>}{<q>} {<Rdn>,} <Rdn>, <Rm> if (DN:Rdn) == '1101' || Rm == '1101' then SEE "ADD (SP plus register)"; d = UInt(DN:Rdn); n = d; m = UInt(Rm); setflags = FALSE; (shift_t, shift_n) = (SRType_LSL, 0); if n == 15 && m == 15 then UNPREDICTABLE; if d == 15 && InITBlock() && !LastInITBlock() then UNPREDICTABLE; 1 1 1 0 1 0 1 1 0 0 0 != 1101 (0) 0 0 0 0 0 0 1 1 ADD{<c>}{<q>} {<Rd>,} <Rn>, <Rm>, RRX 0 Z Z Z Z Z N N ADD<c>.W {<Rd>,} <Rn>, <Rm> ADD{<c>}.W {<Rd>,} <Rn>, <Rm> ADD{<c>}{<q>} {<Rd>,} <Rn>, <Rm> {, <shift> #<amount>} 1 0 0 0 N N N N 0 0 1 1 ADDS{<c>}{<q>} {<Rd>,} <Rn>, <Rm>, RRX 1 Z Z Z Z Z N N N N N N ADDS.W {<Rd>,} <Rn>, <Rm> ADDS{<c>}{<q>} {<Rd>,} <Rn>, <Rm> {, <shift> #<amount>} if Rd == '1111' && S == '1' then SEE "CMN (register)"; if Rn == '1101' then SEE "ADD (SP plus register)"; d = UInt(Rd); n = UInt(Rn); m = UInt(Rm); setflags = (S == '1'); (shift_t, shift_n) = DecodeImmShift(stype, imm3:imm2); if (d == 15 && !setflags) || n == 15 || m == 15 then UNPREDICTABLE; // Armv8-A removes UNPREDICTABLE for R13 <c> See Standard assembler syntax fields. <q> See Standard assembler syntax fields. <Rdn> Is the general-purpose source and destination register, encoded in the "DN:Rdn" field. If the PC is used, the instruction is a branch to the address calculated by the operation. This is a simple branch, see Pseudocode description of operations on the AArch32 general-purpose registers and the PC. The assembler language allows <Rdn> to be specified once or twice in the assembler syntax. When used inside an IT block, and <Rdn> and <Rm> are in the range R0 to R7, <Rdn> must be specified once so that encoding T2 is preferred to encoding T1. In all other cases there is no difference in behavior when <Rdn> is specified once or twice. <Rd> For encoding A1: is the general-purpose destination register, encoded in the "Rd" field. If omitted, this register is the same as <Rn>. If the PC is used: For the ADD variant, the instruction is a branch to the address calculated by the operation. This is an interworking branch, see Pseudocode description of operations on the AArch32 general-purpose registers and the PC. For the ADDS variant, the instruction performs an exception return, that restores PSTATE from SPSR_<current_mode>. Arm deprecates use of this instruction. <Rd> For encoding T1: is the general-purpose destination register, encoded in the "Rd" field. When used inside an IT block, <Rd> must be specified. When used outside an IT block, <Rd> is optional, and: If omitted, this register is the same as <Rn>. If present, encoding T1 is preferred to encoding T2. <Rd> For encoding T3: is the general-purpose destination register, encoded in the "Rd" field. If omitted, this register is the same as <Rn>. <Rn> For encoding A1: is the first general-purpose source register, encoded in the "Rn" field. The PC can be used. If the SP is used, see ADD (SP plus register). <Rn> For encoding T1: is the first general-purpose source register, encoded in the "Rn" field. <Rn> For encoding T3: is the first general-purpose source register, encoded in the "Rn" field. If the SP is used, see ADD (SP plus register). <Rm> For encoding A1: is the second general-purpose source register, encoded in the "Rm" field. The PC can be used, but this is deprecated. <Rm> For encoding T1 and T3: is the second general-purpose source register, encoded in the "Rm" field. <Rm> For encoding T2: is the second general-purpose source register, encoded in the "Rm" field. The PC can be used. <shift> Is the type of shift to be applied to the second source register, stype <shift> 00 LSL 01 LSR 10 ASR 11 ROR <amount> For encoding A1: is the shift amount, in the range 1 to 31 (when <shift> = LSL or ROR) or 1 to 32 (when <shift> = LSR or ASR) encoded in the "imm5" field as <amount> modulo 32. <amount> For encoding T3: is the shift amount, in the range 1 to 31 (when <shift> = LSL or ROR) or 1 to 32 (when <shift> = LSR or ASR), encoded in the "imm3:imm2" field as <amount> modulo 32. if ConditionPassed() then EncodingSpecificOperations(); shifted = Shift(R[m], shift_t, shift_n, PSTATE.C); (result, nzcv) = AddWithCarry(R[n], shifted, '0'); if d == 15 then if setflags then ALUExceptionReturn(result); else ALUWritePC(result); else R[d] = result; if setflags then PSTATE.<N,Z,C,V> = nzcv;