Data-processing and miscellaneous instructions

!= 1111 00x != 1111 00

Extra load/store

0 1 != 00 1 != 1111 000 1 != 00 1

Load/Store Dual, Half, Signed Byte (register)

0

Load/Store Dual, Half, Signed Byte (immediate, literal)

1

Multiply and Accumulate

0 0xxxx 1 00 1

Synchronization primitives and Load-Acquire/Store-Release

0 1xxxx 1 00 1 != 1111 0001 11 1001

UNALLOCATED

0

Load/Store Exclusive and Load-Acquire/Store-Release

1

Miscellaneous

0 10xx0 0 != 1111 00010 0 0

UNALLOCATED

00 001

UNALLOCATED

00 010

UNALLOCATED

00 011

UNALLOCATED

00 110

Branch and Exchange (register)

01 001

Branch and Exchange to Jazelle (register)

01 010

Branch with Link and Exchange (register)

01 011

UNALLOCATED

01 110

UNALLOCATED

10 001

UNALLOCATED

10 010

UNALLOCATED

10 011

UNALLOCATED

10 110

Count Leading Zeros

11 001

UNALLOCATED

11 010

UNALLOCATED

11 011

Exception Return

11 110

Exception Generation

111

Move special register (register)

000

Cyclic Redundancy Check

100

Integer Saturating Arithmetic

101

Halfword Multiply and Accumulate

0 10xx0 1 0

Data-processing register (immediate shift)

0 != 10xx0 0 != 1111 000 0

Integer Data Processing (three register, immediate shift)

0x

Integer Test and Compare (two register, immediate shift)

10 1

Logical Arithmetic (three register, immediate shift)

11

Data-processing register (register shift)

0 != 10xx0 0 1 != 1111 000 0 1

Integer Data Processing (three register, register shift)

0x

Integer Test and Compare (two register, register shift)

10 1

Logical Arithmetic (three register, register shift)

11

Data-processing immediate

1 != 1111 001

Integer Data Processing (two register and immediate)

0x

Move Halfword (immediate)

10 00

Move Special Register and Hints (immediate)

10 10

Integer Test and Compare (one register and immediate)

10 x1

Logical Arithmetic (two register and immediate)

11

Load/Store Word, Unsigned Byte (immediate, literal)

!= 1111 010

Load/Store Word, Unsigned Byte (register)

!= 1111 011 0

Media instructions

!= 1111 011 1 != 1111 011 1

Parallel Arithmetic

00xxx

Select Bytes

01000 101

UNALLOCATED

01000 001

Pack Halfword

01000 xx0

UNALLOCATED

01001 x01

UNALLOCATED

01001 xx0

UNALLOCATED

0110x x01

UNALLOCATED

0110x xx0

Saturate 16-bit

01x10 001

UNALLOCATED

01x10 101

Reverse Bit/Byte

01x11 x01

Saturate 32-bit

01x1x xx0

UNALLOCATED

01xxx 111

Extend and Add

01xxx 011

Signed multiply, Divide

10xxx

Unsigned Sum of Absolute Differences

11000 000

UNALLOCATED

11000 100

UNALLOCATED

11001 x00

UNALLOCATED

1101x x00

UNALLOCATED

110xx 111

UNALLOCATED

1110x 111

Bitfield Insert

1110x x00

UNALLOCATED

11110 111

Permanently UNDEFINED

11111 111

UNALLOCATED

1111x x00

UNALLOCATED

11x0x x10

Bitfield Extract

11x1x x10

UNALLOCATED

11xxx 011

UNALLOCATED

11xxx x01

Branch, branch with link, and block data transfer

10x 10

Exception Save/Restore

1111 0

Load/Store Multiple

!= 1111 0

Branch (immediate)

1

System register access, Advanced SIMD, floating-point, and Supervisor call

11x 11

UNALLOCATED

0x 0x

UNALLOCATED

10 0x

Supervisor call

11 1111

UNALLOCATED

1111

Supervisor Call

!= 1111

Unconditional Advanced SIMD and floating-point instructions

1111 != 11 1x 111111 1

Advanced SIMD three registers of the same length extension

0xx 0x

Floating-point conditional select

100 0 != 00 0 0

Floating-point minNum/maxNum

101 00xxxx 0 != 00 0

Floating-point extraction and insertion

101 110000 0 != 00 1 0

Floating-point directed convert to integer

101 111xxx 0 != 00 1 0

Advanced SIMD and floating-point multiply with accumulate

10x 0 00

Advanced SIMD and floating-point dot product

10x 1 0x

Advanced SIMD and System register load/store and 64-bit move

!= 1111 0x 1x != 1111 110 1

Advanced SIMD and floating-point 64-bit move

00x0 0x

System register 64-bit move

00x0 11

Advanced SIMD and floating-point load/store

!= 00x0 0x

System register load/store

!= 00x0 11

UNALLOCATED

10

Advanced SIMD and System register 32-bit move

!= 1111 10 1x 1 != 1111 1110 1 1

UNALLOCATED

000 000

Floating-point 16-bit move

000 001

Floating-point 32-bit move

000 010

UNALLOCATED

001 010

UNALLOCATED

01x 010

UNALLOCATED

10x 010

UNALLOCATED

110 010

Floating-point move special register

111 010

Advanced SIMD 8/16/32-bit element move/duplicate

011

UNALLOCATED

10x

System register 32-bit move

11x

Floating-point data-processing

!= 1111 10 10 0 != 1111 1110 10 0

Floating-point data-processing (two registers)

1x11 1

Floating-point move immediate

1x11 0

Floating-point data-processing (three registers)

!= 1x11

UNALLOCATED

!= 1111 10 11 0

Unconditional instructions

1111 0xx 11110

Miscellaneous

00x 1111000

UNALLOCATED

0xxxx

Change Process State

10000 xx0x

UNALLOCATED

10001 1000

UNALLOCATED

10001 x100

UNALLOCATED

10001 xx01

SETPAN

10001 0000

UNALLOCATED

1000x 0111

UNPREDICTABLE

10010 0111

UNALLOCATED

10011 0111

UNALLOCATED

1001x xx0x

UNALLOCATED

100xx 0011

UNALLOCATED

100xx 0x10

UNALLOCATED

100xx 1x1x

UNALLOCATED

101xx

UNALLOCATED

11xxx

Advanced SIMD data-processing

01x 1111001

Advanced SIMD three registers of the same length

0

Advanced SIMD two registers, or three registers of different lengths

1 0 1111001 1 0

Advanced SIMD vector extract

0 11

Advanced SIMD two registers misc

1 11 0x

Advanced SIMD table permute

1 11 10

Advanced SIMD duplicate (scalar)

1 11 11

Advanced SIMD three registers of different lengths

!= 11 0

Advanced SIMD two registers and a scalar

!= 11 1

Advanced SIMD shifts and immediate generation

1 1 1111001 1 1

Advanced SIMD one register and modified immediate

000xxxxxxxxxxx0

Advanced SIMD two registers and shift amount

!= 000xxxxxxxxxxx0

Memory hints and barriers

1xx 1 111101 1

UNPREDICTABLE

00xx1

UNPREDICTABLE

01001

Barriers

01011

UNPREDICTABLE

011x1

Preload (immediate)

0xxx0

Preload (register)

1xxx0 0

UNPREDICTABLE

1xxx1 0

UNALLOCATED

1xxxx 1

Advanced SIMD element or structure load/store

100 0 11110100 0

Advanced SIMD load/store multiple structures

0

Advanced SIMD load single structure to all lanes

1 11

Advanced SIMD load/store single structure to one lane

1 != 11

UNALLOCATED

101 0

UNALLOCATED

11x 0 Instruction bits Encoding Group 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 != 1111 0 0 Data-processing and miscellaneous instructions != 1111 0 1 0 Load/store word and unsigned byte (immediate) != 1111 0 1 1 0 Load/store word and unsigned byte (register) != 1111 0 1 1 1 Media instructions 1 0 Branch, branch with link, and block data transfer 1 1 System register access, Advanced SIMD, floating-point, and Supervisor call 1 1 1 1 0 Unconditional instructions != 1111 0 0 0 != 10xx0 0 Data-processing and miscellaneous instructions / Data-processing register (immediate shift) != 1111 0 0 0 != 10xx0 0 1 Data-processing and miscellaneous instructions / Data-processing register (register shift) != 1111 0 0 0 1 0 0 0 Data-processing and miscellaneous instructions / Miscellaneous != 1111 0 0 0 1 0 0 1 0 Data-processing and miscellaneous instructions / Halfword multiply and multiply accumulate != 1111 0 0 0 0 1 0 0 1 Data-processing and miscellaneous instructions / Multiply and multiply accumulate != 1111 0 0 0 1 1 0 0 1 Data-processing and miscellaneous instructions / Synchronization primitives and Load-Acquire/Store-Release != 1111 0 0 0 1 != 00 1 Data-processing and miscellaneous instructions / Extra load/store != 1111 0 0 1 Data-processing and miscellaneous instructions / Data-processing immediate 1 1 0 0 System register access, Advanced SIMD, floating-point, and Supervisor call / UNALLOCATED 1 1 1 0 0 System register access, Advanced SIMD, floating-point, and Supervisor call / UNALLOCATED != 1111 1 1 0 1 System register access, Advanced SIMD, floating-point, and Supervisor call / Advanced SIMD and System register load/store and 64-bit move != 1111 1 1 1 0 1 0 0 System register access, Advanced SIMD, floating-point, and Supervisor call / Floating-point data-processing != 1111 1 1 1 0 1 1 0 System register access, Advanced SIMD, floating-point, and Supervisor call / UNALLOCATED != 1111 1 1 1 0 1 1 System register access, Advanced SIMD, floating-point, and Supervisor call / Advanced SIMD and System register 32-bit move 1 1 1 1 1 1 != 11 1 System register access, Advanced SIMD, floating-point, and Supervisor call / Unconditional Advanced SIMD and floating-point instructions 1 1 1 1 System register access, Advanced SIMD, floating-point, and Supervisor call / Supervisor call 1 1 1 1 0 0 0 Unconditional instructions / Miscellaneous 1 1 1 1 0 0 1 Unconditional instructions / Advanced SIMD data-processing 1 1 1 1 0 1 1 Unconditional instructions / Memory hints and barriers 1 1 1 1 0 1 0 0 0 Unconditional instructions / Advanced SIMD element or structure load/store 1 1 1 1 0 1 0 1 0 Unconditional instructions / UNALLOCATED 1 1 1 1 0 1 1 0 Unconditional instructions / UNALLOCATED 1 1 1 1 0 0 1 0 Unconditional instructions / Advanced SIMD data-processing / Advanced SIMD three registers of the same length 1 1 1 1 0 0 1 1 0 Unconditional instructions / Advanced SIMD data-processing / Advanced SIMD two registers, or three registers of different lengths 1 1 1 1 0 0 1 1 1 Unconditional instructions / Advanced SIMD data-processing / Advanced SIMD shifts and immediate generation Instruction bits Instruction class 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 != 1111 0 1 0 Load/Store Word, Unsigned Byte (immediate, literal) != 1111 0 1 1 0 Load/Store Word, Unsigned Byte (register) != 1111 0 1 1 0 0 1 Parallel Arithmetic != 1111 0 1 1 0 1 0 1 1 1 Extend and Add != 1111 0 1 1 0 1 1 1 1 1 UNALLOCATED != 1111 0 1 1 0 1 1 0 1 Saturate 32-bit != 1111 0 1 1 0 1 1 0 0 0 1 1 Saturate 16-bit != 1111 0 1 1 0 1 1 0 1 0 1 1 UNALLOCATED != 1111 0 1 1 0 1 1 1 0 1 1 Reverse Bit/Byte != 1111 0 1 1 0 1 0 0 0 0 1 Pack Halfword != 1111 0 1 1 0 1 0 0 0 0 0 1 1 UNALLOCATED != 1111 0 1 1 0 1 0 0 0 1 0 1 1 Select Bytes != 1111 0 1 1 0 1 0 0 1 0 1 UNALLOCATED != 1111 0 1 1 0 1 0 0 1 0 1 1 UNALLOCATED != 1111 0 1 1 0 1 1 0 0 1 UNALLOCATED != 1111 0 1 1 0 1 1 0 0 1 1 UNALLOCATED != 1111 0 1 1 1 0 1 Signed multiply, Divide != 1111 0 1 1 1 1 0 1 1 UNALLOCATED != 1111 0 1 1 1 1 0 1 1 1 UNALLOCATED != 1111 0 1 1 1 1 0 1 0 1 UNALLOCATED != 1111 0 1 1 1 1 1 1 0 1 Bitfield Extract != 1111 0 1 1 1 1 0 1 1 1 1 UNALLOCATED != 1111 0 1 1 1 1 0 0 0 0 0 0 1 Unsigned Sum of Absolute Differences != 1111 0 1 1 1 1 0 0 0 1 0 0 1 UNALLOCATED != 1111 0 1 1 1 1 0 0 1 0 0 1 UNALLOCATED != 1111 0 1 1 1 1 0 1 0 0 1 UNALLOCATED != 1111 0 1 1 1 1 1 0 0 0 1 Bitfield Insert != 1111 0 1 1 1 1 1 0 1 1 1 1 UNALLOCATED != 1111 0 1 1 1 1 1 1 0 0 1 UNALLOCATED != 1111 0 1 1 1 1 1 1 0 1 1 1 1 UNALLOCATED != 1111 0 1 1 1 1 1 1 1 1 1 1 1 Permanently UNDEFINED 1 0 1 Branch (immediate) 1 1 1 1 1 0 0 Exception Save/Restore != 1111 1 0 0 Load/Store Multiple != 1111 0 0 0 0 0 Integer Data Processing (three register, immediate shift) != 1111 0 0 0 1 0 1 0 Integer Test and Compare (two register, immediate shift) != 1111 0 0 0 1 1 0 Logical Arithmetic (three register, immediate shift) != 1111 0 0 0 0 0 1 Integer Data Processing (three register, register shift) != 1111 0 0 0 1 0 1 0 1 Integer Test and Compare (two register, register shift) != 1111 0 0 0 1 1 0 1 Logical Arithmetic (three register, register shift) != 1111 0 0 0 1 0 0 0 0 0 0 Move special register (register) != 1111 0 0 0 1 0 0 0 1 0 0 Cyclic Redundancy Check != 1111 0 0 0 1 0 0 0 1 0 1 Integer Saturating Arithmetic != 1111 0 0 0 1 0 0 0 1 1 1 Exception Generation != 1111 0 0 0 1 0 0 0 0 0 0 0 1 UNALLOCATED != 1111 0 0 0 1 0 0 0 0 0 0 1 0 UNALLOCATED != 1111 0 0 0 1 0 0 0 0 0 0 1 1 UNALLOCATED != 1111 0 0 0 1 0 0 0 0 0 1 1 0 UNALLOCATED != 1111 0 0 0 1 0 0 1 0 0 0 0 1 Branch and Exchange (register) != 1111 0 0 0 1 0 0 1 0 0 0 1 0 Branch and Exchange to Jazelle (register) != 1111 0 0 0 1 0 0 1 0 0 0 1 1 Branch with Link and Exchange (register) != 1111 0 0 0 1 0 0 1 0 0 1 1 0 UNALLOCATED != 1111 0 0 0 1 0 1 0 0 0 0 0 1 UNALLOCATED != 1111 0 0 0 1 0 1 0 0 0 0 1 0 UNALLOCATED != 1111 0 0 0 1 0 1 0 0 0 0 1 1 UNALLOCATED != 1111 0 0 0 1 0 1 0 0 0 1 1 0 UNALLOCATED != 1111 0 0 0 1 0 1 1 0 0 0 0 1 Count Leading Zeros != 1111 0 0 0 1 0 1 1 0 0 0 1 0 UNALLOCATED != 1111 0 0 0 1 0 1 1 0 0 0 1 1 UNALLOCATED != 1111 0 0 0 1 0 1 1 0 0 1 1 0 Exception Return != 1111 0 0 0 1 0 0 1 0 Halfword Multiply and Accumulate != 1111 0 0 0 0 1 0 0 1 Multiply and Accumulate != 1111 0 0 0 1 0 1 0 0 1 UNALLOCATED != 1111 0 0 0 1 1 1 0 0 1 Load/Store Exclusive and Load-Acquire/Store-Release != 1111 0 0 0 0 1 != 00 1 Load/Store Dual, Half, Signed Byte (register) != 1111 0 0 0 1 1 != 00 1 Load/Store Dual, Half, Signed Byte (immediate, literal) != 1111 0 0 1 0 Integer Data Processing (two register and immediate) != 1111 0 0 1 1 0 1 Integer Test and Compare (one register and immediate) != 1111 0 0 1 1 0 0 0 Move Halfword (immediate) != 1111 0 0 1 1 0 1 0 Move Special Register and Hints (immediate) != 1111 0 0 1 1 1 Logical Arithmetic (two register and immediate) 1 1 0 0 UNALLOCATED 1 1 1 0 0 UNALLOCATED != 1111 1 1 0 1 1 0 UNALLOCATED != 1111 1 1 0 0 0 0 1 0 Advanced SIMD and floating-point 64-bit move != 1111 1 1 0 0 0 0 1 1 1 System register 64-bit move != 1111 1 1 0 != 00x0 1 0 Advanced SIMD and floating-point load/store != 1111 1 1 0 != 00x0 1 1 1 System register load/store != 1111 1 1 1 0 1 1 1 1 0 0 0 Floating-point move immediate != 1111 1 1 1 0 1 1 1 1 0 1 0 Floating-point data-processing (two registers) != 1111 1 1 1 0 != 1x11 1 0 0 Floating-point data-processing (three registers) != 1111 1 1 1 0 1 0 1 1 1 Advanced SIMD 8/16/32-bit element move/duplicate != 1111 1 1 1 0 1 1 0 1 UNALLOCATED != 1111 1 1 1 0 1 1 1 1 System register 32-bit move != 1111 1 1 1 0 0 0 0 1 0 0 0 1 UNALLOCATED != 1111 1 1 1 0 0 0 0 1 0 0 1 1 Floating-point 16-bit move != 1111 1 1 1 0 0 0 0 1 0 1 0 1 Floating-point 32-bit move != 1111 1 1 1 0 0 0 1 1 0 1 0 1 UNALLOCATED != 1111 1 1 1 0 0 1 1 0 1 0 1 UNALLOCATED != 1111 1 1 1 0 1 0 1 0 1 0 1 UNALLOCATED != 1111 1 1 1 0 1 1 0 1 0 1 0 1 UNALLOCATED != 1111 1 1 1 0 1 1 1 1 0 1 0 1 Floating-point move special register 1 1 1 1 1 1 0 1 0 Advanced SIMD three registers of the same length extension 1 1 1 1 1 1 1 0 1 0 0 0 Advanced SIMD and floating-point multiply with accumulate 1 1 1 1 1 1 1 0 1 1 0 Advanced SIMD and floating-point dot product 1 1 1 1 1 1 1 0 0 1 0 != 00 0 0 Floating-point conditional select 1 1 1 1 1 1 1 0 1 0 0 1 0 != 00 0 Floating-point minNum/maxNum 1 1 1 1 1 1 1 0 1 1 1 0 0 0 0 1 0 != 00 1 0 Floating-point extraction and insertion 1 1 1 1 1 1 1 0 1 1 1 1 1 0 != 00 1 0 Floating-point directed convert to integer 1 1 1 1 1 1 1 1 UNALLOCATED != 1111 1 1 1 1 Supervisor Call 1 1 1 1 0 0 0 0 UNALLOCATED 1 1 1 1 0 0 0 1 0 0 0 1 0 UNALLOCATED 1 1 1 1 0 0 0 1 0 0 0 0 1 1 UNALLOCATED 1 1 1 1 0 0 0 1 0 0 1 1 UNALLOCATED 1 1 1 1 0 0 0 1 0 0 0 0 1 1 1 UNALLOCATED 1 1 1 1 0 0 0 1 0 0 0 0 0 Change Process State 1 1 1 1 0 0 0 1 0 0 0 1 0 1 UNALLOCATED 1 1 1 1 0 0 0 1 0 0 0 1 1 0 0 UNALLOCATED 1 1 1 1 0 0 0 1 0 0 0 1 0 0 0 0 SETPAN 1 1 1 1 0 0 0 1 0 0 0 1 1 0 0 0 UNALLOCATED 1 1 1 1 0 0 0 1 0 0 1 0 UNALLOCATED 1 1 1 1 0 0 0 1 0 0 1 0 0 1 1 1 UNPREDICTABLE 1 1 1 1 0 0 0 1 0 0 1 1 0 1 1 1 UNALLOCATED 1 1 1 1 0 0 0 1 0 1 UNALLOCATED 1 1 1 1 0 0 0 1 1 UNALLOCATED 1 1 1 1 0 1 0 0 1 Preload (immediate) 1 1 1 1 0 1 0 0 1 1 UNPREDICTABLE 1 1 1 1 0 1 0 1 0 0 1 1 UNPREDICTABLE 1 1 1 1 0 1 0 1 0 1 1 1 Barriers 1 1 1 1 0 1 0 1 1 1 1 UNPREDICTABLE 1 1 1 1 0 1 1 1 1 UNALLOCATED 1 1 1 1 0 1 1 0 1 0 Preload (register) 1 1 1 1 0 1 1 1 1 0 UNPREDICTABLE 1 1 1 1 0 1 0 0 0 0 Advanced SIMD load/store multiple structures 1 1 1 1 0 1 0 0 1 0 1 1 Advanced SIMD load single structure to all lanes 1 1 1 1 0 1 0 0 1 0 != 11 Advanced SIMD load/store single structure to one lane 1 1 1 1 0 1 1 0 UNALLOCATED 1 1 1 1 0 0 1 0 Advanced SIMD three registers of the same length 1 1 1 1 0 0 1 1 != 11 0 0 Advanced SIMD three registers of different lengths 1 1 1 1 0 0 1 1 != 11 1 0 Advanced SIMD two registers and a scalar 1 1 1 1 0 0 1 0 1 1 1 0 Advanced SIMD vector extract 1 1 1 1 0 0 1 1 1 1 1 0 0 Advanced SIMD two registers misc 1 1 1 1 0 0 1 1 1 1 1 1 0 0 Advanced SIMD table permute 1 1 1 1 0 0 1 1 1 1 1 1 1 0 Advanced SIMD duplicate (scalar) 1 1 1 1 0 0 1 1 0 0 0 0 1 Advanced SIMD one register and modified immediate 1 1 1 1 0 0 1 1 != 000xxxxxxxxxxx0 1 Advanced SIMD two registers and shift amount Data-processing register (register shift) != 1111 0 0 0 0 0 1 Decode fields Instruction page Encoding opc 000 AND, ANDS (register-shifted register) Flag setting 001 EOR, EORS (register-shifted register) Flag setting 010 SUB, SUBS (register-shifted register) Flag setting 011 RSB, RSBS (register-shifted register) Flag setting 100 ADD, ADDS (register-shifted register) Flag setting 101 ADC, ADCS (register-shifted register) Flag setting 110 SBC, SBCS (register-shifted register) Flag setting 111 RSC, RSCS (register-shifted register) Flag setting != 1111 0 0 0 1 0 1 (0) (0) (0) (0) 0 1 Decode fields Instruction page Encoding opc 00 TST (register-shifted register) 01 TEQ (register-shifted register) 10 CMP (register-shifted register) 11 CMN (register-shifted register) != 1111 0 0 0 1 1 0 1 Decode fields Instruction page Encoding opc 00 ORR, ORRS (register-shifted register) Flag setting 01 MOV, MOVS (register-shifted register) A1, Flag setting 10 BIC, BICS (register-shifted register) Flag setting 11 MVN, MVNS (register-shifted register) Flag setting Data-processing register (immediate shift) != 1111 0 0 0 0 0 Decode fields Instruction page Encoding opc S Rn imm5:stype 000 != 0000011 AND, ANDS (register) A1, ANDS, shift or rotate by value 000 0000011 AND, ANDS (register) A1, ANDS, rotate right with extend 001 != 0000011 EOR, EORS (register) A1, EORS, shift or rotate by value 001 0000011 EOR, EORS (register) A1, EORS, rotate right with extend 010 0 != 1101 != 0000011 SUB, SUBS (register) A1, SUB, shift or rotate by value 010 0 != 1101 0000011 SUB, SUBS (register) A1, SUB, rotate right with extend 010 0 1101 != 0000011 SUB, SUBS (SP minus register) A1, SUB, shift or rotate by value 010 0 1101 0000011 SUB, SUBS (SP minus register) A1, SUB, rotate right with extend 010 1 != 1101 != 0000011 SUB, SUBS (register) A1, SUBS, shift or rotate by value 010 1 != 1101 0000011 SUB, SUBS (register) A1, SUBS, rotate right with extend 010 1 1101 != 0000011 SUB, SUBS (SP minus register) A1, SUBS, shift or rotate by value 010 1 1101 0000011 SUB, SUBS (SP minus register) A1, SUBS, rotate right with extend 011 != 0000011 RSB, RSBS (register) A1, RSBS, shift or rotate by value 011 0000011 RSB, RSBS (register) A1, RSBS, rotate right with extend 100 0 != 1101 != 0000011 ADD, ADDS (register) A1, ADD, shift or rotate by value 100 0 != 1101 0000011 ADD, ADDS (register) A1, ADD, rotate right with extend 100 0 1101 != 0000011 ADD, ADDS (SP plus register) A1, ADD, shift or rotate by value 100 0 1101 0000011 ADD, ADDS (SP plus register) A1, ADD, rotate right with extend 100 1 != 1101 != 0000011 ADD, ADDS (register) A1, ADDS, shift or rotate by value 100 1 != 1101 0000011 ADD, ADDS (register) A1, ADDS, rotate right with extend 100 1 1101 != 0000011 ADD, ADDS (SP plus register) A1, ADDS, shift or rotate by value 100 1 1101 0000011 ADD, ADDS (SP plus register) A1, ADDS, rotate right with extend 101 != 0000011 ADC, ADCS (register) A1, ADCS, shift or rotate by value 101 0000011 ADC, ADCS (register) A1, ADCS, rotate right with extend 110 != 0000011 SBC, SBCS (register) A1, SBCS, shift or rotate by value 110 0000011 SBC, SBCS (register) A1, SBCS, rotate right with extend 111 != 0000011 RSC, RSCS (register) RSCS, shift or rotate by value 111 0000011 RSC, RSCS (register) RSCS, rotate right with extend != 1111 0 0 0 1 0 1 (0) (0) (0) (0) 0 Decode fields Instruction page Encoding opc imm5:stype 00 != 0000011 TST (register) A1, Shift or rotate by value 00 0000011 TST (register) A1, Rotate right with extend 01 != 0000011 TEQ (register) A1, Shift or rotate by value 01 0000011 TEQ (register) A1, Rotate right with extend 10 != 0000011 CMP (register) A1, Shift or rotate by value 10 0000011 CMP (register) A1, Rotate right with extend 11 != 0000011 CMN (register) A1, Shift or rotate by value 11 0000011 CMN (register) A1, Rotate right with extend != 1111 0 0 0 1 1 0 Decode fields Instruction page Encoding opc imm5:stype 00 != 0000011 ORR, ORRS (register) A1, ORRS, shift or rotate by value 00 0000011 ORR, ORRS (register) A1, ORRS, rotate right with extend 01 != 0000011 MOV, MOVS (register) A1, MOVS, shift or rotate by value 01 0000011 MOV, MOVS (register) A1, MOVS, rotate right with extend 10 != 0000011 BIC, BICS (register) A1, BICS, shift or rotate by value 10 0000011 BIC, BICS (register) A1, BICS, rotate right with extend 11 != 0000011 MVN, MVNS (register) A1, MVNS, shift or rotate by value 11 0000011 MVN, MVNS (register) A1, MVNS, rotate right with extend Miscellaneous != 1111 0 0 0 1 0 0 1 0 (1) (1) (1) (1) (1) (1) (1) (1) (1) (1) (1) (1) 0 0 0 1 Instruction page Encoding BX A1 != 1111 0 0 0 1 0 0 1 0 (1) (1) (1) (1) (1) (1) (1) (1) (1) (1) (1) (1) 0 0 1 0 Instruction page Encoding BXJ A1 != 1111 0 0 0 1 0 0 1 0 (1) (1) (1) (1) (1) (1) (1) (1) (1) (1) (1) (1) 0 0 1 1 Instruction page Encoding BLX (register) A1 != 1111 0 0 0 1 0 1 1 0 (1) (1) (1) (1) (1) (1) (1) (1) 0 0 0 1 Instruction page Encoding CLZ A1 != 1111 0 0 0 1 0 0 (0) (0) (0) 0 1 0 0 Decode fields Instruction page Encoding sz C 00 0 CRC32 A1, CRC32B 00 1 CRC32C A1, CRC32CB 01 0 CRC32 A1, CRC32H 01 1 CRC32C A1, CRC32CH 10 0 CRC32 A1, CRC32W 10 1 CRC32C A1, CRC32CW 11 UNPREDICTABLE != 1111 0 0 0 1 0 0 0 1 1 1 Decode fields Instruction page Encoding opc 00 HLT A1 01 BKPT A1 10 HVC A1 11 SMC A1 != 1111 0 0 0 1 0 1 1 0 (0) (0) (0) (0) (0) (0) (0) (0) (0) (0) (0) (0) 0 1 1 0 (1) (1) (1) (0) Instruction page Encoding ERET A1 != 1111 0 0 0 1 0 0 (0) (0) (0) (0) 0 1 0 1 Decode fields Instruction page Encoding opc 00 QADD A1 01 QSUB A1 10 QDADD A1 11 QDSUB A1 != 1111 0 0 0 1 0 0 (0) (0) 0 0 0 0 Decode fields Instruction page Encoding opc B x0 0 MRS A1 x0 1 MRS (Banked register) A1 x1 0 MSR (register) A1 x1 1 MSR (Banked register) A1 Halfword multiply and multiply accumulate != 1111 0 0 0 1 0 0 1 0 Decode fields Instruction page Encoding opc M N 00 SMLABB, SMLABT, SMLATB, SMLATT A1, SMLATT 01 0 0 SMLAWB, SMLAWT A1, SMLAWB 01 0 1 SMULWB, SMULWT A1, SMULWB 01 1 0 SMLAWB, SMLAWT A1, SMLAWT 01 1 1 SMULWB, SMULWT A1, SMULWT 10 SMLALBB, SMLALBT, SMLALTB, SMLALTT A1, SMLALTT 11 SMULBB, SMULBT, SMULTB, SMULTT A1, SMULTT Multiply and multiply accumulate != 1111 0 0 0 0 1 0 0 1 Decode fields Instruction page Encoding opc S 000 MUL, MULS A1, Flag setting 001 MLA, MLAS A1, Flag setting 010 0 UMAAL A1 010 1 UNALLOCATED 011 0 MLS A1 011 1 UNALLOCATED 100 UMULL, UMULLS A1, Flag setting 101 UMLAL, UMLALS A1, Flag setting 110 SMULL, SMULLS A1, Flag setting 111 SMLAL, SMLALS A1, Flag setting Synchronization primitives and Load-Acquire/Store-Release != 1111 0 0 0 1 1 (1) (1) 1 0 0 1 Decode fields Instruction page Encoding size L ex ord 00 0 0 0 STL A1 00 0 0 1 UNALLOCATED 00 0 1 0 STLEX A1 00 0 1 1 STREX A1 00 1 0 0 LDA A1 00 1 0 1 UNALLOCATED 00 1 1 0 LDAEX A1 00 1 1 1 LDREX A1 01 0 0 UNALLOCATED 01 0 1 0 STLEXD A1 01 0 1 1 STREXD A1 01 1 0 UNALLOCATED 01 1 1 0 LDAEXD A1 01 1 1 1 LDREXD A1 10 0 0 0 STLB A1 10 0 0 1 UNALLOCATED 10 0 1 0 STLEXB A1 10 0 1 1 STREXB A1 10 1 0 0 LDAB A1 10 1 0 1 UNALLOCATED 10 1 1 0 LDAEXB A1 10 1 1 1 LDREXB A1 11 0 0 0 STLH A1 11 0 0 1 UNALLOCATED 11 0 1 0 STLEXH A1 11 0 1 1 STREXH A1 11 1 0 0 LDAH A1 11 1 0 1 UNALLOCATED 11 1 1 0 LDAEXH A1 11 1 1 1 LDREXH A1 Extra load/store != 1111 0 0 0 1 1 != 00 1 Decode fields Instruction page Encoding P:W o1 Rn op2 0 1111 10 LDRD (literal) A1 != 01 1 1111 01 LDRH (literal) A1 != 01 1 1111 10 LDRSB (literal) A1 != 01 1 1111 11 LDRSH (literal) A1 00 0 != 1111 10 LDRD (immediate) A1, Post-indexed 00 0 01 STRH (immediate) A1, Post-indexed 00 0 11 STRD (immediate) A1, Post-indexed 00 1 != 1111 01 LDRH (immediate) A1, Post-indexed 00 1 != 1111 10 LDRSB (immediate) A1, Post-indexed 00 1 != 1111 11 LDRSH (immediate) A1, Post-indexed 01 0 != 1111 10 UNALLOCATED 01 0 01 STRHT A1 01 0 11 UNALLOCATED 01 1 01 LDRHT A1 01 1 10 LDRSBT A1 01 1 11 LDRSHT A1 10 0 != 1111 10 LDRD (immediate) A1, Offset 10 0 01 STRH (immediate) A1, Offset 10 0 11 STRD (immediate) A1, Offset 10 1 != 1111 01 LDRH (immediate) A1, Offset 10 1 != 1111 10 LDRSB (immediate) A1, Offset 10 1 != 1111 11 LDRSH (immediate) A1, Offset 11 0 != 1111 10 LDRD (immediate) A1, Pre-indexed 11 0 01 STRH (immediate) A1, Pre-indexed 11 0 11 STRD (immediate) A1, Pre-indexed 11 1 != 1111 01 LDRH (immediate) A1, Pre-indexed 11 1 != 1111 10 LDRSB (immediate) A1, Pre-indexed 11 1 != 1111 11 LDRSH (immediate) A1, Pre-indexed != 1111 0 0 0 0 (0) (0) (0) (0) 1 != 00 1 Decode fields Instruction page Encoding P W o1 op2 0 0 0 01 STRH (register) A1, Post-indexed 0 0 0 10 LDRD (register) Post-indexed 0 0 0 11 STRD (register) Post-indexed 0 0 1 01 LDRH (register) A1, Post-indexed 0 0 1 10 LDRSB (register) A1, Post-indexed 0 0 1 11 LDRSH (register) A1, Post-indexed 0 1 0 01 STRHT A2 0 1 0 10 UNALLOCATED 0 1 0 11 UNALLOCATED 0 1 1 01 LDRHT A2 0 1 1 10 LDRSBT A2 0 1 1 11 LDRSHT A2 1 0 01 STRH (register) A1, Pre-indexed 1 0 10 LDRD (register) Pre-indexed 1 0 11 STRD (register) Pre-indexed 1 1 01 LDRH (register) A1, Pre-indexed 1 1 10 LDRSB (register) A1, Pre-indexed 1 1 11 LDRSH (register) A1, Pre-indexed Data-processing immediate != 1111 0 0 1 0 Decode fields Instruction page Encoding opc S Rn 000 AND, ANDS (immediate) A1, ANDS 001 EOR, EORS (immediate) A1, EORS 010 0 != 11x1 SUB, SUBS (immediate) A1, SUB 010 0 1101 SUB, SUBS (SP minus immediate) A1, SUB 010 0 1111 ADR A2 010 1 != 1101 SUB, SUBS (immediate) A1, SUBS 010 1 1101 SUB, SUBS (SP minus immediate) A1, SUBS 011 RSB, RSBS (immediate) A1, RSBS 100 0 != 11x1 ADD, ADDS (immediate) A1, ADD 100 0 1101 ADD, ADDS (SP plus immediate) A1, ADD 100 0 1111 ADR A1 100 1 != 1101 ADD, ADDS (immediate) A1, ADDS 100 1 1101 ADD, ADDS (SP plus immediate) A1, ADDS 101 ADC, ADCS (immediate) A1, ADCS 110 SBC, SBCS (immediate) A1, SBCS 111 RSC, RSCS (immediate) RSCS != 1111 0 0 1 1 0 1 (0) (0) (0) (0) Decode fields Instruction page Encoding opc 00 TST (immediate) A1 01 TEQ (immediate) A1 10 CMP (immediate) A1 11 CMN (immediate) A1 != 1111 0 0 1 1 1 Decode fields Instruction page Encoding opc 00 ORR, ORRS (immediate) A1, ORRS 01 MOV, MOVS (immediate) A1, MOVS 10 BIC, BICS (immediate) A1, BICS 11 MVN, MVNS (immediate) A1, MVNS != 1111 0 0 1 1 0 0 0 Decode fields Instruction page Encoding H 0 MOV, MOVS (immediate) A2 1 MOVT A1 != 1111 0 0 1 1 0 1 0 (1) (1) (1) (1) Decode fields Instruction page Encoding R:imm4 imm12 != 00000 MSR (immediate) 00000 xxxx00000000 NOP A1 00000 xxxx00000001 YIELD A1 00000 xxxx00000010 WFE A1 00000 xxxx00000011 WFI A1 00000 xxxx00000100 SEV A1 00000 xxxx00000101 SEVL A1 00000 xxxx0000011x Reserved hint, behaves as NOP 00000 xxxx00001xxx Reserved hint, behaves as NOP 00000 xxxx00010000 ESB A1 00000 xxxx00010001 Reserved hint, behaves as NOP 00000 xxxx00010010 TSB CSYNC A1 00000 xxxx00010011 Reserved hint, behaves as NOP 00000 xxxx00010100 CSDB A1 00000 xxxx00010101 Reserved hint, behaves as NOP 00000 xxxx00010110 CLRBHB A1 00000 xxxx00010111 Reserved hint, behaves as NOP 00000 xxxx00011xxx Reserved hint, behaves as NOP 00000 xxxx001xxxxx Reserved hint, behaves as NOP 00000 xxxx01xxxxxx Reserved hint, behaves as NOP 00000 xxxx10xxxxxx Reserved hint, behaves as NOP 00000 xxxx110xxxxx Reserved hint, behaves as NOP 00000 xxxx1110xxxx Reserved hint, behaves as NOP 00000 xxxx1111xxxx DBG A1 Load/store word and unsigned byte (immediate) != 1111 0 1 0 Decode fields Instruction page Encoding P:W o2 o1 Rn != 01 0 1 1111 LDR (literal) A1 != 01 1 1 1111 LDRB (literal) A1 00 0 0 STR (immediate) A1, Post-indexed 00 0 1 != 1111 LDR (immediate) A1, Post-indexed 00 1 0 STRB (immediate) A1, Post-indexed 00 1 1 != 1111 LDRB (immediate) A1, Post-indexed 01 0 0 STRT A1 01 0 1 LDRT A1 01 1 0 STRBT A1 01 1 1 LDRBT A1 10 0 0 STR (immediate) A1, Offset 10 0 1 != 1111 LDR (immediate) A1, Offset 10 1 0 STRB (immediate) A1, Offset 10 1 1 != 1111 LDRB (immediate) A1, Offset 11 0 0 STR (immediate) A1, Pre-indexed 11 0 1 != 1111 LDR (immediate) A1, Pre-indexed 11 1 0 STRB (immediate) A1, Pre-indexed 11 1 1 != 1111 LDRB (immediate) A1, Pre-indexed Load/store word and unsigned byte (register) != 1111 0 1 1 0 Decode fields Instruction page Encoding P o2 W o1 0 0 0 0 STR (register) A1, Post-indexed 0 0 0 1 LDR (register) A1, Post-indexed 0 0 1 0 STRT A2 0 0 1 1 LDRT A2 0 1 0 0 STRB (register) A1, Post-indexed 0 1 0 1 LDRB (register) A1, Post-indexed 0 1 1 0 STRBT A2 0 1 1 1 LDRBT A2 1 0 0 STR (register) A1, Pre-indexed 1 0 1 LDR (register) A1, Pre-indexed 1 1 0 STRB (register) A1, Pre-indexed 1 1 1 LDRB (register) A1, Pre-indexed Media instructions != 1111 0 1 1 1 1 1 1 0 1 Decode fields Instruction page Encoding U 0 SBFX A1 1 UBFX A1 != 1111 0 1 1 1 1 1 0 0 0 1 Decode fields Instruction page Encoding Rn != 1111 BFI A1 1111 BFC A1 != 1111 0 1 1 0 1 (0) (0) 0 1 1 1 Decode fields Instruction page Encoding U op Rn 0 00 != 1111 SXTAB16 A1 0 00 1111 SXTB16 A1 0 10 != 1111 SXTAB A1 0 10 1111 SXTB A1 0 11 != 1111 SXTAH A1 0 11 1111 SXTH A1 1 00 != 1111 UXTAB16 A1 1 00 1111 UXTB16 A1 1 10 != 1111 UXTAB A1 1 10 1111 UXTB A1 1 11 != 1111 UXTAH A1 1 11 1111 UXTH A1 != 1111 0 1 1 0 1 0 0 0 0 1 Instruction page Encoding PKHBT, PKHTB A1, PKHTB != 1111 0 1 1 0 0 (1) (1) (1) (1) 1 Decode fields Instruction page Encoding op1 B op2 000 UNALLOCATED 001 0 00 SADD16 A1 001 0 01 SASX A1 001 0 10 SSAX A1 001 0 11 SSUB16 A1 001 1 00 SADD8 A1 001 1 01 UNALLOCATED 001 1 10 UNALLOCATED 001 1 11 SSUB8 A1 010 0 00 QADD16 A1 010 0 01 QASX A1 010 0 10 QSAX A1 010 0 11 QSUB16 A1 010 1 00 QADD8 A1 010 1 01 UNALLOCATED 010 1 10 UNALLOCATED 010 1 11 QSUB8 A1 011 0 00 SHADD16 A1 011 0 01 SHASX A1 011 0 10 SHSAX A1 011 0 11 SHSUB16 A1 011 1 00 SHADD8 A1 011 1 01 UNALLOCATED 011 1 10 UNALLOCATED 011 1 11 SHSUB8 A1 100 UNALLOCATED 101 0 00 UADD16 A1 101 0 01 UASX A1 101 0 10 USAX A1 101 0 11 USUB16 A1 101 1 00 UADD8 A1 101 1 01 UNALLOCATED 101 1 10 UNALLOCATED 101 1 11 USUB8 A1 110 0 00 UQADD16 A1 110 0 01 UQASX A1 110 0 10 UQSAX A1 110 0 11 UQSUB16 A1 110 1 00 UQADD8 A1 110 1 01 UNALLOCATED 110 1 10 UNALLOCATED 110 1 11 UQSUB8 A1 111 0 00 UHADD16 A1 111 0 01 UHASX A1 111 0 10 UHSAX A1 111 0 11 UHSUB16 A1 111 1 00 UHADD8 A1 111 1 01 UNALLOCATED 111 1 10 UNALLOCATED 111 1 11 UHSUB8 A1 != 1111 0 1 1 1 1 1 1 1 1 1 1 1 Decode fields Instruction page Encoding cond 0xxx UNALLOCATED 10xx UNALLOCATED 110x UNALLOCATED 1110 UDF A1 != 1111 0 1 1 0 1 1 1 (1) (1) (1) (1) (1) (1) (1) (1) 0 1 1 Decode fields Instruction page Encoding o1 o2 0 0 REV A1 0 1 REV16 A1 1 0 RBIT A1 1 1 REVSH A1 != 1111 0 1 1 0 1 1 0 (1) (1) (1) (1) 0 0 1 1 Decode fields Instruction page Encoding U 0 SSAT16 A1 1 USAT16 A1 != 1111 0 1 1 0 1 1 0 1 Decode fields Instruction page Encoding U 0 SSAT A1, Arithmetic shift right 1 USAT A1, Arithmetic shift right != 1111 0 1 1 0 1 0 0 0 (1) (1) (1) (1) 1 0 1 1 Instruction page Encoding SEL A1 != 1111 0 1 1 1 0 1 Decode fields Instruction page Encoding op1 Ra op2 000 != 1111 000 SMLAD, SMLADX A1, SMLAD 000 != 1111 001 SMLAD, SMLADX A1, SMLADX 000 != 1111 010 SMLSD, SMLSDX A1, SMLSD 000 != 1111 011 SMLSD, SMLSDX A1, SMLSDX 000 1xx UNALLOCATED 000 1111 000 SMUAD, SMUADX A1, SMUAD 000 1111 001 SMUAD, SMUADX A1, SMUADX 000 1111 010 SMUSD, SMUSDX A1, SMUSD 000 1111 011 SMUSD, SMUSDX A1, SMUSDX 001 000 SDIV A1 001 != 000 UNALLOCATED 010 UNALLOCATED 011 000 UDIV A1 011 != 000 UNALLOCATED 100 000 SMLALD, SMLALDX A1, SMLALD 100 001 SMLALD, SMLALDX A1, SMLALDX 100 010 SMLSLD, SMLSLDX A1, SMLSLD 100 011 SMLSLD, SMLSLDX A1, SMLSLDX 100 1xx UNALLOCATED 101 != 1111 000 SMMLA, SMMLAR A1, SMMLA 101 != 1111 001 SMMLA, SMMLAR A1, SMMLAR 101 01x UNALLOCATED 101 10x UNALLOCATED 101 110 SMMLS, SMMLSR A1, SMMLS 101 111 SMMLS, SMMLSR A1, SMMLSR 101 1111 000 SMMUL, SMMULR A1, SMMUL 101 1111 001 SMMUL, SMMULR A1, SMMULR 11x UNALLOCATED != 1111 0 1 1 1 1 0 0 0 0 0 0 1 Decode fields Instruction page Encoding Ra != 1111 USADA8 A1 1111 USAD8 A1 Branch, branch with link, and block data transfer 1 0 1 Decode fields Instruction page Encoding cond H != 1111 0 B A1 != 1111 1 BL, BLX (immediate) A1 1111 BL, BLX (immediate) A2 1 1 1 1 1 0 0 Decode fields Instruction page Encoding P U S L 0 0 UNALLOCATED 0 0 0 1 RFE, RFEDA, RFEDB, RFEIA, RFEIB A1, Decrement After 0 0 1 0 SRS, SRSDA, SRSDB, SRSIA, SRSIB A1, Decrement After 0 1 0 1 RFE, RFEDA, RFEDB, RFEIA, RFEIB A1, Increment After 0 1 1 0 SRS, SRSDA, SRSDB, SRSIA, SRSIB A1, Increment After 1 0 0 1 RFE, RFEDA, RFEDB, RFEIA, RFEIB A1, Decrement Before 1 0 1 0 SRS, SRSDA, SRSDB, SRSIA, SRSIB A1, Decrement Before 1 1 UNALLOCATED 1 1 0 1 RFE, RFEDA, RFEDB, RFEIA, RFEIB A1, Increment Before 1 1 1 0 SRS, SRSDA, SRSDB, SRSIA, SRSIB A1, Increment Before != 1111 1 0 0 Decode fields Instruction page Encoding P U op L register_list 0 0 0 0 STMDA, STMED 0 0 0 1 LDMDA, LDMFA 0 1 0 0 STM, STMIA, STMEA A1 0 1 0 1 LDM, LDMIA, LDMFD A1 1 0 STM (User registers) 1 0 0 0 STMDB, STMFD A1 1 0 0 1 LDMDB, LDMEA A1 1 1 0xxxxxxxxxxxxxxx LDM (User registers) 1 1 0 0 STMIB, STMFA 1 1 0 1 LDMIB, LDMED 1 1 1xxxxxxxxxxxxxxx LDM (exception return) Floating-point data-processing != 1111 1 1 1 0 1 0 0 Decode fields Instruction page Encoding o0:o1 size o2 != 111 00 UNALLOCATED 000 01 0 VMLA (floating-point) A2, Half-precision scalar 000 01 1 VMLS (floating-point) A2, Half-precision scalar 000 10 0 VMLA (floating-point) A2, Single-precision scalar 000 10 1 VMLS (floating-point) A2, Single-precision scalar 000 11 0 VMLA (floating-point) A2, Double-precision scalar 000 11 1 VMLS (floating-point) A2, Double-precision scalar 001 01 0 VNMLS A1, Half-precision scalar 001 01 1 VNMLA A1, Half-precision scalar 001 10 0 VNMLS A1, Single-precision scalar 001 10 1 VNMLA A1, Single-precision scalar 001 11 0 VNMLS A1, Double-precision scalar 001 11 1 VNMLA A1, Double-precision scalar 010 01 0 VMUL (floating-point) A2, Half-precision scalar 010 01 1 VNMUL A1, Half-precision scalar 010 10 0 VMUL (floating-point) A2, Single-precision scalar 010 10 1 VNMUL A1, Single-precision scalar 010 11 0 VMUL (floating-point) A2, Double-precision scalar 010 11 1 VNMUL A1, Double-precision scalar 011 01 0 VADD (floating-point) A2, Half-precision scalar 011 01 1 VSUB (floating-point) A2, Half-precision scalar 011 10 0 VADD (floating-point) A2, Single-precision scalar 011 10 1 VSUB (floating-point) A2, Single-precision scalar 011 11 0 VADD (floating-point) A2, Double-precision scalar 011 11 1 VSUB (floating-point) A2, Double-precision scalar 100 01 0 VDIV A1, Half-precision scalar 100 10 0 VDIV A1, Single-precision scalar 100 11 0 VDIV A1, Double-precision scalar 101 01 0 VFNMS A1, Half-precision scalar 101 01 1 VFNMA A1, Half-precision scalar 101 10 0 VFNMS A1, Single-precision scalar 101 10 1 VFNMA A1, Single-precision scalar 101 11 0 VFNMS A1, Double-precision scalar 101 11 1 VFNMA A1, Double-precision scalar 110 01 0 VFMA A2, Half-precision scalar 110 01 1 VFMS A2, Half-precision scalar 110 10 0 VFMA A2, Single-precision scalar 110 10 1 VFMS A2, Single-precision scalar 110 11 0 VFMA A2, Double-precision scalar 110 11 1 VFMS A2, Double-precision scalar != 1111 1 1 1 0 1 1 1 1 0 1 0 Decode fields Instruction page Encoding o1 opc2 size o3 00 UNALLOCATED 0 000 01 0 UNALLOCATED 0 000 01 1 VABS A2, Half-precision scalar 0 000 10 0 VMOV (register) A2, Single-precision scalar 0 000 10 1 VABS A2, Single-precision scalar 0 000 11 0 VMOV (register) A2, Double-precision scalar 0 000 11 1 VABS A2, Double-precision scalar 0 001 01 0 VNEG A2, Half-precision scalar 0 001 01 1 VSQRT A1, Half-precision scalar 0 001 10 0 VNEG A2, Single-precision scalar 0 001 10 1 VSQRT A1, Single-precision scalar 0 001 11 0 VNEG A2, Double-precision scalar 0 001 11 1 VSQRT A1, Double-precision scalar 0 010 01 UNALLOCATED 0 010 10 0 VCVTB A1, Half-precision to single-precision 0 010 10 1 VCVTT A1, Half-precision to single-precision 0 010 11 0 VCVTB A1, Half-precision to double-precision 0 010 11 1 VCVTT A1, Half-precision to double-precision 0 011 01 0 VCVTB (BFloat16) A1 0 011 01 1 VCVTT (BFloat16) A1 0 011 10 0 VCVTB A1, Single-precision to half-precision 0 011 10 1 VCVTT A1, Single-precision to half-precision 0 011 11 0 VCVTB A1, Double-precision to half-precision 0 011 11 1 VCVTT A1, Double-precision to half-precision 0 100 01 0 VCMP A1, Half-precision scalar 0 100 01 1 VCMPE A1, Half-precision scalar 0 100 10 0 VCMP A1, Single-precision scalar 0 100 10 1 VCMPE A1, Single-precision scalar 0 100 11 0 VCMP A1, Double-precision scalar 0 100 11 1 VCMPE A1, Double-precision scalar 0 101 01 0 VCMP A2, Half-precision scalar 0 101 01 1 VCMPE A2, Half-precision scalar 0 101 10 0 VCMP A2, Single-precision scalar 0 101 10 1 VCMPE A2, Single-precision scalar 0 101 11 0 VCMP A2, Double-precision scalar 0 101 11 1 VCMPE A2, Double-precision scalar 0 110 01 0 VRINTR A1, Half-precision scalar 0 110 01 1 VRINTZ (floating-point) A1, Half-precision scalar 0 110 10 0 VRINTR A1, Single-precision scalar 0 110 10 1 VRINTZ (floating-point) A1, Single-precision scalar 0 110 11 0 VRINTR A1, Double-precision scalar 0 110 11 1 VRINTZ (floating-point) A1, Double-precision scalar 0 111 01 0 VRINTX (floating-point) A1, Half-precision scalar 0 111 01 1 UNALLOCATED 0 111 10 0 VRINTX (floating-point) A1, Single-precision scalar 0 111 10 1 VCVT (between double-precision and single-precision) A1, Single-precision to double-precision 0 111 11 0 VRINTX (floating-point) A1, Double-precision scalar 0 111 11 1 VCVT (between double-precision and single-precision) A1, Double-precision to single-precision 1 000 01 VCVT (integer to floating-point, floating-point) A1, Half-precision scalar 1 000 10 VCVT (integer to floating-point, floating-point) A1, Single-precision scalar 1 000 11 VCVT (integer to floating-point, floating-point) A1, Double-precision scalar 1 001 01 UNALLOCATED 1 001 10 UNALLOCATED 1 001 11 0 UNALLOCATED 1 001 11 1 VJCVT A1 1 01x 01 VCVT (between floating-point and fixed-point, floating-point) A1, Half-precision scalar 1 01x 10 VCVT (between floating-point and fixed-point, floating-point) A1, Single-precision scalar 1 01x 11 VCVT (between floating-point and fixed-point, floating-point) A1, Double-precision scalar 1 100 01 0 VCVTR A1, Half-precision scalar 1 100 01 1 VCVT (floating-point to integer, floating-point) A1, Half-precision scalar 1 100 10 0 VCVTR A1, Single-precision scalar 1 100 10 1 VCVT (floating-point to integer, floating-point) A1, Single-precision scalar 1 100 11 0 VCVTR A1, Double-precision scalar 1 100 11 1 VCVT (floating-point to integer, floating-point) A1, Double-precision scalar 1 101 01 0 VCVTR A1, Half-precision scalar 1 101 01 1 VCVT (floating-point to integer, floating-point) A1, Half-precision scalar 1 101 10 0 VCVTR A1, Single-precision scalar 1 101 10 1 VCVT (floating-point to integer, floating-point) A1, Single-precision scalar 1 101 11 0 VCVTR A1, Double-precision scalar 1 101 11 1 VCVT (floating-point to integer, floating-point) A1, Double-precision scalar 1 11x 01 VCVT (between floating-point and fixed-point, floating-point) A1, Half-precision scalar 1 11x 10 VCVT (between floating-point and fixed-point, floating-point) A1, Single-precision scalar 1 11x 11 VCVT (between floating-point and fixed-point, floating-point) A1, Double-precision scalar != 1111 1 1 1 0 1 1 1 1 0 (0) 0 (0) 0 Decode fields Instruction page Encoding size 00 UNALLOCATED 01 VMOV (immediate) A2, Half-precision scalar 10 VMOV (immediate) A2, Single-precision scalar 11 VMOV (immediate) A2, Double-precision scalar Advanced SIMD and System register 32-bit move != 1111 1 1 1 0 1 0 1 1 1 (0) (0) (0) (0) Decode fields Instruction page Encoding opc1 L opc2 0xx 0 VMOV (general-purpose register to scalar) A1 1 VMOV (scalar to general-purpose register) A1 1xx 0 0x VDUP (general-purpose register) A1 1xx 0 1x UNALLOCATED != 1111 1 1 1 0 0 0 0 1 0 0 1 (0) (0) 1 (0) (0) (0) (0) Instruction page Encoding VMOV (between general-purpose register and half-precision) A1, To general-purpose register != 1111 1 1 1 0 0 0 0 1 0 1 0 (0) (0) 1 (0) (0) (0) (0) Instruction page Encoding VMOV (between general-purpose register and single-precision) A1, To general-purpose register != 1111 1 1 1 0 1 1 1 1 0 1 0 (0) (0) (0) 1 (0) (0) (0) (0) Decode fields Instruction page Encoding L 0 VMSR A1 1 VMRS A1 != 1111 1 1 1 0 1 1 1 1 Decode fields Instruction page Encoding L 0 MCR A1 1 MRC A1 Advanced SIMD and System register load/store and 64-bit move != 1111 1 1 0 0 0 0 1 0 Decode fields Instruction page Encoding D op size opc2 o3 0 UNALLOCATED 1 0 UNALLOCATED 1 0x 00 1 UNALLOCATED 1 01 UNALLOCATED 1 0 10 00 1 VMOV (between two general-purpose registers and two single-precision registers) A1, From general-purpose registers 1 0 11 00 1 VMOV (between two general-purpose registers and a doubleword floating-point register) A1, From general-purpose registers 1 1x UNALLOCATED 1 1 10 00 1 VMOV (between two general-purpose registers and two single-precision registers) A1, To general-purpose registers 1 1 11 00 1 VMOV (between two general-purpose registers and a doubleword floating-point register) A1, To general-purpose registers != 1111 1 1 0 1 0 Decode fields Instruction page Encoding P U W L Rn size imm8 0 0 1 UNALLOCATED 0 1 0x UNALLOCATED 0 1 0 10 VSTM, VSTMDB, VSTMIA A2, Increment After 0 1 0 11 xxxxxxx0 VSTM, VSTMDB, VSTMIA A1, Increment After 0 1 0 11 xxxxxxx1 FSTMDBX, FSTMIAX A1, Increment After 0 1 1 10 VLDM, VLDMDB, VLDMIA A2, Increment After 0 1 1 11 xxxxxxx0 VLDM, VLDMDB, VLDMIA A1, Increment After 0 1 1 11 xxxxxxx1 FLDM*X (FLDMDBX, FLDMIAX) A1, Increment After 1 0 0 01 VSTR A1, Half-precision scalar 1 0 0 10 VSTR A1, Single-precision scalar 1 0 0 11 VSTR A1, Double-precision scalar 1 0 1 != 1111 01 VLDR (immediate) A1, Half-precision scalar 1 0 1 != 1111 10 VLDR (immediate) A1, Single-precision scalar 1 0 1 != 1111 11 VLDR (immediate) A1, Double-precision scalar 1 0 1 0x UNALLOCATED 1 0 1 0 10 VSTM, VSTMDB, VSTMIA A2, Decrement Before 1 0 1 0 11 xxxxxxx0 VSTM, VSTMDB, VSTMIA A1, Decrement Before 1 0 1 0 11 xxxxxxx1 FSTMDBX, FSTMIAX A1, Decrement Before 1 0 1 1 10 VLDM, VLDMDB, VLDMIA A2, Decrement Before 1 0 1 1 11 xxxxxxx0 VLDM, VLDMDB, VLDMIA A1, Decrement Before 1 0 1 1 11 xxxxxxx1 FLDM*X (FLDMDBX, FLDMIAX) A1, Decrement Before 1 0 1 1111 01 VLDR (literal) A1, Half-precision scalar 1 0 1 1111 10 VLDR (literal) A1, Single-precision scalar 1 0 1 1111 11 VLDR (literal) A1, Double-precision scalar 1 1 1 UNALLOCATED != 1111 1 1 0 0 0 0 1 1 1 Decode fields Instruction page Encoding D L 0 UNALLOCATED 1 0 MCRR A1 1 1 MRRC A1 != 1111 1 1 0 1 1 1 Decode fields Instruction page Encoding P:U:W D L Rn CRd cp15 != 000 0 != 0101 0 UNALLOCATED != 000 0 1 1111 0101 0 LDC (literal) A1 != 000 1 UNALLOCATED != 000 1 0101 0 UNALLOCATED 0x1 0 0 0101 0 STC A1, Post-indexed 0x1 0 1 != 1111 0101 0 LDC (immediate) A1, Post-indexed 010 0 0 0101 0 STC A1, Unindexed 010 0 1 != 1111 0101 0 LDC (immediate) A1, Unindexed 1x0 0 0 0101 0 STC A1, Offset 1x0 0 1 != 1111 0101 0 LDC (immediate) A1, Offset 1x1 0 0 0101 0 STC A1, Pre-indexed 1x1 0 1 != 1111 0101 0 LDC (immediate) A1, Pre-indexed Unconditional Advanced SIMD and floating-point instructions 1 1 1 1 1 1 1 0 1 1 0 Decode fields Instruction page Encoding op1 op2 op4 Q U 0 00 0 UNALLOCATED 0 00 1 0 0 VDOT (by element) A1, 64-bit SIMD vector 0 00 1 1 UNALLOCATED 0 00 1 1 0 VDOT (by element) A1, 128-bit SIMD vector 0 01 0 UNALLOCATED 0 10 0 UNALLOCATED 0 10 1 0 0 VSDOT (by element) A1, 64-bit SIMD vector 0 10 1 0 1 VUDOT (by element) A1, 64-bit SIMD vector 0 10 1 1 0 VSDOT (by element) A1, 128-bit SIMD vector 0 10 1 1 1 VUDOT (by element) A1, 128-bit SIMD vector 0 11 UNALLOCATED 1 0 UNALLOCATED 1 00 1 0 0 VUSDOT (by element) A1, 64-bit SIMD vector 1 00 1 0 1 VSUDOT (by element) A1, 64-bit SIMD vector 1 00 1 1 0 VUSDOT (by element) A1, 128-bit SIMD vector 1 00 1 1 1 VSUDOT (by element) A1, 128-bit SIMD vector 1 01 1 UNALLOCATED 1 1x 1 UNALLOCATED 1 1 1 1 1 1 1 0 1 0 0 0 Decode fields Instruction page Encoding op1 op2 Q U 0 0 VCMLA (by element) A1, 128-bit SIMD vector of half-precision floating-point 0 00 1 VFMAL (by scalar) A1, 128-bit SIMD vector 0 01 1 VFMSL (by scalar) A1, 128-bit SIMD vector 0 10 1 UNALLOCATED 0 11 1 VFMAB, VFMAT (BFloat16, by scalar) A1 1 0 0 VCMLA (by element) A1, 64-bit SIMD vector of single-precision floating-point 1 1 UNALLOCATED 1 1 0 VCMLA (by element) A1, 128-bit SIMD vector of single-precision floating-point 1 1 1 1 1 1 0 1 0 Decode fields Instruction page Encoding op1 op2 op3 op4 Q U x1 0x 0 0 0 0 VCADD A1, 64-bit SIMD vector x1 0x 0 0 0 1 UNALLOCATED x1 0x 0 0 1 0 VCADD A1, 128-bit SIMD vector x1 0x 0 0 1 1 UNALLOCATED 00 0x 0 0 UNALLOCATED 00 0x 0 1 UNALLOCATED 00 00 1 0 0 0 UNALLOCATED 00 00 1 0 0 1 UNALLOCATED 00 00 1 0 1 0 VMMLA A1 00 00 1 0 1 1 UNALLOCATED 00 00 1 1 0 0 VDOT (vector) A1, 64-bit SIMD vector 00 00 1 1 0 1 UNALLOCATED 00 00 1 1 1 0 VDOT (vector) A1, 128-bit SIMD vector 00 00 1 1 1 1 UNALLOCATED 00 01 1 0 UNALLOCATED 00 01 1 1 UNALLOCATED 00 10 0 0 1 VFMAL (vector) A1, 128-bit SIMD vector 00 10 0 1 UNALLOCATED 00 10 1 0 0 UNALLOCATED 00 10 1 0 1 0 VSMMLA A1 00 10 1 0 1 1 VUMMLA A1 00 10 1 1 0 0 VSDOT (vector) A1, 64-bit SIMD vector 00 10 1 1 0 1 VUDOT (vector) A1, 64-bit SIMD vector 00 10 1 1 1 0 VSDOT (vector) A1, 128-bit SIMD vector 00 10 1 1 1 1 VUDOT (vector) A1, 128-bit SIMD vector 00 11 0 0 1 VFMAB, VFMAT (BFloat16, vector) A1 00 11 0 1 UNALLOCATED 00 11 1 0 UNALLOCATED 00 11 1 1 UNALLOCATED 01 10 0 0 1 VFMSL (vector) A1, 128-bit SIMD vector 01 10 0 1 UNALLOCATED 01 10 1 0 0 UNALLOCATED 01 10 1 0 1 0 VUSMMLA A1 01 10 1 0 1 1 UNALLOCATED 01 10 1 1 0 0 VUSDOT (vector) A1, 64-bit SIMD vector 01 10 1 1 1 UNALLOCATED 01 10 1 1 1 0 VUSDOT (vector) A1, 128-bit SIMD vector 01 11 0 1 UNALLOCATED 01 11 1 0 UNALLOCATED 01 11 1 1 UNALLOCATED 1x 0 0 0 VCMLA A1, 128-bit SIMD vector 10 11 0 1 UNALLOCATED 10 11 1 0 UNALLOCATED 10 11 1 1 UNALLOCATED 11 11 0 1 UNALLOCATED 11 11 1 0 UNALLOCATED 11 11 1 1 UNALLOCATED 1 1 1 1 1 1 1 0 0 1 0 != 00 0 0 Decode fields Instruction page Encoding size 01 VSELEQ, VSELGE, VSELGT, VSELVS A1, Greater than, half-precision scalar 10 VSELEQ, VSELGE, VSELGT, VSELVS A1, Greater than, single-precision scalar 11 VSELEQ, VSELGE, VSELGT, VSELVS A1, Greater than, double-precision scalar 1 1 1 1 1 1 1 0 1 1 1 1 1 0 != 00 1 0 Decode fields Instruction page Encoding o1 RM size op 0 != 00 1 UNALLOCATED 0 00 01 0 VRINTA (floating-point) A1, Half-precision scalar 0 00 10 0 VRINTA (floating-point) A1, Single-precision scalar 0 00 11 0 VRINTA (floating-point) A1, Double-precision scalar 0 01 01 0 VRINTN (floating-point) A1, Half-precision scalar 0 01 10 0 VRINTN (floating-point) A1, Single-precision scalar 0 01 11 0 VRINTN (floating-point) A1, Double-precision scalar 0 10 01 0 VRINTP (floating-point) A1, Half-precision scalar 0 10 10 0 VRINTP (floating-point) A1, Single-precision scalar 0 10 11 0 VRINTP (floating-point) A1, Double-precision scalar 0 11 01 0 VRINTM (floating-point) A1, Half-precision scalar 0 11 10 0 VRINTM (floating-point) A1, Single-precision scalar 0 11 11 0 VRINTM (floating-point) A1, Double-precision scalar 1 00 01 VCVTA (floating-point) A1, Half-precision scalar 1 00 10 VCVTA (floating-point) A1, Single-precision scalar 1 00 11 VCVTA (floating-point) A1, Double-precision scalar 1 01 01 VCVTN (floating-point) A1, Half-precision scalar 1 01 10 VCVTN (floating-point) A1, Single-precision scalar 1 01 11 VCVTN (floating-point) A1, Double-precision scalar 1 10 01 VCVTP (floating-point) A1, Half-precision scalar 1 10 10 VCVTP (floating-point) A1, Single-precision scalar 1 10 11 VCVTP (floating-point) A1, Double-precision scalar 1 11 01 VCVTM (floating-point) A1, Half-precision scalar 1 11 10 VCVTM (floating-point) A1, Single-precision scalar 1 11 11 VCVTM (floating-point) A1, Double-precision scalar 1 1 1 1 1 1 1 0 1 1 1 0 0 0 0 1 0 != 00 1 0 Decode fields Instruction page Encoding size op 01 UNALLOCATED 10 0 VMOVX A1 10 1 VINS A1 11 UNALLOCATED 1 1 1 1 1 1 1 0 1 0 0 1 0 != 00 0 Decode fields Instruction page Encoding size op 01 0 VMAXNM A2, Half-precision scalar 01 1 VMINNM A2, Half-precision scalar 10 0 VMAXNM A2, Single-precision scalar 10 1 VMINNM A2, Single-precision scalar 11 0 VMAXNM A2, Double-precision scalar 11 1 VMINNM A2, Double-precision scalar Supervisor call != 1111 1 1 1 1 Instruction page Encoding SVC A1 Miscellaneous 1 1 1 1 0 0 0 1 0 0 0 0 (0) (0) (0) (0) (0) (0) 0 Decode fields Instruction page Encoding imod M op I F mode 1 0 0 0xxxx SETEND A1 00 1 0 CPS, CPSID, CPSIE A1, Change mode 10 0 CPS, CPSID, CPSIE A1, Interrupt enable and change mode 1 0 0 1xxxx UNALLOCATED 1 0 1 UNALLOCATED 1 1 UNALLOCATED 11 0 CPS, CPSID, CPSIE A1, Interrupt disable and change mode 1 1 1 1 0 0 0 1 0 0 0 1 (0) (0) (0) (0) (0) (0) (0) (0) (0) (0) (0) 0 0 0 0 (0) (0) (0) (0) Instruction page Encoding SETPAN A1 Memory hints and barriers 1 1 1 1 0 1 0 1 0 1 1 1 (1) (1) (1) (1) (1) (1) (1) (1) (0) (0) (0) (0) Decode fields Instruction page Encoding opcode option 0000 UNPREDICTABLE 0001 CLREX A1 001x UNPREDICTABLE 0100 != 0x00 DSB A1 0100 0000 SSBB A1 0100 0100 PSSBB A1 0101 DMB A1 0110 ISB A1 0111 SB A1 1xxx UNPREDICTABLE 1 1 1 1 0 1 0 0 1 (1) (1) (1) (1) Decode fields Instruction page Encoding D R Rn 0 0 Reserved hint, behaves as NOP 0 1 PLI (immediate, literal) A1 1 1111 PLD (literal) A1 1 0 != 1111 PLD, PLDW (immediate) A1, Preload write 1 1 != 1111 PLD, PLDW (immediate) A1, Preload read 1 1 1 1 0 1 1 0 1 (1) (1) (1) (1) 0 Decode fields Instruction page Encoding D o2 imm5:stype 0 0 Reserved hint, behaves as NOP 0 1 != 0000011 PLI (register) A1, Shift or rotate by value 0 1 0000011 PLI (register) A1, Rotate right with extend 1 0 != 0000011 PLD, PLDW (register) A1, Preload write, optional shift or rotate 1 0 0000011 PLD, PLDW (register) A1, Preload write, rotate right with extend 1 1 != 0000011 PLD, PLDW (register) A1, Preload read, optional shift or rotate 1 1 0000011 PLD, PLDW (register) A1, Preload read, rotate right with extend Advanced SIMD element or structure load/store 1 1 1 1 0 1 0 0 1 0 1 1 Decode fields Instruction page Encoding L N a Rm 0 UNALLOCATED 1 00 != 11x1 VLD1 (single element to all lanes) A1, Post-indexed 1 00 1101 VLD1 (single element to all lanes) A1, Post-indexed 1 00 1111 VLD1 (single element to all lanes) A1, Offset 1 01 != 11x1 VLD2 (single 2-element structure to all lanes) A1, Post-indexed 1 01 1101 VLD2 (single 2-element structure to all lanes) A1, Post-indexed 1 01 1111 VLD2 (single 2-element structure to all lanes) A1, Offset 1 10 0 != 11x1 VLD3 (single 3-element structure to all lanes) A1, Post-indexed 1 10 0 1101 VLD3 (single 3-element structure to all lanes) A1, Post-indexed 1 10 0 1111 VLD3 (single 3-element structure to all lanes) A1, Offset 1 10 1 UNALLOCATED 1 11 != 11x1 VLD4 (single 4-element structure to all lanes) A1, Post-indexed 1 11 1101 VLD4 (single 4-element structure to all lanes) A1, Post-indexed 1 11 1111 VLD4 (single 4-element structure to all lanes) A1, Offset 1 1 1 1 0 1 0 0 0 0 Decode fields Instruction page Encoding L itype Rm 0 000x != 11x1 VST4 (multiple 4-element structures) A1, Post-indexed 0 000x 1101 VST4 (multiple 4-element structures) A1, Post-indexed 0 000x 1111 VST4 (multiple 4-element structures) A1, Offset 0 0010 != 11x1 VST1 (multiple single elements) A4, Post-indexed 0 0010 1101 VST1 (multiple single elements) A4, Post-indexed 0 0010 1111 VST1 (multiple single elements) A4, Offset 0 0011 != 11x1 VST2 (multiple 2-element structures) A2, Post-indexed 0 0011 1101 VST2 (multiple 2-element structures) A2, Post-indexed 0 0011 1111 VST2 (multiple 2-element structures) A2, Offset 0 010x != 11x1 VST3 (multiple 3-element structures) A1, Post-indexed 0 010x 1101 VST3 (multiple 3-element structures) A1, Post-indexed 0 010x 1111 VST3 (multiple 3-element structures) A1, Offset 0 0110 != 11x1 VST1 (multiple single elements) A3, Post-indexed 0 0110 1101 VST1 (multiple single elements) A3, Post-indexed 0 0110 1111 VST1 (multiple single elements) A3, Offset 0 0111 != 11x1 VST1 (multiple single elements) A1, Post-indexed 0 0111 1101 VST1 (multiple single elements) A1, Post-indexed 0 0111 1111 VST1 (multiple single elements) A1, Offset 0 100x != 11x1 VST2 (multiple 2-element structures) A1, Post-indexed 0 100x 1101 VST2 (multiple 2-element structures) A1, Post-indexed 0 100x 1111 VST2 (multiple 2-element structures) A1, Offset 0 1010 != 11x1 VST1 (multiple single elements) A2, Post-indexed 0 1010 1101 VST1 (multiple single elements) A2, Post-indexed 0 1010 1111 VST1 (multiple single elements) A2, Offset 1 000x != 11x1 VLD4 (multiple 4-element structures) A1, Post-indexed 1 000x 1101 VLD4 (multiple 4-element structures) A1, Post-indexed 1 000x 1111 VLD4 (multiple 4-element structures) A1, Offset 1 0010 != 11x1 VLD1 (multiple single elements) A4, Post-indexed 1 0010 1101 VLD1 (multiple single elements) A4, Post-indexed 1 0010 1111 VLD1 (multiple single elements) A4, Offset 1 0011 != 11x1 VLD2 (multiple 2-element structures) A2, Post-indexed 1 0011 1101 VLD2 (multiple 2-element structures) A2, Post-indexed 1 0011 1111 VLD2 (multiple 2-element structures) A2, Offset 1 010x != 11x1 VLD3 (multiple 3-element structures) A1, Post-indexed 1 010x 1101 VLD3 (multiple 3-element structures) A1, Post-indexed 1 010x 1111 VLD3 (multiple 3-element structures) A1, Offset 1011 UNALLOCATED 1 0110 != 11x1 VLD1 (multiple single elements) A3, Post-indexed 1 0110 1101 VLD1 (multiple single elements) A3, Post-indexed 1 0110 1111 VLD1 (multiple single elements) A3, Offset 1 0111 != 11x1 VLD1 (multiple single elements) A1, Post-indexed 1 0111 1101 VLD1 (multiple single elements) A1, Post-indexed 1 0111 1111 VLD1 (multiple single elements) A1, Offset 11xx UNALLOCATED 1 100x != 11x1 VLD2 (multiple 2-element structures) A1, Post-indexed 1 100x 1101 VLD2 (multiple 2-element structures) A1, Post-indexed 1 100x 1111 VLD2 (multiple 2-element structures) A1, Offset 1 1010 != 11x1 VLD1 (multiple single elements) A2, Post-indexed 1 1010 1101 VLD1 (multiple single elements) A2, Post-indexed 1 1010 1111 VLD1 (multiple single elements) A2, Offset 1 1 1 1 0 1 0 0 1 0 != 11 Decode fields Instruction page Encoding L size N Rm 0 00 00 != 11x1 VST1 (single element from one lane) A1, Post-indexed 0 00 00 1101 VST1 (single element from one lane) A1, Post-indexed 0 00 00 1111 VST1 (single element from one lane) A1, Offset 0 00 01 != 11x1 VST2 (single 2-element structure from one lane) A1, Post-indexed 0 00 01 1101 VST2 (single 2-element structure from one lane) A1, Post-indexed 0 00 01 1111 VST2 (single 2-element structure from one lane) A1, Offset 0 00 10 != 11x1 VST3 (single 3-element structure from one lane) A1, Post-indexed 0 00 10 1101 VST3 (single 3-element structure from one lane) A1, Post-indexed 0 00 10 1111 VST3 (single 3-element structure from one lane) A1, Offset 0 00 11 != 11x1 VST4 (single 4-element structure from one lane) A1, Post-indexed 0 00 11 1101 VST4 (single 4-element structure from one lane) A1, Post-indexed 0 00 11 1111 VST4 (single 4-element structure from one lane) A1, Offset 0 01 00 != 11x1 VST1 (single element from one lane) A2, Post-indexed 0 01 00 1101 VST1 (single element from one lane) A2, Post-indexed 0 01 00 1111 VST1 (single element from one lane) A2, Offset 0 01 01 != 11x1 VST2 (single 2-element structure from one lane) A2, Post-indexed 0 01 01 1101 VST2 (single 2-element structure from one lane) A2, Post-indexed 0 01 01 1111 VST2 (single 2-element structure from one lane) A2, Offset 0 01 10 != 11x1 VST3 (single 3-element structure from one lane) A2, Post-indexed 0 01 10 1101 VST3 (single 3-element structure from one lane) A2, Post-indexed 0 01 10 1111 VST3 (single 3-element structure from one lane) A2, Offset 0 01 11 != 11x1 VST4 (single 4-element structure from one lane) A2, Post-indexed 0 01 11 1101 VST4 (single 4-element structure from one lane) A2, Post-indexed 0 01 11 1111 VST4 (single 4-element structure from one lane) A2, Offset 0 10 00 != 11x1 VST1 (single element from one lane) A3, Post-indexed 0 10 00 1101 VST1 (single element from one lane) A3, Post-indexed 0 10 00 1111 VST1 (single element from one lane) A3, Offset 0 10 01 != 11x1 VST2 (single 2-element structure from one lane) A3, Post-indexed 0 10 01 1101 VST2 (single 2-element structure from one lane) A3, Post-indexed 0 10 01 1111 VST2 (single 2-element structure from one lane) A3, Offset 0 10 10 != 11x1 VST3 (single 3-element structure from one lane) A3, Post-indexed 0 10 10 1101 VST3 (single 3-element structure from one lane) A3, Post-indexed 0 10 10 1111 VST3 (single 3-element structure from one lane) A3, Offset 0 10 11 != 11x1 VST4 (single 4-element structure from one lane) A3, Post-indexed 0 10 11 1101 VST4 (single 4-element structure from one lane) A3, Post-indexed 0 10 11 1111 VST4 (single 4-element structure from one lane) A3, Offset 1 00 00 != 11x1 VLD1 (single element to one lane) A1, Post-indexed 1 00 00 1101 VLD1 (single element to one lane) A1, Post-indexed 1 00 00 1111 VLD1 (single element to one lane) A1, Offset 1 00 01 != 11x1 VLD2 (single 2-element structure to one lane) A1, Post-indexed 1 00 01 1101 VLD2 (single 2-element structure to one lane) A1, Post-indexed 1 00 01 1111 VLD2 (single 2-element structure to one lane) A1, Offset 1 00 10 != 11x1 VLD3 (single 3-element structure to one lane) A1, Post-indexed 1 00 10 1101 VLD3 (single 3-element structure to one lane) A1, Post-indexed 1 00 10 1111 VLD3 (single 3-element structure to one lane) A1, Offset 1 00 11 != 11x1 VLD4 (single 4-element structure to one lane) A1, Post-indexed 1 00 11 1101 VLD4 (single 4-element structure to one lane) A1, Post-indexed 1 00 11 1111 VLD4 (single 4-element structure to one lane) A1, Offset 1 01 00 != 11x1 VLD1 (single element to one lane) A2, Post-indexed 1 01 00 1101 VLD1 (single element to one lane) A2, Post-indexed 1 01 00 1111 VLD1 (single element to one lane) A2, Offset 1 01 01 != 11x1 VLD2 (single 2-element structure to one lane) A2, Post-indexed 1 01 01 1101 VLD2 (single 2-element structure to one lane) A2, Post-indexed 1 01 01 1111 VLD2 (single 2-element structure to one lane) A2, Offset 1 01 10 != 11x1 VLD3 (single 3-element structure to one lane) A2, Post-indexed 1 01 10 1101 VLD3 (single 3-element structure to one lane) A2, Post-indexed 1 01 10 1111 VLD3 (single 3-element structure to one lane) A2, Offset 1 01 11 != 11x1 VLD4 (single 4-element structure to one lane) A2, Post-indexed 1 01 11 1101 VLD4 (single 4-element structure to one lane) A2, Post-indexed 1 01 11 1111 VLD4 (single 4-element structure to one lane) A2, Offset 1 10 00 != 11x1 VLD1 (single element to one lane) A3, Post-indexed 1 10 00 1101 VLD1 (single element to one lane) A3, Post-indexed 1 10 00 1111 VLD1 (single element to one lane) A3, Offset 1 10 01 != 11x1 VLD2 (single 2-element structure to one lane) A3, Post-indexed 1 10 01 1101 VLD2 (single 2-element structure to one lane) A3, Post-indexed 1 10 01 1111 VLD2 (single 2-element structure to one lane) A3, Offset 1 10 10 != 11x1 VLD3 (single 3-element structure to one lane) A3, Post-indexed 1 10 10 1101 VLD3 (single 3-element structure to one lane) A3, Post-indexed 1 10 10 1111 VLD3 (single 3-element structure to one lane) A3, Offset 1 10 11 != 11x1 VLD4 (single 4-element structure to one lane) A3, Post-indexed 1 10 11 1101 VLD4 (single 4-element structure to one lane) A3, Post-indexed 1 10 11 1111 VLD4 (single 4-element structure to one lane) A3, Offset Advanced SIMD three registers of the same length 1 1 1 1 0 0 1 0 Decode fields Instruction page Encoding U size opc Q o1 0 0x 1100 1 VFMA A1, 128-bit SIMD vector 0 0x 1101 0 VADD (floating-point) A1, 128-bit SIMD vector 0 0x 1101 1 VMLA (floating-point) A1, 128-bit SIMD vector 0 0x 1110 0 VCEQ (register) A2, 128-bit SIMD vector 0 0x 1111 0 VMAX (floating-point) A1, 128-bit SIMD vector 0 0x 1111 1 VRECPS A1, 128-bit SIMD vector 0000 0 VHADD A1, 128-bit SIMD vector 0 00 0001 1 VAND (register) A1, 128-bit SIMD vector 0000 1 VQADD A1, 128-bit SIMD vector 0001 0 VRHADD A1, 128-bit SIMD vector 0 00 1100 0 SHA1C A1 0010 0 VHSUB A1, 128-bit SIMD vector 0 01 0001 1 VBIC (register) A1, 128-bit SIMD vector 0010 1 VQSUB A1, 128-bit SIMD vector 0011 0 VCGT (register) A1, 128-bit SIMD vector 0011 1 VCGE (register) A1, 128-bit SIMD vector 0 01 1100 0 SHA1P A1 0 1x 1100 1 VFMS A1, 128-bit SIMD vector 0 1x 1101 0 VSUB (floating-point) A1, 128-bit SIMD vector 0 1x 1101 1 VMLS (floating-point) A1, 128-bit SIMD vector 0 1x 1110 0 UNALLOCATED 0 1x 1111 0 VMIN (floating-point) A1, 128-bit SIMD vector 0 1x 1111 1 VRSQRTS A1, 128-bit SIMD vector 0100 0 VSHL (register) A1, 128-bit SIMD vector 0 1000 0 VADD (integer) A1, 128-bit SIMD vector 0 10 0001 1 VORR (register) A1, 128-bit SIMD vector 0 1000 1 VTST A1, 128-bit SIMD vector 0100 1 VQSHL (register) A1, 128-bit SIMD vector 0 1001 0 VMLA (integer) A1, 128-bit SIMD vector 0101 0 VRSHL A1, 128-bit SIMD vector 0101 1 VQRSHL A1, 128-bit SIMD vector 0 1011 0 VQDMULH A1, 128-bit SIMD vector 0 10 1100 0 SHA1M A1 0 1011 1 VPADD (integer) A1 0110 0 VMAX (integer) A1, 128-bit SIMD vector 0 11 0001 1 VORN (register) A1, 128-bit SIMD vector 0110 1 VMIN (integer) A1, 128-bit SIMD vector 0111 0 VABD (integer) A1, 128-bit SIMD vector 0111 1 VABA A1, 128-bit SIMD vector 0 11 1100 0 SHA1SU0 A1 1 0x 1101 0 VPADD (floating-point) A1 1 0x 1101 1 VMUL (floating-point) A1, 128-bit SIMD vector 1 0x 1110 0 VCGE (register) A2, 128-bit SIMD vector 1 0x 1110 1 VACGE A1, 128-bit SIMD vector 1 0x 1111 0 0 VPMAX (floating-point) A1 1 0x 1111 1 VMAXNM A1, 128-bit SIMD vector 1 00 0001 1 VEOR A1, 128-bit SIMD vector 1001 1 VMUL (integer and polynomial) A1, 128-bit SIMD vector 1 00 1100 0 SHA256H A1 1010 0 0 VPMAX (integer) A1 1 01 0001 1 VBSL A1, 128-bit SIMD vector 1010 0 1 VPMIN (integer) A1 1010 1 UNALLOCATED 1 01 1100 0 SHA256H2 A1 1 1x 1101 0 VABD (floating-point) A1, 128-bit SIMD vector 1 1x 1110 0 VCGT (register) A2, 128-bit SIMD vector 1 1x 1110 1 VACGT A1, 128-bit SIMD vector 1 1x 1111 0 0 VPMIN (floating-point) A1 1 1x 1111 1 VMINNM A1, 128-bit SIMD vector 1 1000 0 VSUB (integer) A1, 128-bit SIMD vector 1 10 0001 1 VBIT A1, 128-bit SIMD vector 1 1000 1 VCEQ (register) A1, 128-bit SIMD vector 1 1001 0 VMLS (integer) A1, 128-bit SIMD vector 1 1011 0 VQRDMULH A1, 128-bit SIMD vector 1 10 1100 0 SHA256SU1 A1 1 1011 1 VQRDMLAH A1, 128-bit SIMD vector 1 11 0001 1 VBIF A1, 128-bit SIMD vector 1 1100 1 VQRDMLSH A1, 128-bit SIMD vector 1 1111 1 0 UNALLOCATED Advanced SIMD two registers, or three registers of different lengths 1 1 1 1 0 0 1 1 1 1 1 1 1 0 Decode fields Instruction page Encoding opc 000 VDUP (scalar) A1, 001 UNALLOCATED 01x UNALLOCATED 1xx UNALLOCATED 1 1 1 1 0 0 1 1 1 1 1 1 0 0 Instruction page Encoding VTBL, VTBX A1, VTBX 1 1 1 1 0 0 1 1 != 11 0 0 Decode fields Instruction page Encoding U opc 0000 VADDL A1 0001 VADDW A1 0010 VSUBL A1 0 0100 VADDHN A1 0011 VSUBW A1 0 0110 VSUBHN A1 0 1001 VQDMLAL A1 0101 VABAL A1 0 1011 VQDMLSL A1 0 1101 VQDMULL A1 0111 VABDL (integer) A1 1000 VMLAL (integer) A1 1010 VMLSL (integer) A1 1 0100 VRADDHN A1 1 0110 VRSUBHN A1 11x0 VMULL (integer and polynomial) A1 1 1001 UNALLOCATED 1 1011 UNALLOCATED 1 1101 UNALLOCATED 1111 UNALLOCATED 1 1 1 1 0 0 1 1 != 11 1 0 Decode fields Instruction page Encoding Q opc 000x VMLA (by scalar) A1, 128-bit SIMD vector 0 0011 VQDMLAL A2 0010 VMLAL (by scalar) A1 0 0111 VQDMLSL A2 010x VMLS (by scalar) A1, 128-bit SIMD vector 0 1011 VQDMULL A2 0110 VMLSL (by scalar) A1 100x VMUL (by scalar) A1, 128-bit SIMD vector 1 0011 UNALLOCATED 1010 VMULL (by scalar) A1 1 0111 UNALLOCATED 1100 VQDMULH A2, 128-bit SIMD vector 1101 VQRDMULH A2, 128-bit SIMD vector 1 1011 UNALLOCATED 1110 VQRDMLAH A2, 128-bit SIMD vector 1111 VQRDMLSH A2, 128-bit SIMD vector 1 1 1 1 0 0 1 1 1 1 1 0 0 Decode fields Instruction page Encoding size opc1 opc2 Q 00 0000 VREV64 A1, 128-bit SIMD vector 00 0001 VREV32 A1, 128-bit SIMD vector 00 0010 VREV16 A1, 128-bit SIMD vector 00 0011 UNALLOCATED 00 010x VPADDL A1, 128-bit SIMD vector 00 0110 0 AESE A1 00 0110 1 AESD A1 00 0111 0 AESMC A1 00 0111 1 AESIMC A1 00 1000 VCLS A1, 128-bit SIMD vector 00 10 0000 VSWP A1, 128-bit SIMD vector 00 1001 VCLZ A1, 128-bit SIMD vector 00 1010 VCNT A1, 128-bit SIMD vector 00 1011 VMVN (register) A1, 128-bit SIMD vector 00 10 1100 1 UNALLOCATED 00 110x VPADAL A1, 128-bit SIMD vector 00 1110 VQABS A1, 128-bit SIMD vector 00 1111 VQNEG A1, 128-bit SIMD vector 01 x000 VCGT (immediate #0) A1, 128-bit SIMD vector 01 x001 VCGE (immediate #0) A1, 128-bit SIMD vector 01 x010 VCEQ (immediate #0) A1, 128-bit SIMD vector 01 x011 VCLE (immediate #0) A1, 128-bit SIMD vector 01 x100 VCLT (immediate #0) A1, 128-bit SIMD vector 01 x110 VABS A1, 128-bit SIMD vector 01 x111 VNEG A1, 128-bit SIMD vector 01 0101 1 SHA1H A1 01 10 1100 1 VCVT (from single-precision to BFloat16, Advanced SIMD) A1 10 0001 VTRN A1, 128-bit SIMD vector 10 0010 VUZP A1, 128-bit SIMD vector 10 0011 VZIP A1, 128-bit SIMD vector 10 0100 0 VMOVN A1 10 0100 1 VQMOVN, VQMOVUN A1, Unsigned result 10 0101 VQMOVN, VQMOVUN A1, Signed result 10 0110 0 VSHLL A2 10 0111 0 SHA1SU1 A1 10 0111 1 SHA256SU0 A1 10 1000 VRINTN (Advanced SIMD) A1, 128-bit SIMD vector 10 1001 VRINTX (Advanced SIMD) A1, 128-bit SIMD vector 10 1010 VRINTA (Advanced SIMD) A1, 128-bit SIMD vector 10 1011 VRINTZ (Advanced SIMD) A1, 128-bit SIMD vector 10 10 1100 1 UNALLOCATED 10 1100 0 VCVT (between half-precision and single-precision, Advanced SIMD) A1, Single-precision to half-precision 10 1101 VRINTM (Advanced SIMD) A1, 128-bit SIMD vector 10 1110 0 VCVT (between half-precision and single-precision, Advanced SIMD) A1, Half-precision to single-precision 10 1110 1 UNALLOCATED 10 1111 VRINTP (Advanced SIMD) A1, 128-bit SIMD vector 11 000x VCVTA (Advanced SIMD) A1, 128-bit SIMD vector 11 001x VCVTN (Advanced SIMD) A1, 128-bit SIMD vector 11 010x VCVTP (Advanced SIMD) A1, 128-bit SIMD vector 11 011x VCVTM (Advanced SIMD) A1, 128-bit SIMD vector 11 10x0 VRECPE A1, 128-bit SIMD vector 11 10x1 VRSQRTE A1, 128-bit SIMD vector 11 10 1100 1 UNALLOCATED 11 11xx VCVT (between floating-point and integer, Advanced SIMD) A1, 128-bit SIMD vector 1 1 1 1 0 0 1 0 1 1 1 0 Instruction page Encoding VEXT (byte elements) A1, 128-bit SIMD vector Advanced SIMD shifts and immediate generation 1 1 1 1 0 0 1 1 0 0 0 0 1 Decode fields Instruction page Encoding cmode op 0xx0 0 VMOV (immediate) A1, 128-bit SIMD vector 0xx0 1 VMVN (immediate) A1, 128-bit SIMD vector 0xx1 0 VORR (immediate) A1, 128-bit SIMD vector 0xx1 1 VBIC (immediate) A1, 128-bit SIMD vector 10x0 0 VMOV (immediate) A3, 128-bit SIMD vector 10x0 1 VMVN (immediate) A2, 128-bit SIMD vector 10x1 0 VORR (immediate) A2, 128-bit SIMD vector 10x1 1 VBIC (immediate) A2, 128-bit SIMD vector 11xx 0 VMOV (immediate) A4, 128-bit SIMD vector 110x 1 VMVN (immediate) A3, 128-bit SIMD vector 1110 1 VMOV (immediate) A5, 128-bit SIMD vector 1111 1 UNALLOCATED 1 1 1 1 0 0 1 1 1 Decode fields Instruction page Encoding U imm3H:L imm3L opc Q != 0000 0000 VSHR A1, 128-bit SIMD vector != 0000 0001 VSRA A1, 128-bit SIMD vector != 0000 000 1010 0 VMOVL A1 != 0000 0010 VRSHR A1, 128-bit SIMD vector != 0000 0011 VRSRA A1, 128-bit SIMD vector != 0000 0111 VQSHL, VQSHLU (immediate) A1, 128-bit SIMD vector, signed result != 0000 1001 0 VQSHRN, VQSHRUN A1, Signed result != 0000 1001 1 VQRSHRN, VQRSHRUN A1, Signed result != 0000 1010 0 VSHLL A1 != 0000 11xx VCVT (between floating-point and fixed-point, Advanced SIMD) A1, 128-bit SIMD vector 0 != 0000 0101 VSHL (immediate) A1, 128-bit SIMD vector 0 != 0000 1000 0 VSHRN A1 0 != 0000 1000 1 VRSHRN A1 1 != 0000 0100 VSRI A1, 128-bit SIMD vector 1 != 0000 0101 VSLI A1, 128-bit SIMD vector 1 != 0000 0110 VQSHL, VQSHLU (immediate) A1, 128-bit SIMD vector, unsigned result 1 != 0000 1000 0 VQSHRN, VQSHRUN A1, Unsigned result 1 != 0000 1000 1 VQRSHRN, VQRSHRUN A1, Unsigned result