UDIV Unsigned Divide Unsigned Divide divides a 32-bit unsigned integer register value by a 32-bit unsigned integer register value, and writes the result to the destination register. The condition flags are not affected. See Divide instructions for more information about this instruction. For more information about the constrained unpredictable behavior of this instruction, see Architectural Constraints on UNPREDICTABLE behaviors. It has encodings from the following instruction sets: A32 ( A1 ) and T32 ( T1 ) . != 1111 0 1 1 1 0 0 1 1 (1) (1) (1) (1) 0 0 0 1 UDIV{<c>}{<q>} {<Rd>,} <Rn>, <Rm> d = UInt(Rd); n = UInt(Rn); m = UInt(Rm); a = UInt(Ra); if d == 15 || n == 15 || m == 15 || a != 15 then UNPREDICTABLE; Ra != '1111' The instruction performs a divide and the register specified by Ra becomes unknown. 1 1 1 1 1 0 1 1 1 0 1 1 (1) (1) (1) (1) 1 1 1 1 UDIV{<c>}{<q>} {<Rd>,} <Rn>, <Rm> d = UInt(Rd); n = UInt(Rn); m = UInt(Rm); a = UInt(Ra); // Armv8-A removes UNPREDICTABLE for R13 if d == 15 || n == 15 || m == 15 || a != 15 then UNPREDICTABLE; Ra != '1111' The instruction performs a divide and the register specified by Ra becomes unknown. <c> See Standard assembler syntax fields. <q> See Standard assembler syntax fields. <Rd> Is the general-purpose destination register, encoded in the "Rd" field. <Rn> Is the first general-purpose source register holding the dividend, encoded in the "Rn" field. <Rm> Is the second general-purpose source register holding the divisor, encoded in the "Rm" field. if ConditionPassed() then EncodingSpecificOperations(); integer result; if UInt(R[m]) == 0 then result = 0; else result = RoundTowardsZero(Real(UInt(R[n])) / Real(UInt(R[m]))); R[d] = result<31:0>;