STLEXD Store-Release Exclusive Doubleword Store-Release Exclusive Doubleword stores a doubleword from two registers to memory if the executing PE has exclusive access to the memory at that address, and returns a status value of 0 if the store was successful, or of 1 if no store was performed. The instruction also has memory ordering semantics as described in Load-Acquire, Store-Release. For more information about support for shared memory see Synchronization and semaphores. For information about memory accesses see Memory accesses. For more information about the constrained unpredictable behavior of this instruction, see Architectural Constraints on UNPREDICTABLE behaviors. Aborts and alignment If a synchronous Data Abort exception is generated by the execution of this instruction: Memory is not updated. <Rd> is not updated. A non word-aligned memory address causes an Alignment fault Data Abort exception to be generated, subject to the following rules: If AArch32.ExclusiveMonitorsPass() returns TRUE, the exception is generated. Otherwise, it is implementation defined whether the exception is generated. If AArch32.ExclusiveMonitorsPass() returns FALSE and the memory address, if accessed, would generate a synchronous Data Abort exception, it is implementation defined whether the exception is generated. If CPSR.DIT is 1, the timing of this instruction is insensitive to the value of the data being loaded or stored. It has encodings from the following instruction sets: A32 ( A1 ) and T32 ( T1 ) . != 1111 0 0 0 1 1 0 1 0 (1) (1) 1 0 1 0 0 1 STLEXD{<c>}{<q>} <Rd>, <Rt>, <Rt2>, [<Rn>] d = UInt(Rd); t = UInt(Rt); t2 = t+1; n = UInt(Rn); if d == 15 || Rt<0> == '1' || t2 == 15 || n == 15 then UNPREDICTABLE; if d == n || d == t || d == t2 then UNPREDICTABLE; d == t d == n The instruction performs the store to an unknown address. Rt<0> == '1' Rt == '1110' The instruction is handled as described in Using R15. 1 1 1 0 1 0 0 0 1 1 0 0 1 1 1 1 STLEXD{<c>}{<q>} <Rd>, <Rt>, <Rt2>, [<Rn>] d = UInt(Rd); t = UInt(Rt); t2 = UInt(Rt2); n = UInt(Rn); if d == 15 || t == 15 || t2 == 15 || n == 15 then UNPREDICTABLE; if d == n || d == t || d == t2 then UNPREDICTABLE; d == t d == n The instruction performs the store to an unknown address. <c> See Standard assembler syntax fields. <q> See Standard assembler syntax fields. <Rd> Is the destination general-purpose register into which the status result of the store exclusive is written, encoded in the "Rd" field. The value returned is: 0If the operation updates memory. 1If the operation fails to update memory. <Rt> For encoding A1: is the first general-purpose register to be transferred, encoded in the "Rt" field. <Rt> must be even-numbered and not R14. <Rt> For encoding T1: is the first general-purpose register to be transferred, encoded in the "Rt" field. <Rt2> For encoding A1: is the second general-purpose register to be transferred. <Rt2> must be <R(t+1)>. <Rt2> For encoding T1: is the second general-purpose register to be transferred, encoded in the "Rt2" field. <Rn> Is the general-purpose base register, encoded in the "Rn" field. if ConditionPassed() then EncodingSpecificOperations(); address = R[n]; // Create doubleword to store such that R[t] will be stored at address and R[t2] at address+4. value = if BigEndian(AccessType_GPR) then R[t]:R[t2] else R[t2]:R[t]; if AArch32.ExclusiveMonitorsPass(address, 8) then MemO[address, 8] = value; R[d] = ZeroExtend('0', 32); else R[d] = ZeroExtend('1', 32);