SDIV Signed Divide Signed Divide divides a 32-bit signed integer register value by a 32-bit signed integer register value, and writes the result to the destination register. The condition flags are not affected. For more information about the constrained unpredictable behavior of this instruction, see Architectural Constraints on UNPREDICTABLE behaviors. Overflow If the signed integer division 0x80000000 / 0xFFFFFFFF is performed, the pseudocode produces the intermediate integer result +2³¹, that overflows the 32-bit signed integer range. No indication of this overflow case is produced, and the 32-bit result written to <Rd> must be the bottom 32 bits of the binary representation of +2³¹. So the result of the division is 0x80000000. It has encodings from the following instruction sets: A32 ( A1 ) and T32 ( T1 ) . != 1111 0 1 1 1 0 0 0 1 (1) (1) (1) (1) 0 0 0 1 SDIV{<c>}{<q>} {<Rd>,} <Rn>, <Rm> d = UInt(Rd); n = UInt(Rn); m = UInt(Rm); a = UInt(Ra); if d == 15 || n == 15 || m == 15 || a != 15 then UNPREDICTABLE; Ra != '1111' The instruction executes as described, and the register specified by Ra becomes unknown. 1 1 1 1 1 0 1 1 1 0 0 1 (1) (1) (1) (1) 1 1 1 1 SDIV{<c>}{<q>} {<Rd>,} <Rn>, <Rm> d = UInt(Rd); n = UInt(Rn); m = UInt(Rm); a = UInt(Ra); // Armv8-A removes UNPREDICTABLE for R13 if d == 15 || n == 15 || m == 15 || a != 15 then UNPREDICTABLE; Ra != '1111' The instruction executes as described, and the register specified by Ra becomes unknown. <c> See Standard assembler syntax fields. <q> See Standard assembler syntax fields. <Rd> Is the general-purpose destination register, encoded in the "Rd" field. <Rn> Is the first general-purpose source register holding the dividend, encoded in the "Rn" field. <Rm> Is the second general-purpose source register holding the divisor, encoded in the "Rm" field. if ConditionPassed() then EncodingSpecificOperations(); integer result; if SInt(R[m]) == 0 then result = 0; else result = RoundTowardsZero(Real(SInt(R[n])) / Real(SInt(R[m]))); R[d] = result<31:0>;