LSL (immediate)
Logical Shift Left (immediate)
Logical Shift Left (immediate) shifts a register value left by an immediate number of bits, shifting in zeros, and writes the result to the destination register.
MOV, MOVS (register)
It has encodings from the following instruction sets:
A32 (
A1
)
and
T32 (
T2
and
T3
)
.
!= 1111
0
0
0
1
1
0
1
0
(0)
(0)
(0)
(0)
!= 00000
0
0
0
LSL{<c>}{<q>} {<Rd>,} <Rm>, #<imm>
MOV{<c>}{<q>} <Rd>, <Rm>, LSL #<imm>
Unconditionally
0
0
0
0
0
!= 00000
LSL<c>{<q>} {<Rd>,} <Rm>, #<imm>
MOV<c>{<q>} <Rd>, <Rm>, LSL #<imm>
InITBlock()
1
1
1
0
1
0
1
0
0
1
0
0
1
1
1
1
(0)
0
0
LSL<c>.W {<Rd>,} <Rm>, #<imm>
LSL{<c>}{<q>} {<Rd>,} <Rm>, #<imm>
MOV{<c>}{<q>} <Rd>, <Rm>, LSL #<imm>
Unconditionally
<c>
See Standard assembler syntax fields.
<q>
See Standard assembler syntax fields.
<Rd>
For encoding A1: is the general-purpose destination register, encoded in the "Rd" field. Arm deprecates using the PC as the destination register, but if the PC is used, the instruction is a branch to the address calculated by the operation. This is an interworking branch, see Pseudocode description of operations on the AArch32 general-purpose registers and the PC.
<Rd>
For encoding T2 and T3: is the general-purpose destination register, encoded in the "Rd" field.
<Rm>
For encoding A1: is the general-purpose source register, encoded in the "Rm" field. The PC can be used, but this is deprecated.
<Rm>
For encoding T2 and T3: is the general-purpose source register, encoded in the "Rm" field.
<imm>
For encoding A1: is the shift amount, in the range 0 to 31, encoded in the "imm5" field as <imm> modulo 32.
<imm>
For encoding T2: is the shift amount, in the range 1 to 31, encoded in the "imm5" field as <amount> modulo 32.
<imm>
For encoding T3: is the shift amount, in the range 0 to 31, encoded in the "imm3:imm2" field as <imm> modulo 32.